TRANSCEND TS512MDOM44H-S

TTrraannsscceenndd 4444--P
Piinn IID
DE
E FFllaasshh M
Moodduullee ((H
Hoorriizzoonnttaall))
TTS
S112288M
M ~~ 44G
GD
DO
OM
M4444H
H--S
S
Description
Features
With an IDE interface and strong data retention ability,
•
RoHS compliant products
44-Pin IDE Flash Modules are ideal for use in the
•
Storage Capacity: 128MB ~ 4GB
harsh environments where Industrial PCs, Set-Top
•
Operating Voltage: 3.3V ±5% or 5V ±10%
Boxes, etc. are used.
•
Operating Temperature: 0°C ~ 70°C
•
Endurance: 2,000,000 Program/Erase cycles
•
MTBF: 1,000,000 hours
•
Durability of Connector: 10,000 times
•
Fully compatible with devices and OS that support the
IDE standard (pitch = 2.00mm)
•
Built-in ECC function assures high reliability of data
transfer
•
Supports up to Ultra DMA Mode 4
•
Supports PIO Mode 6
Placement
Transcend Information Inc.
Dimensions
Side
Millimeters
Inches
A
46.00 ± 0.40
1.81 ± 0.016
B
28.00 ± 0.20
1.10 ± 0.008
C
6.00 ± 0.50
0.24 ± 0.020
1
Ver 1.0
TTrraannsscceenndd 4444--P
Piinn IID
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E FFllaasshh M
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TTS
S112288M
M ~~ 44G
GD
DO
OM
M4444H
H--S
S
Pin Definition
Pin Assignments
Pin
No.
Pin
No.
Pin
Name
01 -RESET 12
02
GND
13
03
HD7
14
04
HD8
15
05
HD6
16
06
HD9
17
07
HD5
18
HD12
HD2
HD13
HD1
HD14
HD0
HD15
08
09
10
11
Pin
Name
HD10
HD4
HD11
HD3
Pin
Pin
No Name
23 IOWB
24 GND
25 IORB
26 GND
27 IORDY
28
NC
29 -DMAC
K
19
GND 30 GND
20
NC
31 IREQ
21 DMARQ 32 IOIS16B
22
GND 33 HA1
Pin
No.
Symbol
Pin
Name
34 PDIAGB
35
HA0
36
HA2
37 CE1B
38 CE2B
39 DASPB
40
GND
HD0 ~ HD15
Data Bus (Bi-directional)
HA0 ~ HA2
Address Bus (Input)
-RESET
Device Reset (Input)
IORB
Device I/O Read (Input)
IOWB
Device I/O Write (Input)
IOIS16B
Transfer Type 8/16 bit (Output)
CE1B, CE2B
Chip Select (Input)
PDIAGB
Pass Diagnostic (Bi-directional)
DMARQ
Disk Active/Slave Present
(Bi-directional)
DMA request
DMACK-
DMA acknowledge
IREQ
Interrupt Request (Output)
NC
No Connection
GND
Ground
VCC
Vcc Power Input
DASPB
41
42
43
44
VCC
VCC
GND
GND
Function
Pin Layout
Pin1
Bulge
Pin2
Transcend Information Inc.
Pin43
Pin44
2
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TTS
S112288M
M ~~ 44G
GD
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M4444H
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S
Block Diagram
With 1 pcs of Flash Memory:
With 2 pcs of Flash Memory:
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TTS
S112288M
M ~~ 44G
GD
DO
OM
M4444H
H--S
S
Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
VDD-VSS
DC Power Supply
-0.6
+6
V
Ta
Operating Temperature
0
+70
°C
Tst
Storage Temperature
-40
+85
°C
Recommended Operating Conditions
Symbol
Parameter
Min
Max
Units
VDD
Power supply
3.0
5.5
V
VIN
Input voltage
0
VDD+0.3
V
Ta
Operating Temperature
0
+70
°C
DC Characteristics
(Ta=0 oC to +70 oC, Vcc = 5.0V ± 10%)
Parameter
Symbol
Min
Max
Unit
Remark
Supply Voltage
High level output voltage
Low level output voltage
VCC
VOH
VOL
4.5
VCC-0.8
--
5.5
-0.8
High level input voltage
VIH
4.0
--
Non-schmitt trigger
2.92
--
Low level input voltage
VIL
--
0.8
--
1.70
V
V
V
V
V
V
V
Symbol
Min
Max
Unit
Remark
Supply Voltage
High level output voltage
Low level output voltage
VCC
VOH
VOL
3.135
VCC-0.8
--
3.465
-0.8
High level input voltage
VIH
2.4
--
Non-schmitt trigger
2.05
--
Low level input voltage
VIL
V
V
V
V
V
V
V
Schmitt trigger1
Non-schmitt trigger
Schmitt trigger1
(Ta=0 oC to +70 oC, Vcc = 3.3V ± 5%)
Parameter
Transcend Information Inc.
--
0.6
--
1.25
Schmitt trigger1
Non-schmitt trigger
Schmitt trigger1
4
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TTS
S112288M
M ~~ 44G
GD
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M4444H
H--S
S
Transcend Information Inc.
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Ver 1.0
TTrraannsscceenndd 4444--P
Piinn IID
DE
E FFllaasshh M
Moodduullee ((H
Hoorriizzoonnttaall))
TTS
S112288M
M ~~ 44G
GD
DO
OM
M4444H
H--S
S
True IDE PIO Mode Read/Write Timing
t0
t1
t2
t2
t2i
t3
t4
t5
t6
t6Z
t7
t8
t9
tRD
Item
Mode
0
600
Mode
1
383
Mode
2
240
Mode
3
180
Mode
4
120
Mode
5
100
Mode
6
80
Address Valid to -IORD/-IOWR setup (min)
70
50
30
30
25
15
10
165
290
-60
30
50
5
30
90
60
20
125
290
-45
20
35
5
30
50
45
15
100
290
-30
15
20
5
30
40
30
10
80
80
70
30
10
20
5
30
N/A
N/A
10
70
70
25
20
10
20
5
30
N/A
N/A
10
65
65
25
20
5
15
5
20
N/A
N/A
10
55
55
20
15
5
10
5
20
N/A
N/A
10
0
0
0
0
0
0
0
35
1250
5
35
1250
5
35
1250
5
35
1250
5
35
1250
5
N/A5
N/A5
N/A5
N/A5
N/A5
N/A5
Cycle time (min) 1
-IORD/-IOWR (min)
1
-IORD/-IOWR (min) Register (8 bit)
-IORD/-IOWR recovery time (min)
-IOWR data setup (min)
-IOWR data hold (min)
-IORD data setup (min)
-IORD data hold (min)
-IORD data tristate (max)2
Address valid to IOCS16 assertion (max) 4
Address valid to IOCS16 released (max) 4
-IORD/-IOWR to address valid hold
Read Data Valid to IORDY active (min), if
IORDY initially low after tA
IORDY Setup time 3
tA
tB IORDY Pulse Width (max)
tC IORDY assertion to release (max)
Notes: All timings are in nanoseconds. The maximum load on -IOCS16 is 1 LSTTL with a 50 pF (40pF below
120nsec Cycle Time) total load. All times are in nanoseconds. Minimum time from -IORDY high to -IORD
high is 0 nsec, but minimum -IORD width shall still be met.
(1) t0 is the minimum total cycle time, t2 is the minimum command active time, and t2i is the minimum
command recovery time or command inactive time. The actual cycle time equals the sum of the actual
command active time and the actual command inactive time. The three timing requirements of t0, t2, and
t2i shall be met. The minimum total cycle time requirement is greater than the sum of t2 and t2i. This means
a host implementation can lengthen either or both t2 or t2i to ensure that t0 is equal to or greater than the
value reported in the device’s identify device data.
(2) This parameter specifies the time from the negation edge of -IORD to the time that the data bus is
released by the device.
(3) The delay from the activation of -IORD or -IOWR until the state of IORDY is first sampled. If IORDY is
inactive then the host shall wait until IORDY is active before the PIO cycle can be completed. If the device
is not driving IORDY negated at tA after the activation of -IORD or -IOWR, then t5 shall be met and tRD is
not applicable. If the device is driving IORDY negated at the time tA after the activation of -IORD or -IOWR,
then tRD shall be met and t5 is not applicable.
(4) t7 and t8 apply only to modes 0, 1 and 2. For other modes, this signal is not valid.
(5) IORDY is not supported in this mode.
Transcend Information Inc.
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Piinn IID
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E FFllaasshh M
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Hoorriizzoonnttaall))
TTS
S112288M
M ~~ 44G
GD
DO
OM
M4444H
H--S
S
True IDE PIO Mode Timing Diagram
Figure 1: True IDE PIO Mode Timing Diagram
Notes:
(1) Device address consists of -CS0, -CS1, and A[02::00]
(2) Data consists of D[15::00] (16-bit) or D[07::00] (8 bit)
(3) -IOCS16 is shown for PIO modes 0, 1 and 2. For other modes, this signal is ignored.
(4) The negation of IORDY by the device is used to extend the PIO cycle. The determination of whether the cycle
is to be extended is made by the host after tA from the assertion of -IORD or -IOWR. The assertion and negation
of IORDY is described in the following three cases:
(4-1) Device never negates IORDY: No wait is generated.
(4-2) Device starts to drive IORDY low before tA, but causes IORDY to be asserted before tA: No wait
generated.
(4-3) Device drives IORDY low before tA: wait generated. The cycle completes after IORDY is reasserted. For
cycles where a wait is generated and -IORD is asserted, the device shall place read data on D15-D00 for
tRD before causing IORDY to be asserted.
Transcend Information Inc.
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TTS
S112288M
M ~~ 44G
GD
DO
OM
M4444H
H--S
S
True IDE Multiword DMA Mode Read/Write Timing Specification
Mode 0
(ns)
480
Mode 1
(ns)
150
Mode 2
(ns)
120
Mode 3
(ns)
100
Mode 4
(ns)
80
-IORD / -IOWR asserted width(min) 1
215
80
70
65
55
-IORD data access (max)
150
60
50
50
45
5
5
5
5
5
-IORD/-IOWR data setup (min)
100
30
20
15
10
-IOWR data hold (min)
20
15
10
5
5
DMACK to –IORD/-IOWR setup (min)
0
0
0
0
0
-IORD / -IOWR to -DMACK hold (min)
20
5
5
5
5
-IORD negated width (min) 1
50
50
25
25
20
215
50
25
25
20
-IORD to DMARQ delay (max)
120
40
35
35
35
-IOWR to DMARQ delay (max)
40
40
35
35
35
CS(1:0) valid to –IORD / -IOWR
50
30
25
10
5
CS(1:0) hold
15
10
10
10
10
-DMACK
20
25
25
25
25
Item
t0
tD
tE
tF
tG
tH
tI
tJ
tKR
tKW
tLR
tLW
tM
tN
tZ
Cycle time (min) 1
-IORD data hold (min)
-IOWR negated width (min)
1
Notes:
(1) t0 is the minimum total cycle time and tD is the minimum command active time, while tKR and tKW are the
minimum command recovery time or command inactive time for input and output cycles respectively. The
actual cycle time equals the sum of the actual command active time and the actual command inactive time.
The three timing requirements of t0, tD, tKR, and tKW shall be met. The minimum total cycle time requirement
is greater than the sum of tD and tKR or tKW.for input and output cycles respectively. This means a host
implementation can lengthen either or both of tD and either of tKR, and tKW as needed to ensure that t0 is
equal to or greater than the value reported in the device’s identify device data.
Transcend Information Inc.
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TTrraannsscceenndd 4444--P
Piinn IID
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E FFllaasshh M
Moodduullee ((H
Hoorriizzoonnttaall))
TTS
S112288M
M ~~ 44G
GD
DO
OM
M4444H
H--S
S
True IDE Multiword DMA Mode Read/Write Timing Diagram
Figure 2: True IDE Multiword DMA Mode Read/Write Timing Diagram
Notes:
(1) If the Card cannot sustain continuous, minimum cycle time DMA transfers, it may negate DMARQ within the
time specified from the start of a DMA transfer cycle to suspend the DMA transfers in progress and reassert the
signal at a later time to continue the DMA operation.
(2) This signal may be negated by the host to suspend the DMA transfer in progress.
Transcend Information Inc.
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Hoorriizzoonnttaall))
TTS
S112288M
M ~~ 44G
GD
DO
OM
M4444H
H--S
S
Ultra DMA Mode Read/Write Timing Specification
Ultra DMA is an optional data transfer protocol used with the READ DMA, and WRITE DMA,
commands. When this protocol is enabled, the Ultra DMA protocol shall be used instead of the Multiword
DMA protocol when these commands are issued by the host. This protocol applies to the Ultra DMA data
burst only. When this protocol is used there are no changes to other elements of the ATA protocol.
UDMA Signal
Type
DMARQ
DMACK
STOP
HDMARDY(R)
HSTROBE(W)
DDMARDY(W)
DSTROBE(R)
DATA
ADDRESS
CSEL
INTRQ
Output
Input
Input
Card Select
Input
Output
Bidir
Input
input
Output
Input
TRUE IDE MODE
UDMA
DMARQ
-DMACK
STOP1
-HDMARDY1,2
HSTROBE(W)1,3,4
-DDMARDY(W)1,3
DSTROBE(R)1,2,4
D[15:00]
A[02:00]5
-CSEL
INTRQ
-CS0
-CS1
Notes: 1) The UDMA interpretation of this signal is valid only during an Ultra DMA data burst.
2) The UDMA interpretation of this signal is valid only during and Ultra DMA data burst during a DMA Read command.
3) The UDMA interpretation of this signal is valid only during an Ultra DMA data burst during a DMA Write command.
4) The HSTROBE and DSTROBE signals are active on both the rising and the falling edge.
5) Address lines 03 through 10 are not used in True IDE mode.
Several signal lines are redefined to provide different functions during an Ultra DMA data burst.
These lines assume their UDMA definitions when:
1. An Ultra DMA mode is selected, and
2. A host issues a READ DMA, or a WRITE DMA command requiring data transfer, and
3. The device asserts (-)DMARQ, and
4. The host asserts (-)DMACK.
These signal lines revert back to the definitions used for non-Ultra DMA transfers upon the negation
of -DMACK by the host at the termination of an Ultra DMA data burst.
With the Ultra DMA protocol, the STROBE signal that latches data from D[15:00] is generated by the
same agent (either host or device) that drives the data onto the bus. Ownership of D[15:00] and this data
strobe signal are given either to the device during an Ultra DMA data-in burst or to the host for an Ultra
Transcend Information Inc.
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E FFllaasshh M
Moodduullee ((H
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TTS
S112288M
M ~~ 44G
GD
DO
OM
M4444H
H--S
S
DMA data-out burst.
During an Ultra DMA data burst a sender shall always drive data onto the bus, and, after a sufficient
time to allow for propagation delay, cable settling, and setup time, the sender shall generate a STROBE
edge to latch the data. Both edges of STROBE are used for data transfers so that the frequency of
STROBE is limited to the same frequency as the data.
Words in the IDENTIFY DEVICE data indicate support of the Ultra DMA feature and the Ultra DMA
modes the device is capable of supporting. The Set transfer mode subcommand in the SET FEATURES
command shall be used by a host to select the Ultra DMA mode at which the system operates. The Ultra
DMA mode selected by a host shall be less than or equal to the fastest mode of which the device is
capable. Only one Ultra DMA mode shall be selected at any given time. All timing requirements for a
selected Ultra DMA mode shall be satisfied. Devices supporting any Ultra DMA mode shall also support
all slower Ultra DMA modes.
An Ultra DMA capable device shall retain the previously selected Ultra DMA mode after executing a
software reset sequence or the sequence caused by receipt of a DEVICE RESET command if a SET
FEATURES disable reverting to defaults command has been issued. The device may revert to a
Multiword DMA mode if a SET FEATURES enable reverting to default has been issued. An Ultra DMA
capable device shall clear any previously selected Ultra DMA mode and revert to the default non-Ultra
DMA modes after executing a power-on or hardware reset.
Both the host and device perform a CRC function during an Ultra DMA data burst. At the end of an
Ultra DMA data burst the host sends its CRC data to the device. The device compares its CRC data to
the data sent from the host. If the two values do not match, the device reports an error in the error register.
If an error occurs during one or more Ultra DMA data bursts for any one command, the device shall report
the first error that occurred. If the device detects that a CRC error has occurred before data transfer for
the command is complete, the device may complete the transfer and report the error or abort the
command and report the error.
NOTE − If a data transfer is terminated before completion, the assertion of INTRQ should be passed
through to the host software driver regardless of whether all data requested by the command has been
transferred.
Transcend Information Inc.
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Hoorriizzoonnttaall))
TTS
S112288M
M ~~ 44G
GD
DO
OM
M4444H
H--S
S
Ultra DMA Data Burst Timing Requirements
Name
t2CYCTYP
tCYC
t2CYC
tDS
tDH
tDVS
tDVH
tCS
tCH
tCVS
tCVH
tZFS
tDZFS
tFS
tLI
tMLI
tUI
tAZ
tZAH
tZAD
tENV
tRFS
tRP
tIORDYZ
tZIORDY
tACK
tSS
UDMA Mode 0 UDMA Mode 1 UDMA Mode 2
Min
240
112
230
15.0
5.0
70.0
6.2
15.0
5.0
70.0
6.2
0
70.0
0
20
0
Max
230
150
Min
160
73
153
10.0
5.0
48.0
6.2
10.0
5.0
48.0
6.2
0
48.0
0
20
0
10
20
0
20
70
75
160
Max
200
150
0
20
0
10
20
0
20
70
70
125
20
0
20
50
Min
120
54
115
7.0
5.0
31.0
6.2
7.0
5.0
31.0
6.2
0
31.0
170
150
Min
90
39
86
7.0
5.0
20.0
6.2
7.0
5.0
20.0
6.2
0
20.0
0
20
0
10
20
0
20
70
60
100
20
0
20
50
Max
UDMA Mode 3
Max
130
100
10
20
0
20
55
60
100
20
0
20
50
20
0
20
50
UDMA Mode 4 Measure location
(See Note 2)
Min
Max
60
Sender
25
Note 3
57
Sender
5.0
Recipient
5.0
Recipient
6.7
Sender
6.2
Sender
5.0
Device
5.0
Device
6.7
Host
6.2
Host
0
Device
6.7
Sender
120 Device
0
100 Note 4
20
Host
0
Host
10 Note 5
20
Host
0
Device
20
55 Host
60 Sender
100
Recipient
20 Device
0
Device
20
Host
50
Sender
Notes: All Timings in ns
(1) All timing measurement switching points (low to high and high to low) shall be taken at 1.5 V.
(2) All signal transitions for a timing parameter shall be measured at the connector specified in the measurement
location column. For example, in the case of tRFS, both STROBE and -DMARDY transitions are measured at the
sender connector.
(3) The parameter tCYC shall be measured at the recipient’s connector farthest from the sender.
(4) The parameter tLI shall be measured at the connector of the sender or recipient that is responding to an
incoming transition from the recipient or sender respectively. Both the incoming signal and the outgoing
response shall be measured at the same connector.
(5) The parameter tAZ shall be measured at the connector of the sender or recipient that is driving the bus but must
release the bus to allow for a bus turnaround.
(6) See Page 14 the AC Timing requirements in Ultra DMA AC Signal Requirements.
Transcend Information Inc.
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M ~~ 44G
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M4444H
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S
Ultra DMA Data Burst Timing Descriptions
Name
t2CYCTYP
tCYC
t2CYC
tDS
tDH
tDVS
tDVH
tCS
tCH
tCVS
tCVH
tZFS
tDZFS
tFS
tLI
tMLI
tUI
tAZ
tZAH
tZAD
tENV
tRFS
tRP
tIORDYZ
tZIORDY
tACK
tSS
Comment
Notes
Typical sustained average two cycle time
Cycle time allowing for asymmetry and clock variations (from STROBE edge to STROBE
edge)
Two cycle time allowing for clock variations (from rising edge to next rising edge or from
falling edge to next falling edge of STROBE)
Data setup time at recipient (from data valid until STROBE edge)
2,
Data hold time at recipient (from STROBE edge until data may become invalid)
2,
Data valid setup time at sender (from data valid until STROBE edge)
3
Data valid hold time at sender (from STROBE edge until data may become invalid)
3
CRC word setup time at device
2
CRC word hold time device
2
CRC word valid setup time at host (from CRC valid until -DMACK negation)
3
CRC word valid hold time at sender (from -DMACK negation until CRC may become invalid) 3
Time from STROBE output released-to-driving until the first transition of critical timing.
Time from data output released-to-driving until the first transition of critical timing.
First STROBE time (for device to first negate DSTROBE from STOP during a data in burst)
Limited interlock time
1
Interlock time with minimum
1
Unlimited interlock time
1
Maximum time allowed for output drivers to release (from asserted or negated)
Minimum delay time required for output
drivers to assert or negate (from released)
Envelope time (from -DMACK to STOP and -HDMARDY during data in burst initiation and
from DMACK to STOP during data out burst initiation)
Ready-to-final-STROBE time (no STROBE edges shall be sent this long after negation of
-DMARDY)
Ready-to-pause time (that recipient shall wait to pause after negating -DMARDY)
Maximum time before releasing IORDY
Minimum time before driving IORDY
4,
Setup and hold times for -DMACK (before assertion or negation)
Time from STROBE edge to negation of DMARQ or assertion of STOP (when sender
terminates a burst)
Notes:
(1) The parameters tUI, tMLI (in Page 19: Ultra DMA Data-In Burst Device Termination Timing and Page 20: Ultra DMA Data-In
Burst Host Termination Timing), and tLI indicate sender-to-recipient or recipient-to-sender interlocks,i.e., one agent
(either sender or recipient) is waiting for the other agent to respond with a signal before proceeding.tUI is an unlimited
interlock that has no maximum time value. tMLI is a limited time-out that has a defined minimum. tLI is a limited time-out
that has a defined maximum.
(2) 80-conductor cabling (see see ATA specification :Annex A)) shall be required in order to meet setup (tDS, tCS) and hold (tDH,
tCH) times in modes greater than 2.
(3) Timing for tDVS, tDVH, tCVS and tCVH shall be met for lumped capacitive loads of 15 and 40 pF at the connector where
the Data and STROBE signals have the same capacitive load value. Due to reflections on the cable, these timing
measurements are not valid in a normally functioning system.
(4) For all timing modes the parameter tZIORDY may be greater than tENV due to the fact that the host has a pull-up on IORDYgiving it a known state when released.
Transcend Information Inc.
13
Ver 1.0
TTrraannsscceenndd 4444--P
Piinn IID
DE
E FFllaasshh M
Moodduullee ((H
Hoorriizzoonnttaall))
TTS
S112288M
M ~~ 44G
GD
DO
OM
M4444H
H--S
S
Ultra DMA Sender and Recipient IC Timing Requirements
Name
UDMA Mode 0 (ns) UDMA Mode 1 (ns) UDMA Mode 2 (ns) UDMA Mode 3 (ns) UDMA Mode 4 (ns)
Min
tDSIC
tDHIC
tDVSIC
tDVHIC
tDSIC
tDHIC
tDVSIC
tDVHIC
Max
14.7
4.8
72.9
9.0
Min
Max
9.7
4.8
50.9
9.0
Min
6.8
4.8
33.9
9.0
Max
Min
Max
6.8
4.8
22.6
9.0
Min
Max
4.8
4.8
9.5
9.0
Recipient IC data setup time (from data valid until STROBE edge) (see note 2)
Recipient IC data hold time (from STROBE edge until data may become invalid) (see note 2)
Sender IC data valid setup time (from data valid until STROBE edge) (see note 3)
Sender IC data valid hold time (from STROBE edge until data may become invalid) (see note 3)
Notes:
(1) All timing measurement switching points(low to high and high to low) shall be taken at 1.5 V.
(2) The correct data value shall be captured by the recipient given input data with a slew rate of 0.4 V/ns rising and
falling and the input STROBE with a slew rate of 0.4 V/ns rising and falling at tDSIC and tDHIC timing (as measured
through 1.5 V).
(3) The parameters tDVSIC and tDVHIC shall be met for lumped capacitive loads of 15 and 40 pF at the IC where all
signals have the same capacitive load value. Noise that may couple onto the output signals from external
sources has not been included in these values.
Ultra DMA AC Signal Requirements
Name
SRISE
SFALL
Comment
Rising Edge Slew Rate for any signal
Falling Edge Slew Rate for any signal
Min[V/ns]
Max [V/ns]
1.25
1.25
Note
1
1
Note:
(1) The sender shall be tested while driving an 18 inch long, 80 conductor cable with PVC insulation material. The
signal under test shall be cut at a test point so that it has not trace, cable or recipient loading after the test point.
All other signals should remain connected through to the recipient. The test point may be located at any point
between the sender’s series termination resistor and one half inch or less of conductor exiting the connector.
If the test point is on a cable conductor rather than the PCB, an adjacent ground conductor shall also be cut
within one half inch of the connector.
The test load and test points should then be soldered directly to the exposed source side connectors. The test
loads consist of a 15 pF or a 40 pF, 5%, 0.08 inch by 0.05 inch surface mount or smaller size capacitor from the
test point to ground. Slew rates shall be met for both capacitor values.
Measurements shall be taken at the test point using a <1 pF, >100 Kohm, 1 Ghz or faster probe and a 500
MHz or faster oscilloscope. The average rate shall be measured from 20% to 80% of the settled VOH level with
data transitions at least 120 nsec apart. The settled VOH level shall be measured as the average output high
level under the defined testing conditions from 100 nsec after 80% of a rising edge until 20% of the subsequent
falling edge.
Transcend Information Inc.
14
Ver 1.0
TTrraannsscceenndd 4444--P
Piinn IID
DE
E FFllaasshh M
Moodduullee ((H
Hoorriizzoonnttaall))
TTS
S112288M
M ~~ 44G
GD
DO
OM
M4444H
H--S
S
Initiating an Ultra DMA Data-In Burst
(a) An Ultra DMA Data-In burst is initiated by following the steps lettered below. The timing diagram is
shown in below: Ultra DMA Data-In Burst Initiation Timing. The associated timing parameters are
specified in Page 12: Ultra DMA Data Burst Timing Requirements and are described in Page 13: Ultra
DMA Data Burst Timing Descriptions.
(b) The following steps shall occur in the order they are listed unless otherwise specifically allowed:
(c) The host shall keep -DMACK in the negated state before an Ultra DMA data burst is initiated.
(d) The device shall assert DMARQ to initiate an Ultra DMA data burst. After assertion of DMARQ the
device shall not negate DMARQ until after the first negation of DSTROBE.
(e) Steps (c), (d), and (e) may occur in any order or at the same time. The host shall assert STOP.
(f) The host shall negate -HDMARDY.
(g) In True IDE mode, the host shall not assert -CS0, -CS1 and A[02:00].
(h) Steps (c), (d), and (e) shall have occurred at least tACK before the host asserts -DMACK. The host
shall keep -DMACK asserted until the end of an Ultra DMA data burst.
(i) The host shall release D[15:00] within tAZ after asserting -DMACK.
(j) The device may assert DSTROBE tZIORDY after the host has asserted -DMACK. While operating in
True IDE mode, once the device has driven DSTROBE, the device shall not release DSTROBE until
after the host has negated -DMACK at the end of an Ultra DMA data burst.
(k) The host shall negate STOP and assert -HDMARDY within tENV after asserting -DMACK. After
negating STOP and asserting -HDMARDY, the host shall not change the state of either signal until
after receiving the first transition of DSTROBE from the device (i.e., after the first data word has been
received).
(l) The device shall drive D[15:00] no sooner than tZAD after the host has asserted -DMACK, negated
STOP, and asserted -HDMARDY.
(m) The device shall drive the first word of the data transfer onto D[15:00]. This step may occur when the
device first drives D[15:00] in step (j).
(n) To transfer the first word of data the device shall negate DSTROBE within tFS after the host has
negated STOP and asserted -HDMARDY. The device shall negate DSTROBE no sooner than tDVS
after driving the first word of data onto D[15:00].
Transcend Information Inc.
15
Ver 1.0
TTrraannsscceenndd 4444--P
Piinn IID
DE
E FFllaasshh M
Moodduullee ((H
Hoorriizzoonnttaall))
TTS
S112288M
M ~~ 44G
GD
DO
OM
M4444H
H--S
S
ALL WAVEFORMS IN THIS DIAGRAM ARE SHOWN WITH THE ASSERTED STATE HIGH.
NEGATIVE TRUE SIGNALS APPEAR INVERTED ON THE BUS RELATIVE TO THE DIAGRAM.
Notes:
The definitions for the IORDY:-DDMARDY:DSTROBE, -IORD: -HDMARDY:HSTROBE, and -IOWR:STOP
signal lines are not in effect until DMARQ and -DMACK are asserted. A[02:00], -CS0 & -CS1 are True IDE mode
signal definitions.
Transcend Information Inc.
16
Ver 1.0
TTrraannsscceenndd 4444--P
Piinn IID
DE
E FFllaasshh M
Moodduullee ((H
Hoorriizzoonnttaall))
TTS
S112288M
M ~~ 44G
GD
DO
OM
M4444H
H--S
S
Sustaining an Ultra DMA Data-In Burst
An Ultra DMA Data-In burst is sustained by following the steps lettered below. The timing diagram
is shown in below: Sustained Ultra DMA Data-In Burst Timing. The timing parameters are specified in
Page 12: Ultra DMA Data Burst Timing Requirements and are described in Page 13: Ultra DMA Data
Burst Timing Descriptions.
The following steps shall occur in the order they are listed unless otherwise specifically allowed:
a) The device shall drive a data word onto D[15:00].
b) The device shall generate a DSTROBE edge to latch the new word no sooner than tDVS after changing
the state of D[15:00]. The device shall generate a DSTROBE edge no more frequently than tCYC for the
selected Ultra DMA mode. The device shall not generate two rising or two falling DSTROBE edges
more frequently than 2tcyc for the selected Ultra DMA mode.
c) The device shall not change the state of D[15:00] until at least tDVH after generating a DSTROBE edge
to latch the data.
d) The device shall repeat steps (a), (b), and (c) until the data transfer is complete or an Ultra DMA data
burst is paused, whichever occurs first.
Notes: D[15:00] and DSTROBE signals are shown at both the host and the device to emphasize that cable settling
time as well as cable propagation delay shall not allow the data signals to be considered stable at the host
until some time after they are driven by the device.
Transcend Information Inc.
17
Ver 1.0
TTrraannsscceenndd 4444--P
Piinn IID
DE
E FFllaasshh M
Moodduullee ((H
Hoorriizzoonnttaall))
TTS
S112288M
M ~~ 44G
GD
DO
OM
M4444H
H--S
S
Host Pausing an Ultra DMA Data-In Burst
The host pauses a Data-In burst by following the steps lettered below. A timing diagram is shown in
below: Ultra DMA Data-In Burst Host Pause Timing. The timing parameters are specified in Page 12:
Ultra DMA Data Burst Timing Requirements and are described in Page 13: Ultra DMA Data Burst Timing
Descriptions.
The following steps shall occur in the order they are listed unless otherwise specifically allowed:
(a) The host shall not pause an Ultra DMA data burst until at least one data word of an Ultra DMA data
burst has been transferred.
(b) The host shall pause an Ultra DMA data burst by negating -HDMARDY.
(c) The device shall stop generating DSTROBE edges within tRFS of the host negating -HDMARDY.
(d) While operating in Ultra DMA modes 2, 1, or 0 the host shall be prepared to receive zero, one or two
additional data words after negating -HDMARDY. While operating in Ultra DMA modes 4 or 3 the host
shall be prepared to receive zero, one, two or three additional data words. The additional data words
are a result of cable round trip delay and tRFS timing for the device.
(e) The host shall resume an Ultra DMA data burst by asserting -HDMARDY.
ALL WAVEFORMS IN THIS DIAGRAM ARE SHOWN WITH THE ASSERTED STATE HIGH.
NEGATIVE TRUE SIGNALS APPEAR INVERTED ON THE BUS RELATIVE TO THE DIAGRAM.
Notes:
(1) The host may assert STOP to request termination of the Ultra DMA data burst no sooner than tRP after
-HDMARDY is negated.
(2) After negating -HDMARDY, the host may receive zero, one, two, or three more data words from the device.
(3) The bus polarity of the (-) DMARQ and (-)DMACK signals is dependent on the active interface mode.
Transcend Information Inc.
18
Ver 1.0
TTrraannsscceenndd 4444--P
Piinn IID
DE
E FFllaasshh M
Moodduullee ((H
Hoorriizzoonnttaall))
TTS
S112288M
M ~~ 44G
GD
DO
OM
M4444H
H--S
S
Device Terminating an Ultra DMA Data-In Burst
The device terminates an Ultra DMA Data-In burst by following the steps lettered below. The timing
diagram is shown in below: Ultra DMA Data-In Burst Device Termination Timing. The timing parameters
are specified in Page 12: Ultra DMA Data Burst Timing Requirements and are described in Page 13:
Ultra DMA Data Burst Timing Descriptions.
The following steps shall occur in the order they are listed unless otherwise specifically allowed:
(a) The device shall not pause an Ultra DMA data burst until at least one data word of an Ultra DMA data
burst has been transferred.
(b) The device shall pause an Ultra DMA data burst by not generating DSTROBE edges.
(c) NOTE − The host shall not immediately assert STOP to initiate Ultra DMA data burst termination
when the device stops generating STROBE edges. If the device does not negate DMARQ, in order to
initiate Ultra DMA data burst termination, the host shall negate -HDMARDY and wait tRP before
asserting STOP.
(d) The device shall resume an Ultra DMA data burst by generating a DSTROBE edge.
ALL WAVEFORMS IN THIS DIAGRAM ARE SHOWN WITH THE ASSERTED STATE HIGH.
NEGATIVE TRUE SIGNALS APPEAR INVERTED ON THE BUS RELATIVE TO THE DIAGRAM.
Notes: The definitions for the STOP, HDMARDY, and DSTROBE signal lines are no longer in effect after DMARQ
and DMACK are negated. A[02:00], -CS0 & -CS1 are True IDE mode signal definitions.
Transcend Information Inc.
19
Ver 1.0
TTrraannsscceenndd 4444--P
Piinn IID
DE
E FFllaasshh M
Moodduullee ((H
Hoorriizzoonnttaall))
TTS
S112288M
M ~~ 44G
GD
DO
OM
M4444H
H--S
S
Host Terminating an Ultra DMA Data-In Burst
The host terminates an Ultra DMA Data-In burst by following the steps lettered below. The timing
diagram is shown in below: Ultra DMA Data-In Burst Host Termination Timing. The timing parameters
are specified in Page 12: Ultra DMA Data Burst Timing Requirements and are described in Page 13:
Ultra DMA Data Burst Timing Descriptions.
The following steps shall occur in the order they are listed unless otherwise specifically allowed:
(a) The host shall not initiate Ultra DMA data burst termination until at least one data word of an Ultra
DMA data burst has been transferred.
(b) The host shall initiate Ultra DMA data burst termination by negating -HDMARDY. The host shall
continue to negate -HDMARDY until the Ultra DMA data burst is terminated.
(c) The device shall stop generating DSTROBE edges within tRFS of the host negating -HDMARDY
(d) While operating in Ultra DMA modes 2, 1, or 0 the host shall be prepared to receive zero, one or two
additional data words after negating -HDMARDY. While operating in Ultra DMA modes 4 or 3 the
host shall be prepared to receive zero, one, two or three additional data words. The additional data
words are a result of cable round trip delay and tRFS timing for the device.
(e) The host shall assert STOP no sooner than tRP after negating -HDMARDY. The host shall not negate
STOP again until after the Ultra DMA data burst is terminated.
(f) The device shall negate DMARQ within tLI after the host has asserted STOP. The device shall not
assert DMARQ again until after the Ultra DMA data burst is terminated.
(g) If DSTROBE is negated, the device shall assert DSTROBE within tLI after the host has asserted
STOP. No data shall be transferred during this assertion. The host shall ignore this transition on
DSTROBE. DSTROBE shall remain asserted until the Ultra DMA data burst is terminated.
(h) The device shall release D[15:00] no later than tAZ after negating DMARQ.
(i) The host shall drive D[15:00] no sooner than tZAH after the device has negated DMARQ. For this step,
the host may first drive D[15:00] with the result of its CRC calculation (see ATA specification Ultra DMA
CRC Calculation).
(j) If the host has not placed the result of its CRC calculation on D[15:00] since first driving D[15:00]
during (9), the host shall place the result of its CRC calculation on D[15:00] (see ATA specification
Ultra DMA CRC Calculation).
(k) The host shall negate -DMACK no sooner than tMLI after the device has asserted DSTROBE and
negated DMARQ and the host has asserted STOP and negated -HDMARDY, and no sooner than tDVS
after the host places the result of its CRC calculation on D[15:00].
(l) The device shall latch the host’s CRC data from D[15:00] on the negating edge of -DMACK.
(m) The device shall compare the CRC data received from the host with the results of its own CRC
calculation. If a miscompare error occurs during one or more Ultra DMA data burst for any one
command, at the end of the command, the device shall report the first error that occurred (see ATA
specification Ultra DMA CRC Calculation)
(n) While operating in True IDE mode, the device shall release DSTROBE within tIORDYZ after the host
negates -DMACK.
(o) The host shall neither negate STOP nor assert -HDMARDY until at least tACK after the host has
negated -DMACK.
Transcend Information Inc.
20
Ver 1.0
TTrraannsscceenndd 4444--P
Piinn IID
DE
E FFllaasshh M
Moodduullee ((H
Hoorriizzoonnttaall))
TTS
S112288M
M ~~ 44G
GD
DO
OM
M4444H
H--S
S
(p) In True IDE mode, the host shall not assert -IORD, -CS0, -CS1, nor A[02:00] until at least tACK after
negating DMACK.
ALL WAVEFORMS IN THIS DIAGRAM ARE SHOWN WITH THE ASSERTED STATE HIGH.
NEGATIVE TRUE SIGNALS APPEAR INVERTED ON THE BUS RELATIVE TO THE DIAGRAM.
Notes: The definitions for the STOP, HDMARDY, and DSTROBE signal lines are no longer in effect after DMARQ
and DMACK are negated. A[02:00], -CS0 & -CS1 are True IDE mode signal definitions.
Transcend Information Inc.
21
Ver 1.0
TTrraannsscceenndd 4444--P
Piinn IID
DE
E FFllaasshh M
Moodduullee ((H
Hoorriizzoonnttaall))
TTS
S112288M
M ~~ 44G
GD
DO
OM
M4444H
H--S
S
Initiating an Ultra DMA Data-Out Burst
An Ultra DMA Data-out burst is initiated by following the steps lettered below. The timing diagram is
shown in below: Ultra DMA Data-Out Burst Initiation Timing. The timing parameters are specified in Page
12: Ultra DMA Data Burst Timing Requirements and are described in Page 13:Ultra DMA Data Burst
Timing Descriptions.
The following steps shall occur in the order they are listed unless otherwise specifically allowed:
(a) The host shall keep -DMACK in the negated state before an Ultra DMA data burst is initiated.
(b) The device shall assert DMARQ to initiate an Ultra DMA data burst.
(c) Steps (c), (d), and (e) may occur in any order or at the same time. The host shall assert STOP.
(d) The host shall assert HSTROBE.
(e) In True IDE mode, the host shall not assert -CS0, -CS1, nor A[02:00].
(f) Steps (c), (d), and (e) shall have occurred at least tACK before the host asserts -DMACK.The host shall
keep -DMACK asserted until the end of an Ultra DMA data burst.
(g) The device may negate -DDMARDY tZIORDY after the host has asserted -DMACK. While operating in
True IDE mode, once the device has negated -DDMARDY, the device shall not release -DDMARDY
until after the host has negated DMACK at the end of an Ultra DMA data burst.
(h) The host shall negate STOP within tENV after asserting -DMACK. The host shall not assert STOP until
after the first negation of HSTROBE.
(i) The device shall assert -DDMARDY within tLI after the host has negated STOP. After asserting
DMARQ and -DDMARDY the device shall not negate either signal until after the first negation of
HSTROBE by the host.
(j) The host shall drive the first word of the data transfer onto D[15:00]. This step may occur any time
during Ultra DMA data burst initiation.
(k) To transfer the first word of data: the host shall negate HSTROBE no sooner than tUI after the device
has asserted -DDMARDY. The host shall negate HSTROBE no sooner than tDVS after the driving the
first word of data onto D[15:00].
Transcend Information Inc.
22
Ver 1.0
TTrraannsscceenndd 4444--P
Piinn IID
DE
E FFllaasshh M
Moodduullee ((H
Hoorriizzoonnttaall))
TTS
S112288M
M ~~ 44G
GD
DO
OM
M4444H
H--S
S
ALL WAVEFORMS IN THIS DIAGRAM ARE SHOWN WITH THE ASSERTED STATE HIGH.
NEGATIVE TRUE SIGNALS APPEAR INVERTED ON THE BUS RELATIVE TO THE DIAGRAM.
Note: The definitions for the STOP, DDMARDY, and HSTROBE signal lines are not in effect until DMARQ and
DMACK are asserted. A[02:00], -CS0 & -CS1 are True IDE mode signal definitions.
Transcend Information Inc.
23
Ver 1.0
TTrraannsscceenndd 4444--P
Piinn IID
DE
E FFllaasshh M
Moodduullee ((H
Hoorriizzoonnttaall))
TTS
S112288M
M ~~ 44G
GD
DO
OM
M4444H
H--S
S
Sustaining an Ultra DMA Data-Out Burst
An Ultra DMA Data-Out burst is sustained by following the steps lettered below. The timing diagram
is shown in below: Sustained Ultra DMA Data-Out Burst Timing. The associated timing parameters are
specified in Page 12: Ultra DMA Data Burst Timing Requirements and are described in Page 13: Ultra
DMA Data Burst Timing Descriptions.
The following steps shall occur in the order they are listed unless otherwise specifically allowed:
(a) The host shall drive a data word onto D[15:00].
(b) The host shall generate an HSTROBE edge to latch the new word no sooner than tDVS after changing
the state of D[15:00]. The host shall generate an HSTROBE edge no more frequently than tCYC for the
selected Ultra DMA mode. The host shall not generate two rising or falling HSTROBE edges more
frequently than 2tcyc for the selected Ultra DMA mode.
(c) The host shall not change the state of D[15:00] until at least tDVH after generating an HSTROBE edge
to latch the data.
(d) The host shall repeat steps (a), (b), and (c) until the data transfer is complete or an Ultra DMA data
burst is paused, whichever occurs first.
Note: Data (D[15:00]) and HSTROBE signals are shown at both the device and the host to emphasize that cable
settling time as well as cable propagation delay shall not allow the data signals to be considered stable at
the device until some time after they are driven by the host.
Transcend Information Inc.
24
Ver 1.0
TTrraannsscceenndd 4444--P
Piinn IID
DE
E FFllaasshh M
Moodduullee ((H
Hoorriizzoonnttaall))
TTS
S112288M
M ~~ 44G
GD
DO
OM
M4444H
H--S
S
Device Pausing an Ultra DMA Data-Out Burst
The device pauses an Ultra DMA Data-Out burst by following the steps lettered below. The timing
diagram is shown in below: Ultra DMA Data-Out Burst Device Pause Timing. The timing parameters are
specified in Page 12: Ultra DMA Data Burst Timing Requirements and are described in Page 13: Ultra
DMA Data Burst Timing Descriptions.
The following steps shall occur in the order they are listed unless otherwise specifically allowed:
(a) The device shall not pause an Ultra DMA data burst until at least one data word of an Ultra DMA data
burst has been transferred.
(b) The device shall pause an Ultra DMA data burst by negating -DDMARDY.
(c) The host shall stop generating HSTROBE edges within tRFS of the device negating -DDMARDY.
(d) While operating in Ultra DMA modes 2, 1, or 0 the device shall be prepared to receive zero, one or two
additional data words after negating -HDMARDY. While operating in Ultra DMA modes 4 or 3 the
device shall be prepared to receive zero, one, two or three additional data words. The additional data
words are a result of cable round trip delay and tRFS timing for the device.
(e) The device shall resume an Ultra DMA data burst by asserting -DDMARDY.
ALL WAVEFORMS IN THIS DIAGRAM ARE SHOWN WITH THE ASSERTED STATE HIGH.
NEGATIVE TRUE SIGNALS APPEAR INVERTED ON THE BUS RELATIVE TO THE DIAGRAM.
Notes:
(1) The device may negate DMARQ to request termination of the Ultra DMA data burst no sooner than tRP after -DDMARDY is
negated.
(2) After negating -DDMARDY, the device may receive zero, one, two, or three more data words from the host.
Transcend Information Inc.
25
Ver 1.0
TTrraannsscceenndd 4444--P
Piinn IID
DE
E FFllaasshh M
Moodduullee ((H
Hoorriizzoonnttaall))
TTS
S112288M
M ~~ 44G
GD
DO
OM
M4444H
H--S
S
Device Terminating an Ultra DMA Data-Out Burst
The device terminates an Ultra DMA Data-Out burst by following the steps lettered below. The timing
diagram for the operation is shown in below: Ultra DMA Data-Out Burst Device Termination Timing. The
timing parameters are specified in Page 12: Ultra DMA Data Burst Timing Requirements and are
described in Page 13: Ultra DMA Data Burst Timing Descriptions.
The following steps shall occur in the order they are listed unless otherwise specifically allowed:
(a) The device shall not initiate Ultra DMA data burst termination until at least one data word of an Ultra
DMA data burst has been transferred.
(b) The device shall initiate Ultra DMA data burst termination by negating -DDMARDY.
(c) The host shall stop generating an HSTROBE edges within tRFS of the device negating -DDMARDY.
(d) While operating in Ultra DMA modes 2, 1, or 0 the device shall be prepared to receive zero, one or two
additional data words after negating -HDMARDY. While operating in Ultra DMA modes 4 or 3 the
device shall be prepared to receive zero, one, two or three additional data words. The additional
data words are a result of cable round trip delay and tRFS timing for the device.
(e) The device shall negate DMARQ no sooner than tRP after negating -DDMARDY. The device shall not
assert DMARQ again until after the Ultra DMA data burst is terminated.
(f) The host shall assert STOP within tLI after the device has negated DMARQ. The host shall not negate
STOP again until after the Ultra DMA data burst is terminated.
(g) If HSTROBE is negated, the host shall assert HSTROBE within tLI after the device has negated
DMARQ. No data shall be transferred during this assertion. The device shall ignore this transition of
HSTROBE. HSTROBE shall remain asserted until the Ultra DMA data burst is terminated.
(h) The host shall place the result of its CRC calculation on D[15:00] (see ATA specification Ultra DMA
CRC Calculation).
(i) The host shall negate -DMACK no sooner than tMLI after the host has asserted HSTROBE and STOP
and the device has negated DMARQ and -DDMARDY, and no sooner than tDVS after placing the result
of its CRC calculation on D[15:00].
(j) The device shall latch the host’s CRC data from D[15:00] on the negating edge of -DMACK.
(k) The device shall compare the CRC data received from the host with the results of its own CRC
calculation. If a miscompare error occurs during one or more Ultra DMA data bursts for any one
command, the device shall report the first error that occurred (see ATA specification Ultra DMA CRC
Calculation).
(l) While operating in True IDE mode, the device shall release DSTROBE within tIORDYZ after the host
negates -DMACK.
(m) The host shall not negate STOP nor assert –HDMARDY until at least tACK after negating -DMACK.
(n) In True IDE mode, the host shall not assert -IOWR, -CS0, -CS1, nor A[02:00] until at least tACK after
negating DMACK.
Transcend Information Inc.
26
Ver 1.0
TTrraannsscceenndd 4444--P
Piinn IID
DE
E FFllaasshh M
Moodduullee ((H
Hoorriizzoonnttaall))
TTS
S112288M
M ~~ 44G
GD
DO
OM
M4444H
H--S
S
ALL WAVEFORMS IN THIS DIAGRAM ARE SHOWN WITH THE ASSERTED STATE HIGH.
NEGATIVE TRUE SIGNALS APPEAR INVERTED ON THE BUS RELATIVE TO THE DIAGRAM.
Note: The definitions for the STOP, DDMARDY, and HSTROBE signal lines are no longer in effect after DMARQ
and DMACK are negated. A00-A02, -CS0 & -CS1 are True IDE mode signal definitions.
Transcend Information Inc.
27
Ver 1.0
TTrraannsscceenndd 4444--P
Piinn IID
DE
E FFllaasshh M
Moodduullee ((H
Hoorriizzoonnttaall))
TTS
S112288M
M ~~ 44G
GD
DO
OM
M4444H
H--S
S
Host Terminating an Ultra DMA Data-Out Burst
Termination of an Ultra DMA Data-Out burst by the host is shown in below: Ultra DMA Data-Out
Burst Host Termination Timing while timing parameters are specified in Page 12: Ultra DMA Data Burst
Timing Requirements and timing parameters are described in Page 13: Ultra DMA Data Burst Timing
Descriptions.
The following steps shall occur in the order they are listed unless otherwise specifically allowed:
(a) The host shall initiate termination of an Ultra DMA data burst by not generating HSTROBE edges.
(b) The host shall assert STOP no sooner than tSS after it last generated an HSTROBE edge.The host
shall not negate STOP again until after the Ultra DMA data burst is terminated.
(c) The device shall negate DMARQ within tLI after the host asserts STOP. The device shall not assert
DMARQ again until after the Ultra DMA data burst is terminated.
(d) The device shall negate -DDMARDY within tLI after the host has negated STOP. The device shall not
assert -DDMARDY again until after the Ultra DMA data burst termination is complete.
(e) If HSTROBE is negated, the host shall assert HSTROBE within tLI after the device has negated
DMARQ. No data shall be transferred during this assertion. The device shall ignore this transition on
HSTROBE. HSTROBE shall remain asserted until the Ultra DMA data burst is terminated.
(f) The host shall place the result of its CRC calculation on D[15:00] (see ATA specification Ultra DMA
CRC Calculation).
(g) The host shall negate -DMACK no sooner than tMLI after the host has asserted HSTROBE and STOP
and the device has negated DMARQ and -DDMARDY, and no sooner than tDVS after placing the result
of its CRC calculation on D[15:00].
(h) The device shall latch the host’s CRC data from D[15:00] on the negating edge of -DMACK.
(i) The device shall compare the CRC data received from the host with the results of its own CRC
calculation. If a miscompare error occurs during one or more Ultra DMA data bursts for any one
command, at the end of the command, the device shall report the first error that occurred (see ATA
specification Ultra DMA CRC Calculation).
(j) While operating in True IDE mode, the device shall release -DDMARDY within tIORDYZ after the host
has negated -DMACK.
(k) The host shall neither negate STOP nor negate HSTROBE until at least tACK after negating -DMACK.
(l) In True IDE mode, the host shall not assert -IOWR, -CS0, -CS1, nor A[02:00] until at least tACK after
negating DMACK..
Transcend Information Inc.
28
Ver 1.0
TTrraannsscceenndd 4444--P
Piinn IID
DE
E FFllaasshh M
Moodduullee ((H
Hoorriizzoonnttaall))
TTS
S112288M
M ~~ 44G
GD
DO
OM
M4444H
H--S
S
ALL WAVEFORMS IN THIS DIAGRAM ARE SHOWN WITH THE ASSERTED STATE HIGH.
NEGATIVE TRUE SIGNALS APPEAR INVERTED ON THE BUS RELATIVE TO THE DIAGRAM.
Notes: The definitions for the STOP, DDMARDY, and HSTROBE signal lines are no longer in effect after DMARQ
and DMACK are negated. A[02:00], -CS0 & -CS1 are True IDE mode signal definitions.
Transcend Information Inc.
29
Ver 1.0
TTrraannsscceenndd 4444--P
Piinn IID
DE
E FFllaasshh M
Moodduullee ((H
Hoorriizzoonnttaall))
TTS
S112288M
M ~~ 44G
GD
DO
OM
M4444H
H--S
S
IDENTIFY DEVICE information
The Identify Device command enables the host to receive parameter information from the device.
This command has the same protocol as the Read Sector(s) command. The parameter words in the
buffer have the arrangement and meanings defined in Table as below. All reserved bits or words are zero.
Hosts should not depend on Obsolete words in Identify Device containing 0. Table below specifies each
field in the data returned by the Identify Device Command. In Table as below, X indicates a numeric
nibble value specific to the card and aaaa indicates an ASCII string specific to the particular drive.
Word
Default
Total
Address
Value
Bytes
0
044Ah
2
General configuration – Bit Significant with ATA-4 definitions.
1
XXXXh
2
Default number of cylinders
2
0000h
2
Reserved
3
00XXh
2
Default number of heads
4
0000h
2
Obsolete
5
0000h
2
Obsolete
6
XXXXh
2
Default number of sectors per track
7-8
XXXXh
4
Number of sectors per card (Word 7 = MSW, Word 8 = LSW)
9
XXXXh
2
Obsolete
10-19
aaaa
20
Serial number in ASCII (Right Justified)
20
0000h
2
Obsolete
21
0000h
2
Obsolete
22
0004h
2
Number of ECC bytes passed on Read/Write Long Commands
23-26
aaaa
8
Firmware revision in ASCII. Big Endian Byte Order in Word
27-46
aaaa
40
47
XXXXh
2
Maximum number of sectors on Read/Write Multiple command
48
0000h
2
Reserved
49
XX00h
2
Capabilities
50
0000h
2
Reserved
Transcend Information Inc.
Data Field Type Information
Model number in ASCII (Left Justified) Big Endian Byte Order in
Word
30
Ver 1.0
TTrraannsscceenndd 4444--P
Piinn IID
DE
E FFllaasshh M
Moodduullee ((H
Hoorriizzoonnttaall))
TTS
S112288M
M ~~ 44G
GD
DO
OM
M4444H
H--S
S
Word
Address
Default
Value
Total
Bytes
51
52
53
54
55
56
57-58
59
60-61
62
63
64
0200h
0000h
000Xh
XXXXh
XXXXh
XXXXh
XXXXh
01XXh
XXXXh
0000h
0X0Xh
0003h
2
2
2
2
2
2
4
2
4
2
2
2
65
XXXXh
2
66
XXXXh
2
67
68
69-79
80-81
82-84
85-87
88
89
90
91
92-127
128
129-159
160
161
162
163
164
165-167
168-255
XXXXh
XXXXh
0000h
0000h
XXXXh
XXXXh
001Fh
XXXXh
XXXXh
XXXXh
0000h
XXXXh
0000h
XXXXh
0000h
0000h
XXXXh
XXXXh
0000h
0000h
2
2
20
4
6
6
2
2
2
2
72
2
64
2
2
2
2
2
6
158
Transcend Information Inc.
Data Field Type Information
PIO data transfer cycle timing mode
Obsolete
Field Validity
Current numbers of cylinders
Current numbers of heads
Current sectors per track
Current capacity in sectors (LBAs)(Word 57 = LSW, Word 58 = MSW)
Multiple sector setting
Total number of sectors addressable in LBA Mode
Reserved
Multiword DMA transfer. In PC Card modes this value shall be 0h
Advanced PIO modes supported
Minimum Multiword DMA transfer cycle time per word. In PC Card
modes this value shall be 0h
Recommended Multiword DMA transfer cycle time. In PC Card
modes this value shall be 0h
Minimum PIO transfer cycle time without flow control
Minimum PIO transfer cycle time with IORDY flow control
Reserved
Reserved – CF cards do not return an ATA version
Features/command sets supported
Features/command sets enabled
Ultra DMA Mode Supported and Selected (UDMA mode 0 ~ 4)
Time required for Security erase unit completion
Time required for Enhanced security erase unit completion
Current Advanced power management value
Reserved
Security status
Vendor unique bytes
Power requirement description
Reserved for assignment by the CFA
Key management schemes supported
CF Advanced True IDE Timing Mode Capability and Setting
CF Advanced PC Card I/O and Memory Timing Mode Capability
Reserved for assignment by the CFA
Reserved
31
Ver 1.0
TTrraannsscceenndd 4444--P
Piinn IID
DE
E FFllaasshh M
Moodduullee ((H
Hoorriizzoonnttaall))
TTS
S112288M
M ~~ 44G
GD
DO
OM
M4444H
H--S
S
Transcend Information Inc.
32
Ver 1.0
TTrraannsscceenndd 4444--P
Piinn IID
DE
E FFllaasshh M
Moodduullee ((H
Hoorriizzoonnttaall))
TTS
S112288M
M ~~ 44G
GD
DO
OM
M4444H
H--S
S
Capacity Specifications:
Transcend P/N
Capacity
Cylinder (C)
Head (H)
Sector (S)
TS128MDOM44H-S
128MB
248
16
63
TS256MDOM44H-S
256MB
496
16
63
TS512MDOM44H-S
512MB
993
16
63
TS1GDOM44H-S
1GB
1942
16
63
TS2GDOM44H-S
2GB
3884
16
63
TS4GDOM44H-S
4GB
7769
16
63
Transcend Information Inc.
33
Ver 1.0
TTrraannsscceenndd 4444--P
Piinn IID
DE
E FFllaasshh M
Moodduullee ((H
Hoorriizzoonnttaall))
TTS
S112288M
M ~~ 44G
GD
DO
OM
M4444H
H--S
S
Ordering Information
TS XXXX DOM 44 H-S
Transcend Product
Type:
V = Vertical
H = Horizontal
Capacity:
128M-512M = 128 MB up to 512 MB
1G-4G = 1 GB up to 4 GB
Pin Count:
40 = 40 pin
44 = 44 pin
IDE Flash Module
(Disk On Module)
The above technical information is based on industry standard data and has been tested to be reliable. However, Transcend
makes no warranty, either expressed or implied, as to its accuracy and assumes no liability in connection with the use of this
product. Transcend reserves the right to make changes to the specifications at any time without prior notice.
TAIWAN
No.70, XingZhong Rd., NeiHu Dist., Taipei, Taiwan, R.O.C
TEL +886-2-2792-8000
Fax +886-2-2793-2222
E-mail: [email protected]
www.transcend.com.tw
Transcend Information Inc.
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34
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