TRANSCEND TS512MDOM44H

TTrraannsscceenndd 4444--P
Piinn IID
DE
E FFllaasshh M
Moodduullee ((H
Hoorriizzoonnttaall))
112288M
M ~~ 44G
GB
B
Description
Features
With an IDE interface and strong data retention
•
RoHS compliant
ability, 44-Pin IDE Flash Modules are ideal for use in
•
Fully compatible with devices and OS that support the
IDE standard (44-Pin, pitch = 2.00 mm)
•
Non-volatile Flash Memory for outstanding data
retention
•
Built-in ECC (Error Correction Code) functionality and
wear-leveling algorithm ensures highly reliable of data
transfer
•
Supports up to Ultra DMA Mode 4
•
Supports PIO Mode 6
•
LED indicates status of usage (Data Access)
•
Shock resistance
the harsh environments where Industrial PCs,
Set-Top Boxes, etc. are used.
Dimensions
Placement
Transcend Information Inc.
Side
Millimeters
Inches
A
46.00 ± 0.40
1.81 ± 0.016
B
28.00 ± 0.20
1.10 ± 0.008
C
6.00 ± 0.50
0.24 ± 0.020
1
Ver 1.0
TTrraannsscceenndd 4444--P
Piinn IID
DE
E FFllaasshh M
Moodduullee ((H
Hoorriizzoonnttaall))
112288M
M ~~ 44G
GB
B
Specifications
Physical Specifications
128 MB to 4 GB
Storage Capacities
Dimensions (mm)
Length
46.0 0 ± 0.40
Width
28.00 ± 0.20
Height
5.87 ± 0.50
Weight
7 g (Max.)
Connector
44-Pin standard IDE/ATA connector (Pitch 2.0 mm)
Environmental Specifications
Operating Temperature
0 ℃ to 70 ℃
Storage Temperature
- 40 ℃ to 85 ℃
Reliability
Write/Erase Endurance
> 2,000,000 cycles
Read Endurance
Unlimited
Data Reliability
Built-in 4 symbol correction ECC (per 512 bytes Sector)
Data Retention
10 years
Connector Durability
5,000 times
Interface Specifications
Jumper Settings
Master/Slave Settings
ATA/ATAPI 5
ATA Compatibility
PIO Modes 0 – 6
UDMA Modes 0 – 4
Transcend Information Inc.
2
Ver 1.0
TTrraannsscceenndd 4444--P
Piinn IID
DE
E FFllaasshh M
Moodduullee ((H
Hoorriizzoonnttaall))
112288M
M ~~ 44G
GB
B
Capacity Specifications
Transcend P/N
Capacity
Cylinder (C)
Head (H)
Sector (S)
TS128MDOM44H
128MB
978
8
32
TS256MDOM44H
256MB
978
16
32
TS512MDOM44H
512MB
993
16
63
TS1GDOM44H
1GB
1985
16
63
TS2GDOM44H
2GB
3954
16
63
TS4GDOM44H
4GB
7889
16
63
Compliance and Warranty
Compliance
CE, FCC and BSMI
Warranty
2 years
Transcend Information Inc.
3
Ver 1.0
TTrraannsscceenndd 4444--P
Piinn IID
DE
E FFllaasshh M
Moodduullee ((H
Hoorriizzoonnttaall))
112288M
M ~~ 44G
GB
B
Package Dimensions
Below figure illustrates the Transcend 44-Pin IDE Flash Module (Horizontal). All dimensions are in mm.
Transcend Information Inc.
4
Ver 1.2
TTrraannsscceenndd 4444--P
Piinn IID
DE
E FFllaasshh M
Moodduullee ((H
Hoorriizzoonnttaall))
112288M
M ~~ 44G
GB
B
Pin Assignments
Pin No.
Pin Name
Pin No.
Pin Name
01
03
05
07
09
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
-RESET
DD7
DD6
DD5
DD4
DD3
DD2
DD1
DD0
GND
DMARQ
-DIOW : STOP
-DIOR : -HDMARDY : HSTROBE
IORDY : DDMARDY : DSTROBE
-DMACK
INTRQ
DA1
DA0
-CS0
-DASP
VCC
GND
02
04
06
08
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
GND
DD8
DD9
DD10
DD11
DD12
DD13
DD14
DD15
KEY-PIN (OPEN)
GND
GND
GND
CSEL
GND
IOCS16B
-PDIAG : -CBLID
DA2
-CS1
GND
VCC
NC (No Connect)
Pin Layout
Pin1
Bulge
Pin2
Transcend Information Inc.
Pin43
Pin44
5
Ver 1.2
TTrraannsscceenndd 4444--P
Piinn IID
DE
E FFllaasshh M
Moodduullee ((H
Hoorriizzoonnttaall))
112288M
M ~~ 44G
GB
B
Pin Description
Pin No.
Signal
01
-RESET
17, 15, 13, 11, 09, 07,
05, 03, 04, 06, 08, 10,
12, 14, 16, 18
DD0 ~ DD15 (Device Data)
21
DMARQ (DMA Request)
I/O*
I
Hardware reset signal from the host.
I/O
O
23
-DIOW (I/O Write)
The host asserts this signal during an UDMA burst to
stop the DMA burst.
-DIOR (I/O Read)
This is the strobe signal used by the host to read from
the device register or the Data port.
When UDMA mode DMA Read is ready, -HDMARDY
should be asserted by the host to indicate that the host is
ready to receive DMA data-in burst.
I
HSTROBE (UDMA Strobe)
HSTROBE receives the data-out strobe signal from the
host for an UDMA burst.
IORDY (I/O channel ready)
This signal is used to temporarily stop the host register
access (read or write) when the device is not ready to
respond to a data transfer request.
DDMARDY (UDMA ready)
28
For DMA data transfers. Device will assert DMARQ
when the device is ready to transfer data to or from the
host.
STOP (Stop UDMA Burst)
-HDMARDY (UDMA ready)
27
16-bit bi-direction Data Bus. DD(7:0) are used for 8-bit
register transfers.
This is the strobe signal used by the host to write to the
device register or Data port.
I
25
Description
O
The device will assert this signal to indicate that the
device is ready to receive UDMA data-out burst.
DSTROBE (UDMA data
strobe)
When UDMA mode DMA Read is active, this signal is
the data-in strobe generated by the device.
CSEL (Cable select)
I
This pin is used to configure this device as Device 0 or
Device 1. When this pin is grounded, this device is
configured as Device 0. When this pin is High, this
device is configured as Device 1.
I
This signal is used by the host in response to DMARQ to
initiate DMA transfer.
O
When this device is selected, this signal is the active
high Interrupt Request to the host.
O
During PIO transfer mode 0, 1 or 2, this pin indicates to
the host the 16-bit data port has been addressed and the
device is prepared to send or receive a 16-bit data word.
When transferring in PIO mode 3, 4, or above, this signal
should not be used by the host, and all transfers will be
16-bit. When transferring in DMA mode, the host must
use a 16-bit DMA channel and this signal will not be
asserted.
29
-DMACK (DMA
acknowledge)
31
INTRQ (Interrupt)
32
IOCS16B
Transcend Information Inc.
6
Ver 1.2
TTrraannsscceenndd 4444--P
Piinn IID
DE
E FFllaasshh M
Moodduullee ((H
Hoorriizzoonnttaall))
112288M
M ~~ 44G
GB
B
35, 33, 36
DA0 ~ DA2 (Device
Address)
34
-PDIAG (Passed
diagnostics)
This is the 3-bit binary coded Address Bus.
I
I/O
This signal will be asserted by Device 1 to indicate to
Device 0 that Device 1 has completed diagnostics.
-CBLID (Cable assembly
type identifier)
37, 38
-CS0, -CS1 (Chip select)
39
-DASP (Device active,
Device 1 present)
41, 42
VCC
2, 19, 22, 24, 26, 30,
40, 43
GND
I
These signals are used to select the Command Block
and Control Block registers. When –DMACK is asserted,
-CS0 and –CS1 shall be negated and transfers shall be
16-bit wide.
I/O
During the reset protocol, -DASP shall be asserted by
Device 1 to indicate that the device is present.
P
Power supply.
Ground.
-
* Note:
“I”
An input from the host system to the device.
“O”
An output from the device to the host system.
“I/O”
An input/output (bi-direction) common.
“P”
Power supply.
Block Diagram
Data bus
44 PIN IDE Connector
Control
Signal
D00 ~ D07
Flash Memory
-CE0, -CE2…
D0 – D7
-CE0
-CE1
-WE…-RE
Others
IDE
Power
Flash Disk
Controller
D10 ~ D17
-CE1, -CE3…
Transcend Information Inc.
Flash Memory
D0 – D7
-CE0
-CE1
-WE…-RE
7
Ver 1.2
TTrraannsscceenndd 4444--P
Piinn IID
DE
E FFllaasshh M
Moodduullee ((H
Hoorriizzoonnttaall))
112288M
M ~~ 44G
GB
B
Command Set
The following table summarizes the command defined in the ATAPI-5 specification and lists the commands supported
by the TS128M-4GDOM44H.
Note 1: FR (Feature Register), SC (Sector Count Register), SN (Sector Number Register), CY (Cylinder Low/High
Register), DR (Drive bit of Drive/Head Register), HD (Head No. bit0-bit3 of Drive/Head Register), LBA (Logical Block
Address Mode supported). Y: Set up; -: Not set up; C: The register contains command specific data.
Transcend Information Inc.
8
Ver 1.2
TTrraannsscceenndd 4444--P
Piinn IID
DE
E FFllaasshh M
Moodduullee ((H
Hoorriizzoonnttaall))
112288M
M ~~ 44G
GB
B
Ordering Information
TS XXXX DOM 44 H
Transcend Product
Type:
V = Vertical
H = Horizontal
Capacity:
32M-512M = 32 MB up to 512 MB
1G-4G = 1 GB up to 4 GB
Pin Count:
40 = 40 pin
44 = 44 pin
IDE Flash Module
(Disk On Module)
The above technical information is based on industry standard data and has been tested to be reliable. However,
Transcend makes no warranty, either expressed or implied, as to its accuracy and assumes no liability in connection with
the use of this product. Transcend reserves the right to make changes to the specifications at any time without prior notice.
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