Winbond Integrated Media Reader W83L518D Datasheet -i- Publication Release Date: May 17, 2005 Revision 1.0 W83L518D Table of Contents1. GENERAL DESCRIPTION ......................................................................................................... 1 2. FUNCTIONS ............................................................................................................................... 1 2.1 General............................................................................................................................. 1 2.2 Smart Card Interface ........................................................................................................ 1 2.3 Memory Stick Interface..................................................................................................... 2 2.4 SD Memory Card Interface .............................................................................................. 2 2.5 Package ........................................................................................................................... 2 3. PIN CONFIGURATION FOR W83L518D ................................................................................... 3 4. PIN DESCRIPTION..................................................................................................................... 4 4.1 Bus Interface .................................................................................................................... 4 4.2 Smart Card Interface Pins ................................................................................................ 5 4.3 Memory Stick Interface/SD Memory Interface Pins ......................................................... 6 4.4 General-Purpose I/O Pins ................................................................................................ 7 4.5 Crystal and Power Pins .................................................................................................... 7 5. GENERAL-PURPOSE I/O PORTS (GPIO) ................................................................................ 8 6. CONFIGURATION REGISTER .................................................................................................. 9 6.1 Plug and Play Configuration............................................................................................. 9 6.2 Compatible PnP ............................................................................................................. 10 6.3 6.2.1 Extended Function Register ........................................................................................... 10 6.2.2 Extended Functions Enable Register (EFER)................................................................. 10 6.2.3 Extended Function Index Register (EFIR), Extended Function Data Register (EFDR)... 11 Configuration Sequence................................................................................................. 11 6.3.1 Software programming example ..................................................................................... 11 6.4 Global Registers............................................................................................................. 12 6.5 Logical Device 0 (Smart Card Interface) ........................................................................ 14 6.6 Logical Device 1 (Memory Stick Interface) .................................................................... 15 6.7 Logical Device 2 (GPIO) ................................................................................................ 16 6.8 Logical Device 3 (SD Memory Interface) ....................................................................... 17 7. ORDERING INSTRUCTION ..................................................................................................... 18 8. HOW TO READ THE TOP MARKING...................................................................................... 19 9. PACKAGE DRAWING AND DIMENSIONS.............................................................................. 20 10. THE W83L518D SCHEMATIC.................................................................................................. 21 11. REVISION HISTORY ................................................................................................................ 23 - ii - W83L518D 1. GENERAL DESCRIPTION W83L518D is Winbond's innovative solution to a new class of storage devices for IA Noetebook, Desktop PC and PC system-related products. It incorporates a security Application: Smart Card Interface and two most promising compact storage interfaces: Memory Stick interface, and SD Memory Card/Multimedia Card interface in IT era. To cater boundless IT implementation possibilities, W83L518D can be configured to interface with host through LPC bus. Base on the LPC interface, one Smart Card Interface port and two flash memory interfaces - Memory Stick and SD Memory ports are provided. The kind of versatility allows user to design very cost-effective products in a very flexible way. The whole chip of W83L518D operates at voltage level of 3.3 V except Smart Card Interface port's I/O pins that are at 5 V to be compatible with mainstream Smart Card implementations. Advanced power management feature further optimizes power consumption whether in operation or in power down mode. W83L518D comes as a 48-pin LQFP streamline package. Combining with powerful functions, effective power management, and versatile configurability, this integrated media reader offers a perfect approach for design of storage device of IT products. The trademarks and intellectual property rights of Memory Stick belong to SONY Corporation. Information check: http://www.memorystick.org/ The trademarks and intellectual property rights of Secure Digital belong to SD Group. Information check: http://www.sdcard.org/ 2. FUNCTIONS 2.1 General • LPC bus is compliant with LPC Spec. 1.01 • LPC bus supports LDRQ# (LPC DMA), SERIRQ (serial IRQ) • Programmable configuration settings • 48 MHz crystal inputs • PCICLK of 33 MHz is needed for LPC bus configuration 2.2 Smart Card Interface • ISO-7816 compliant • PC/SC T=0, T=1 compliant • 16-byte transmitter FIFO and 16-byte receiver FIFO • FIFO threshold interrupt to optimize system performance • Programmable transmission clock frequency • Versatile baud rate configuration • UART-like register file structure • General-purpose C4, C8 channels -1- Publication Release Date: May 17, 2005 Revision 1.0 W83L518D 2.3 Memory Stick Interface • Memory Stick Standard Format Specifications ver. 1.3 compliant • Support MemoryStick PRO (serial mode) • Support interrupt polling transmission • Support FIFO threshold interrupt to optimize system performance • Automatic clock halt to prevent underrun/overrun • 16 MHz interface clock 2.4 SD Memory Card Interface • SD Memory Card Specifications: Part 1 PHYSICAL LAYER SPECIFICATION Version 1.0 Compliant • Support MultiMedia Card • Support interrupt polling transmission • Support FIFO threshold interrupt to leverage system performance • 24 MHz interface clock 2.5 • Package 48-pin LQFP -2- W83L518D SDPWR#/GP21 SDLED/GP20 SCC4 SCC8 MSLED MSPWR# VSS MSCLK MS1 MS2 MS3 MS4 35 34 33 32 31 30 29 28 27 26 25 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 18 17 16 15 14 13 10 11 12 GP13 GP12 8 GP16 GP14 7 GP17 9 6 VSS -3- GP15 5 PME# 3 LFRAME# 4 2 RESET# 1 LDRQ# W 83L518D PCICLK S D C L K /G P 2 2 S D 1 /G P 2 3 S D 2 /G P 2 4 VD D 3V S D 3 /G P 2 5 S D 4 /G P 2 6 S D 5 /G P 2 7 LAD3 LAD2 LAD1 LAD0 S E R IR Q 36 3. PIN CONFIGURATION FOR W83L518D MS5 X IN XOUT SCRST# S C IO SC C LK SCPSNT SCPW R# SCLED VDD G P10 G P11 Publication Release Date: May 11, 2005 Revision 1.0 W83L518D 4. PIN DESCRIPTION Note: INt - 5V TTL level input pin INtp3 - 3.3V TTL level input pin INts - 5V TTL level Schmitt-trigger input pin INtsp3 - 3.3V TTL level Schmitt-trigger input pin I/O12t - 5V TTL level bi-directional pin with 12 mA drive-sink capability I/O24t - 5V TTL level bi-directional pin with 24 mA drive-sink capability I/O16tp3 - 3.3V TTL level bi-directional pin with 16 mA drive-sink capability O2 - 5V output pin with 2 mA drive-sink capability O12 - 5V output pin with 12 mA drive-sink capability O16p3 - 3.3V output pin with 16 mA drive-sink capability OD12p3 4.1 - 3.3V Open-drain output pin with 12 mA sink capability. Bus Interface SYMBOL PIN I/O FUNCTION PME# 5 OD12p3 RESET# 4 INtsp3 Active-low system reset signal. LFRAME# 3 INtsp3 Active-low signal indicates start of a new LPC frame or termination of a premature frame. LDRQ# 2 O16p3 Encoded DMA Request signal. PCICLK 1 Intsp3 PCI clock input of 33 MHz. SERIRQ 48 I/O16tp3 Serial IRQ input/output. LAD0 47 I/O16tp3 This signal combining with other LADx signals communicate address, control, and data information over the LPC bus between a host and a peripheral. LAD1 46 I/O16tp3 This signal combining with other LADx signals communicate address, control, and data information over the LPC bus between a host and a peripheral. LAD2 45 I/O16tp3 This signal combining with other LADx signals communicate address, control, and data information over the LPC bus between a host and a peripheral. LAD3 44 I/O16tp3 This signal combining with other LADx signals communicate address, control, and data information over the LPC bus between a host and peripherals. Active-low PME event. -4- W83L518D 4.2 Smart Card Interface Pins SYMBOL PIN I/O FUNCTION SCC4 34 I/O16tp3 Smart Card interface general purpose I/O channel for connector pin C4 on a card. SCC8 33 I/O16tp3 Smart Card interface general purpose I/O channel for connector pin C8 on a card. SCLED 16 O24 This pin outputs an oscillating clock signal of various frequencies depending on traffic of primary Smart Card interface. SCPWR# 17 O24 Smart Card interface power control signal. SCPSNT 18 INts Smart Card interface card present detection Schmitt-trigger input. SCCLK 19 O2 Smart Card interface clock output. SCIO 20 I/O12t SCRST# 21 O12 Smart Card interface data I/O channel. Smart Card interface reset output. -5- Publication Release Date: May 11, 2005 Revision 1.0 W83L518D 4.3 Memory Stick Interface/SD Memory Interface Pins SYMBOL PIN I/O FUNCTION MSLED 32 O16p3 Memory Stick function - This pin outputs an oscillating clock signal of various frequencies depending on traffic of the Memory Stick interface. MSPWR# 31 O16p3 Memory Stick function - This pin is power control signal for the Memory Stick interface. MSCLK 29 O16p3 Memory Stick function - This pin is SCLK for the Memory Stick interface. MS1 28 O16p3 Memory Stick interface pin. MS2 27 I/O16tp3 Memory Stick interface pin. MS3 26 --- Memory Stick interface pin. MS4 25 INtsp3 Memory Stick interface pin. MS5 24 --- Memory Stick interface pin. SD5 43 I/O16tp3 SD interface pin. SD interface pin. 42 I/O16tp3 SD interface pin. SD interface pin. 41 I/O16tp3 SD interface pin. SD interface pin. 39 I/O16tp3 SD interface pin. SD interface pin. 38 I/O16tp3 SD interface pin. SDCLK 37 O16p3 SD function - This pin is CLK for the SD memory card interface. SDPWR# 36 O16p3 SD function - This pin is power control signal for the SD memory card interface. SDLED 35 O16p3 SD function - This pin outputs an oscillating clock signal of various frequencies depending on traffic of the SD memory card interface. CARD_DETECT 13 INt Function as an alternative card detection input for the SD memory interface. -6- W83L518D 4.4 General-Purpose I/O Pins SYMBOL PIN I/O GP17 7 I/O12t General-purpose I/O port 17. GP16 8 I/O12t General-purpose I/O port 16. GP15 9 I/O12t General-purpose I/O port 15. GP14 10 I/O12t General-purpose I/O port 14. GP13 11 I/O12t General-purpose I/O port 13. GP12 12 I/O12t General-purpose I/O port 12. GP11 EX_CD FUNCTION General-purpose I/O port 11. 13 I/O12t External card detedtion pin. The detectable level can be set on bit 2 of CR F0 on Logical device 3. General-purpose I/O port 10. GP10 PHEFRAS 4.5 14 I/O12t Int This pin also functions as a power-on setting pin whose value is latched on the rising edge of RESET# (pin 4) to select configuration ports as 2Eh/2Fh (PHEFRAS = 1) or 4Eh/4Fh (PHEFRAS = 0). It determines the default value of CR26 bit 6 (HEFRAS). Crystal and Power Pins SYMBOL PIN FUNCTION XOUT, XIN 22, 23 Connected to a 48 MHz crystal and function as the working clock for all the media reader interfaces. VDD3V 40 +3.3V power supply for host interface, Memory Stick/SD Memory interfaces, and internal core. VDD 15 +5V power supply for Smart Card interface I/O pins. VSS 6, 30 Ground. -7- Publication Release Date: May 11, 2005 Revision 1.0 W83L518D 5. GENERAL-PURPOSE I/O PORTS (GPIO) W83L518D supports one group of dedicated general-purpose I/O ports and a multi-functional GPIO group, which share the same pines with the SD interface sockets. There are cases when only one socket is needed in a system and pins for the other unused socket are wasted. To provide the most cost-effective solution, W83L518D could be configured to transform these pins into general-purpose I/O ports. The first group (GP10 ~ 17) is configured through the configuration registers CRF0 ~ CRF2 in logical device 2 and the other group (GP20 ~27) through CRF3 ~ F5. Users can configure each individual port to be an input or output port by programming respective bit in direction register (CRF0/CRF3: 0 = output, 1 = input). Invert port value by setting inversion register (CRF2/CRF5: 0 = non-inverse, 1 = inverse). Port value is read/written through data register (CRF1/CRF4). Table 5.1 and 5.2 illustrate GPIO's assignment. To further facilitate system design, W83L518D allows direct accesses to data register and direction register through I/O ports, whose base address is programmable at CR 60, 61 in logical device 2. Detailed configuration is described in logical device 2 of section 6: CONFIGURATION REGISTER. GP10 (pin 14) also functions as a power-on setting pin whose value is latched on the rising edge of RESET# (pin 4) to select configuation port addresses. Therefore, GP10 is a push-pull I/O port unlike the other GPIO ports, which are open-drained I/Os to support this power-on setting feature. GP11 (pin 13) could function as a card detection input if selected by SDI to support some MMC cards, which don't offer card detection feature through DATA3 pin. Table 5.1 DIRECTION BIT INVERSION BIT 0 = OUTPUT 0 = NON INVERSE 1 = INPUT 1 = INVERSE 0 0 Basic non-inverting output 0 1 Basic inverting output 1 0 Basic non-inverting input 1 1 Basic inverting input I/O OPERATION -8- W83L518D Table 5.2 GPIO PORT DATA REGISTER GP1 GP2 REGISTER BIT ASSIGNMENT GP I/O PORT BIT 0 GP10 BIT 1 GP11 BIT 2 GP12 BIT 3 GP13 BIT 4 GP14 BIT 5 GP15 BIT 6 GP16 BIT 7 GP17 BIT 0 GP20 BIT 1 GP21 BIT 2 GP22 BIT 3 GP23 BIT 4 GP24 BIT 5 GP25 BIT 6 GP26 BIT 7 GP27 6. CONFIGURATION REGISTER 6.1 Plug and Play Configuration W83L518D/W83L519D implement compatible PNP protocol to access configuration registers for setting up different types of configurations. There are four Logical Devices (Logical Device 0 to Logical Device 3) in W83L518D/W83L519D which correspond to four major functions: Smart Card Interface (logical device 0), Memory Stick Interface (logical device 1), GPIO (logical device 2) and SD Memory Interface (logical device 3). Each Logical Device has its own configuration registers (CR30 and above). Host can access those registers by writing an appropriate logical device number into logical device select register at CR07 first. -9- Publication Release Date: May 11, 2005 Revision 1.0 W83L518D 07h logical device select global registers 30h logical device control 3Fh 40h One set per logical device logical device configuration FEh 6.2 6.2.1 Compatible PnP Extended Function Register W83L518D/W83L519D provide two methods to enter Extended Function mode (compatible PnP) and access configuration registers dependent on value of HEFRAS (bit 6 of CR26. The corresponding power-on setting pin is pin 14) as follows: HEFRAS ADDRESS AND VALUE 0 write 83h to I/O address 2Eh twice 1 write 83h to I/O address 4Eh twice In Compatible PnP, a specific value (83h) must be written twice to the Extended Function Enable Register (EFER at I/O address 2Eh or 4Eh). Secondly, an index value (02h, 07h-FFh) must be written to the Extended Function Index Register (EFIR, I/O address at 2Eh or 4Eh which is the same as EFER) to identify which configuration register is to be accessed. User can then access the addressed configuration register through the Extended Function Data Register (EFDR, I/O address at 2Fh or 4Fh). After programming of the configuration register is completed, another specific value (0AAh) should be written to EFER to leave Extended Function mode to prevent inadvertent accesses to those configuration registers. User may write a "1" to bit 5 of CR26 (LOCKREG) to prevent configuration registers from accidental accesses. 6.2.2 Extended Functions Enable Register (EFER) After a power-on reset, W83L518D/W83L519D enters the default operation mode. A specific value must be programmed into the Extended Function Enable Register (EFER) so that configuration registers can be accessed. On a PC/AT system, its I/O address is 2Eh or 4Eh (as described in previous section). - 10 - W83L518D 6.2.3 Extended Function Index Register (EFIR), Extended Function Data Register (EFDR) After entering Extended Function mode, Extended Function Index Register (EFIR) must be written with an index value (02h, 07h-FEh) to specify which configuration register is to be accessed through Extended Function Data Register (EFDR). EFIR is a write-only register at I/O address 2Eh or 4Eh (as described in section 6.2.1) on a PC/AT system and EFDR is a read/write register at I/O address 2Fh or 4Fh. 6.3 Configuration Sequence To program configuration registers, specific configuration sequence must be followed: (1) Write 83h to EFER twice to enter Extended Function mode. (2) Select logical device select register by writing 07h to EFIR. (3) Select logical device by writing a value to EFDR. (4) Select control/configuration register by writing its index to EFIR. (5) Access selected control/configuration register through EFDR. (6) Repeat step 4 ~ 5 as needed. (7) Leave Extended Function mode by writing AAh to EFER. Step 2 and step 3 are not necessary for accessing global register (index 00h to 2Fh). 6.3.1 Software programming example The following example is written in Intel 8086 assembly language. EFER and EFIR are assumed to be at 2Eh, and EFDR is at 2Fh. Use 4Eh/4Fh instead of 2Eh/2Fh if HEFRAS (bit 6 of CR26) is set. ;----------------------------------------------------------------------------------; Enter Extended Function mode, interruptible double-write | ;----------------------------------------------------------------------------------MOV DX, 2Eh MOV AL, 83h OUT DX, AL OUT DX, AL ;----------------------------------------------------------------------------; Configure logical device 1, configuration register CRF0 | ;----------------------------------------------------------------------------MOV DX, 2Eh MOV AL, 07h OUT DX, AL MOV DX, 2Fh MOV AL, 01h OUT DX, AL ; point to Logical Device Number Reg. ; select logical device 1 - 11 - Publication Release Date: May 11, 2005 Revision 1.0 W83L518D ; MOV DX, 2Eh MOV AL, F0H OUT DX, AL MOV DX, 2Fh MOV AL, 3Ch OUT DX, AL ; select CRF0 ; update CRF0 with value 3CH ;-----------------------------------------; Exit extended function mode | ;------------------------------------------ 6.4 MOV DX, 2Eh MOV AL, AAh OUT DX, AL Global Registers CR02 (Default 00h, write only) Bit [7:1]: Reserved. Bit 0: SWRST =0 Normal operation. =1 Software reset. CR07 (Default 00h) Bit [7:0]: Logical Device Number. CR20 (read only) Bit [7:0]: Device ID number (higher byte). = 71h CR21 (read only) Bit [7:0]: Device ID number (lower byte) = 1Xh (for W83L518D) = 2Xh (for W83L519D) X: Revision number CR22 (Default 80h) Bit 7: SCPWD =0 Power down Smart Card interface. =1 No Power down. - 12 - W83L518D Bit 6: MSPWD =0 Power down Memory Stick interface. =1 No Power down. Bit 5: SDPWD =0 Power down SD memory card interface. =1 No Power down. Bit [4:0]: Reserved. CR23 (Default 00h) Bit 7: PME_EN. Power management event enable bit. =0 PME_L function is disabled. =1 Enable to issue a low pulse on PME_L when a power management event occurs. Bit 6: MSPME_EN. Memory Stick interface power management event enable bit. =0 Memory Stick interface power management event is disabled. =1 Enable Memory Stick interface power management event to issue a low pulse on PME_L when PME_EN is also enabled. Bit 5: SDPME_EN. SD memory card interface power management event enable bit. =0 SD memory card interface power management event is disabled. =1 Enable SD memory card interface power management event to issue a low pulse on PME_L when PME_EN is also enabled. Bit 4: SCPME_EN. Smart Card interface power management event enable bit. =0 Smart Card interface power management event is disabled. =1 Enable Smart Card interface power management event to issue a low pulse on PME_L when PME_EN is also enabled. Bit [3:0]: Reserved. CR24 (Default 00h) Bit 7: Reserved. Bit 6: MSPME_STS. Memory Stick interface power management event status bit. =0 No Memory Stick interface power management event occurs. =1 Memory Stick interface power management event occurs. Bit 5: SDPME_STS. SD memory card interface power management event status bit. =0 No SD memory card interface power management event occurs. =1 SD memory card interface power management event occurs. Bit 4: SCPME_STS. Smart Card interface power management event status bit. =0 No Smart Card interface power management event occurs. =1 No Smart Card interface power management event occurs. Bit [3:0]: Reserved. - 13 - Publication Release Date: May 11, 2005 Revision 1.0 W83L518D CR26 (Default 40h) Bit 7: Reserved Bit 6: HEFRAS, Extended Function Register Address Select. The corresponding power-on setting pin is GP10 (PHEFRAS, pin 14). The HEFRAS is defaulted to "1" if PHEFRAS is "0" and is defaulted to "0" if PHEFRAS is "1". =0 Extended Function Registers are at 2Eh/2Fh. =1 Extended Function Registers are at 4Eh/4Fh. Bit 5: LOCKREG =0 Enable accesses of Configuration Registers. =1 Disable accesses of Configuration Registers. Bit [4:0]: Reserved CR29 (Default 00h, only valid in W83L518D) Bit 7: Multi-function selection bit for pin 7 ~ 14 =0 Pin 7 ~ 14 function as Smart Card interface socket B. =1 Pin 7 ~ 14 function as GPIO1. Bit 6: Multi-function selection bit for pin 35 ~ 43 =0 Pin 35 ~ 43 function as MSI/SDI socket B. =1 Pin 35 ~ 43 function as GPIO2. Bit 5: Multi-function selection bit for pin 32 ~ 31 & pin 29 ~ 24. =0 Pin 32 ~ 31 and pin 29 ~ 24 function as MSA (MS interface card A). =1 Pin 32 ~ 31 and pin 29 ~ 24 function as SDA (SD interface card A). Bit 4: Multi-function selection bit for pin 43 ~ 41 & pin 39 ~ 35. =0 Pin 43 ~ 41 & pin 39 ~ 35 function as MSB (MS interface card B). =1 Pin 43 ~ 41 & pin 39 ~ 35 function as SDB (MS interface card B). Bit [3:0]: Reserved. 6.5 Logical Device 0 (Smart Card Interface) CR30 (Default 0x00) Bit [7:1]: Reserved. Bit 0: Logical device active bit. =0 Logical device is inactive. =1 Activates the logical device. CR60, CR61 (Default 0x00, 0x00) These two registers select Smart Card base address [0x100:0xFFF] on 8-byte boundary. CR70 (Default 0x00) Bit [7:4]: Reserved. Bit [3:0]: These bits select IRQ resource for Smart Card interface. - 14 - W83L518D CRF0 (Default 0x00) Bit 7: IRQ sharing control bit. =0 No IRQ sharing. =1 IRQ sharing. Bit 0: SCPSNT_POL (Smart Card PreSeNT POLarity). SCPSNT polarity bit. 6.6 =0 SCPSNT is active high. =1 SCPSNT is active low. Logical Device 1 (Memory Stick Interface) CR30 (Default 0x00) Bit [7:1]: Reserved. Bit 0: Logical device active bit. = 0: Logical device is inactive. = 1: Activates the logical device. CR60, CR61 (Default 0x00, 0x00) These two registers select MSI base address [0x100:0xFFF] on 8-byte boundary. CR70 (Default 0x00) Bit [7:4]: Reserved. Bit [3:0]: These bits select IRQ resource for MSI. CR74 (Default 0x04) Bit [7:4]: Reserved. Bit [3:0]: These bits select DRQ resource for MSI. CRF0 (Default 0x00) Bit [7:5]: Reserved. Bit 4: IRQ polarity control bit by level mode. = 0: IRQ is active high. = 1: IRQ is active low. Bit 3: IRQ polarity control bit by pulse mode. = 0: IRQ is active low. = 1: IRQ is active high. Bit 2: IRQ sharing control bit. = 0: No IRQ sharing. = 1: IRQ sharing. - 15 - Publication Release Date: May 11, 2005 Revision 1.0 W83L518D Bit 1: MS4 output polarity control bit. 0: MS4 output low. 1: MS4 output high. Bit 0: MS4 output enable bit. 0: MS4 output disable. 1: MS4 output enable. 6.7 Logical Device 2 (GPIO) CR30 (Default 00h) Bit [7:3]: Reserved. Bit 2: Individual disable/enable bit for GPIO2. =0 GPIO2 is disabled if bit 0 is also "0". =1 GPIO2 is enabled. Bit 1: Individual disable/enable bit for GPIO1. =0 GPIO1 is disabled if bit 0 is also "0". =1 GPIO1 is enabled. Bit 0: Logical device disable/enable bit. =0 GPIO1 and GPIO2 are disabled/enabled dependent on bit 1 and 2 respectively. =1 Activates GPIO1 and GPIO2. CR60, CR61 (Both default 00h) Base address configuration registers: programmable at addresses from 0100h to 0FF8h on 4-byte boundary. Base address + 0 and base address + 1 are for GPIO1 as direction register and data register respectively while base address + 2 and base address + 3 are for GPIO2 as direction register and data register respectively. CRF0 (GP10 ~ GP17 direction register. Default FFh) When set to "1", respective GPIO port is programmed as an input port. When set to a "0", respective GPIO port is programmed as an output port. CRF1 (GP10 ~ GP17 data register. Default 00h) If a port is programmed to be an output port, its respective bit can be read/written and output to respective pin. If a port is programmed to be an input port, its respective bit reflects what is on respective pin. CRF2 (GP10 ~ GP17 inversion register. Default 00h) When set to "1", respective incoming/outgoing port value is inverted. When set to "0", respective incoming/outgoing port value is the same as in data register. CRF3 (GP20 ~ GP27 direction register. Default FFh) When set to "1", respective GPIO port is programmed as an input port. When set to a "0", respective GPIO port is programmed as an output port. - 16 - W83L518D CRF4 (GP20 ~ GP27 data register. Default 00h) If a port is programmed to be an output port, its respective bit can be read/written and output to respective pin. If a port is programmed to be an input port, its respective bit reflects what is on respective pin. CRF5 (GP20 ~ GP27 inversion register. Default 00h) When set to "1", respective incoming/outgoing port value is inverted. When set to "0", respective incoming/outgoing port value is the same as in data register. 6.8 Logical Device 3 (SD Memory Interface) CR30 (Default 0x00) Bit [7:1]: Reserved. Bit 0: Logical device active bit. =0 Logical device is inactive. =1 Activates the logical device. CR60, CR61 (Default 0x00, 0x00) These two registers select SD Card interface base address [0x100:0xFFF] on 8-byte boundary. CR70 (Default 0x00) Bit [7:4]: Reserved. Bit [3:0]: These bits select IRQ resource for SD interface. CR74 (Default 0x00) Bit [7:4]: Reserved. Bit [3:0]: These bits select DRQ resource for SD interface. CRF0 (Default 0x01) Bit [7:6]: Reserved. Bit 5: Set the output value of the DATA3 pin when bit4 is setted 1. =0 The DATA3 pin will output low. =1 The DATA3 pin will output high. Bit 4: Set the DATA3 (MS1 or MSB1) pin to output pin. =0 Set the DATA3 pin to bi-direction pin. =1 Set the DATA3 pin to output pin. Bit 3: Reserved. Bit 2: Select the pole of the GP11 card-detect pin. =0 When detecting the low signal indicate the card is inserted and high signal indicate the card is extracted. =1 When detecting the high signal incicate the card is inserted and low signal indicate the card is extracted. - 17 - Publication Release Date: May 11, 2005 Revision 1.0 W83L518D Bit 1: Select GP11 pin to detect card. =0 Don’t use the GP11 pin to detect card. =1 Use the GP11 (SCBPWR_L) pin to detect card. Bit 0: Select DATA3 pin to detect card. =0 Don’t use the DATA3 (MS1 or MSB1) to detect card. =1 Use the DATA3 (MS1 or MSB1) pin to detect card. CRF1 (Default 0x01) Bit [7:4]: Reserved. Bit 3: Set the IRQ pole for level mode. =0 The IRQ is active high. =1 The IRQ is active low. Bit 2: Set the IRQ pole for pulse mode. =0 The IRQ is active low. =1 The IRQ is active high. Bit 1: Set the IRQ to level mode or pulse mode. =0 The IRQ is level mode. =1 The IRQ is pulse mode. Bit 0: Use debounce function for card-detect circuit. =0 No debouunce. =1 Use debounce function. 7. ORDERING INSTRUCTION PART NO. PACKAGE W83L518D 48-pin LQFP - 18 - REMARKS W83L518D 8. HOW TO READ THE TOP MARKING SMART@IO W83L518D 201GBSB 1st line: Winbond logo and the SMART@IO Trademark 2nd line: The chip part number. 3rd line: Tracking code 201 G B SB 201: packages made in '02, week 01 G: assembly house ID; O means OSE, G means GR, … BSB: IC revision - 19 - Publication Release Date: May 11, 2005 Revision 1.0 W83L518D 9. PACKAGE DRAWING AND DIMENSIONS Package- 48-pin LQFP HD D A A2 36 A1 25 37 24 48 13 HE E 1 12 b e c SEATING PLANE L Y L1 Controlling dimension : Millimeters Symbol A A1 A2 b c D E e HD HE L L1 Y 0 Dimension in inch Min 0.002 Nom 0.004 Max Dimension in mm Min Nom 0.10 Max 0.006 0.05 0.053 0.055 0.057 1.35 1.40 1.45 0.006 0.008 0.010 0.15 0.20 0.25 0.004 0.006 0.008 0.10 0.15 0.20 0.272 0.276 0.280 6.90 7.00 0.272 0.276 0.280 6.90 7.00 0.014 0.020 0.026 0.35 0.50 0.15 7.10 7.10 0.65 0.350 0.354 0.358 8.90 9.00 9.10 0.350 0.354 0.358 8.90 9.00 9.10 0.018 0.024 0.030 0.45 0.60 0.75 1.00 0.039 0.004 0 - 20 - 7 0.10 0 7 θ W83L518D 10. THE W83L518D SCHEMATIC XOUT Y1 R12 10 2 MSCLK R13 1M SD3 SD4 SD5 LAD3 LAD2 LAD1 LAD0 LAD[3:0] SERIRQ MS5 XIN XOUT SCRST# SCIO SCCLK SCPSNT SCPWCTL# SCLED VDD GP10/HEFRAS GP11/EX_CD U1 W83L518D_SB (LPC) 24 23 22 21 20 19 18 17 16 15 14 13 1 2 1 C6 4.7U 2 3 3VCC SW SPDT MS[5:1] SCRST# SCIO 14 SD1 SD2 SDCLK SD1 SD2 VDD3V SD3 SD4 SD5 LAD3 LAD2 LAD1 LAD0 SERIRQ C5 10P S1 2 XIN 8 37 38 39 40 41 42 43 44 45 46 47 48 C4 10P MSLED MSPWCTL# MS1 MS2 MS3 MS4 MS5 XIN XOUT 5VCC OUT 3VCC SDLED SDPWCTL# VCC SDPWCTL# SDLED SCC4 SCC8 MSLED MSPWCTL# VSS MSCLK MS1 MS2 MS3 MS4 2 SD[5:1] L1 2.2UH SCPSNT SCPWCTL# SCLED HEFRAS EX_CD R15 10 1 2 U2 48MHZ GND R14 10 1 2 36 35 34 33 32 31 30 29 28 27 26 25 1 SDCLK The LC resonance circuit is used to filter base frequency of 3rd overtone crystal. 48MHz SCC8 SCC4 1 1 SCCLK PCICLK LDRQ# LFRAME# LRESET# PME# VSS GP17 GP16 GP15 GP14 GP13 GP12 7 LFRAME# PCIRST# 5VCC 1 2 3 4 5 6 7 8 9 10 11 12 HEFRAS 1 R16 4.7K 2 Power-on strapping for 2E/2F (Config. Port) SD_3VCC 3VCC 3VCC R18 33 1 2 RP1 MOSFET P Q3 SDPWCTL# SD_3VCC 1 2 3VCC R20 330 R19 4.7K 1 8P4R-4.7K 2 1 SD Socket (1) Circuit. R17 10 1 PCICLK 2 4 6 8 PME# R21 10K D3 2 1 SD_3VCC LED J2 2 R22 LED SCLED R26 + C10 4.7K 1U 1 2 Q5 NPN SCPSNT 9 R31 1 4.7K 2 C1 C2 C3 C4 S1 D5 330 C5 C6 C7 C8 S2 5 6 7 8 LED R28 10K R30 1K 11 SD4 SD3 8 7 6 5 4 3 2 1 SDCLK SD2 SD1 SD5 Q6 NPN R29 9 SCIO SCC8 Wr_Pt EX_CD# EX_CD 10 SD4 SD3 Vss2 SDCLK Vdd Vss1 SD2 SD1 SD5 SD_SOCKET 1M 2 SCRST# SCCLK SCC4 1 2 3 4 1U SD_3VCC R24 R27 20K J3 Soft start to protect MOSFET(Optional) + C8 Soft start to protect MOSFET(Optional) SC_VCC R25 1K SC_VCC C9 0.1U 2 330 SDLED 10 5VCC SC_VCC SC_SOCKET R32 330 1 2 LED 3VCC Without SD LED function D6 R34 1K R35 SDLED 1 2 4.7K inbond 1 SC_VCC SC read/write LED D4 SC_VCC 1 2 1 1 Title Size B WINBOND ELECTRONICS CORP. Document Number W83L518D Recommend Circuit Date: Wednesday, October 02, 2002 Wr_Pt 2 5VCC MOSFET P Q4 R23 33 SCPWCTL# 2 1 3 5 7 C7 0.1U SC Socket (1) Circuit. Rev 0.6 Sheet 1 of 2 TheW83L518Dschematic - 21 - Publication Release Date: May 17, 2005 Revision 1.0 W83L518D Winbond Recommended Reader Board <<Connector Side>> MS_3VCC Memory Stick Socket (1) Circuit. 1 2 MS_3VCC 3VCC MOSFET P C1 0.1U 2 4.7K 1 MS2 MS3 MS4 MS5 MSCLK D2 R5 C3 200K 0.1U (OPTION:reserved for power-down) LED 2 PIN 1 : 2x5 ; 2.54 mm(pitch) (R_JP2) PIN 1 PIN 10 (R_JP1) PIN 10 MS_SOCKET 10 Q2 NPN 2 1 1 2 3 4 5 6 7 8 9 10 MS1 330 R_J1 J1 1U R6 1K MSLED R_JP1,2: 1x10 ; 2.0 mm(pitch) LED R3 + C2 Soft start to protect MOSFET(Optional) MS_3VCC R4 2 D1 Q1 1 1 R1 330 3VCC R2 33 MSPWCTL# PIN 6 MS read/write LED PIN 1 2 5 (R_J1) Note 1:The RESET# should be connected Extension Connectors 3VCC R7 1M 2 JP1,2: 1X10;pitch(2.0mm) JP3: 2X5 ;pitch(2.54mm) MS2 MS3 MS4 MS5 MSCLK MSPWCTL# MSLED 1 Note 6:For Note MS4 2 1 2 3 4 5 6 7 8 9 10 MS1 R10 1M 1 JP2 MS2 MS3 MS4 MS5 MSCLK MSPWCTL# MSLED trade marks and intellectual property rights of Memory Stick belong to SONY Corporation.Information check: http://www.memorystick.org JP1,2,3,4 are designed for Winbond recommended reader please meet following connector spec. 3VCC 2 3VCC MS1 Note 4:The Note 5:If R9 1M MS1 Note SD1 R8 1M SD4 2 1 2 3 4 5 6 7 8 9 10 1 SD2 SD3 SD4 SD5 SDCLK SDPWCTL# SDLED 1 JP1 SD2 SD3 SD4 SD5 SDCLK SDPWCTL# SDLED 1 3VCC SD1 SD1 SCPSNT R11 1M 5VCC SCPWCTL# SCC4 SCIO SCCLK 1 2 3 4 5 the recommended reader, please contact to Taiwan Zetatronic Industrial CO.,LTD(http://www.tzt.com.tw) There are some difference as following from previous version: 7: (Ver 0.1 --> Ver 0.2) (1)Added circuit(GP10/EX-CD)to implement to sockets with external card detection pin. (2)Modified pulled-high resistor for write_protect detection from 500 ohm to 4.7K ohm. (3)Added configuration port selection pin(GP10/HEFRAS) by power-on strapping. (Ver 0.2 --> Ver 0.3) (1)Added power-on strapping circuit of different configuration port.(2E/2F) (2)Modified pull-down resistor tied to SD1 from 200K ohm to 1M ohm. (Ver 0.3 --> Ver 0.4) (1)Modified some erroneous netname like SCPWR#,MSPWR# and SDPWR#. (2)DMA transaction cannot be supported in this version. (Ver 0.4 --> Ver 0.5) (1)Modified SD2,3,4,5 pull up to SD_3VCC. (2)Add without SD LED recommend circuit. (Ver 0.5 --> Ver 0.6) (1)Modified Note 3 . inbond 2 JP3 SCPWCTL# SCC4 SCIO SCCLK with a low asserted signal like PCIRST# on PCI bus or LREST#on LPC bus(active low) function of SD and MS can be used on versio A but two sockets interface can be implemented on version B. 3:If any of SC or MS/SD function isn't intened to use, signals like SCPSNT/SD1/MS1 should be tied to a pull-down resistor and SD4/MS4 should be tied to a pull-high resistors. (recommended: 1M Ohm ) Note 2:There is either 6 7 8 9 10 SCRST# SCLED SCC8 SCPSNT SCRST# SCLED SCC8 SCPSNT WINBOND ELECTRONICS CORP. Title HEADER 5X2 Size B Date: - 22 - Document Number W83L518D Recommend Circuit Wednesday, October 02, 2002 Rev 0.6 Sheet 2 of 2 W83L518D 11. REVISION HISTORY VERSION DATE PAGE DESCRIPTION st 1.0 02/Jul. 1 Release 1.1 02/Sep. Recommend circuit modification. 1.11 02/Oct. Recommend circuit modification. 1.12 03/Nov. The Functions modification. (Page 2) A1 May 17, 2005 23 ADD Important Notice Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. - 23 - Publication Release Date: May 17, 2005 Revision 1.0