ASAHI KASEI [AK6510C/12C] AK6510C / 12C SPI bus 32K/64Kbit Serial CMOS EEPROM Features Advanced CMOS EEPROM Technology Single Voltage Supply: 1.8V to 5.5V AK6510C: 32Kbits; 4096 x 8 organization AK6512C: 64Kbits; 8192 x 8 organization SPI Serial Interface Compatible Low Power Consumption 0.8µA Max. (Standby mode) High Reliability Endurance: 1000K E/W cycles / Address Data Retention: 10 Years Special Features 32 byte Page Write Mode Block Write Protection (Protect 1/4,1/2 or Entire Array) Automatic write cycle time-out with auto-ERASE Software and Hardware controlled Write Protection Self timed Programming Cycle: 5msec. Max. Ideal for Low Density Data Storage Low cost, space saving, 8-pin SSOP/SONW package SO DATA REGISTER SI INSTRUCTION REGISTER INSTRUCTION DECODE, CONTROL AND CLOCK GENERATION R/W AMPS AND AUTO ERASE EEPROM AK6510C=32Kbit ADD. BUFFERS DECODER AK6512C=64Kbit CS VPP SW SCK HOLD VREF VPP GENERATOR STATUS REGISTER WP Block Diagram DAP02E-04 2005/03 - 1 - ASAHI KASEI [AK6510C/12C] General Description The AK6510C/12C is a 32768/65536-bit, serial, read/write, non-volatile memory device fabricated using an advanced CMOS EEPROM technology. The AK6510C/12C has 32768-bits/65536-bits of memory organized as 4096/8192 registers of 8 bits each. The AK6510C/12C can operate all function under wide operating voltage range: 1.8V to 5.5V. The charge up circuit for high voltage generation needed for write operations is integrated. The AK6510C/12C serial interface is compatible to a SPI bus. The AK6510C/12C has 6 instructions: READ, WRITE, WREN (write enable), WRDI (write disable), RDSR (read status register), and WRSR (write status register). Each instruction is organized by an op-code (8bits), address (16bits), and data (8bits). When input level of CS pin changed from high level to low level, AK6510C/12C can receive instructions. Pin Configurations AK6510CM/12CM CS SO WP GND 1 2 3 4 8 7 6 5 AK6510CL/12CL VCC HOLD SCK SI CS SO WP GND 1 2 3 4 8 7 6 5 VCC HOLD SCK SI 8pin SONW 8pin SSOP Pin name Functions CS Chip Select input SCK Serial Clock input SI Serial Data input SO Serial Data output WP Write Protect input HOLD Hold input VCC Power Supply GND Ground Type of Products Model AK6510CM AK6510CL AK6512CM AK6512CL Memory size 32K bits 64K bits Temp. Range -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C DAP02E-04 VCC 1.8V to 5.5V 1.8V to 5.5V 1.8V to 5.5V 1.8V to 5.5V Package 8pin Plastic SSOP 8pin Plastic SONW 8pin Plastic SSOP 8pin Plastic SONW 2005/03 - 2 - ASAHI KASEI [AK6510C/12C] Data Transfer An IC that outputs the clock is called "MASTER", an IC that receives the clock is called "SLAVE". The AK6510C/12C operates as a SLAVE. Data is written to the SI pin and read from SO pin. The MSB is transmitted first. After CS pin changes hi level to low level, AK6510C/12C receives the first data bit on the SI pin synchronously with the rising edge of the input pulse of serial clock. While CS pin is high level, the data input to the SI pin is don’t care and SO pin indicates Hi-Z. All the functions are organized 8 bits of op-code, address, and data. If there is an invalid op-code, the AK6510C/12C ignores the address and data information and SO pin indicates Hi-Z. In order to input new op-code, CS pin should be toggled. Hold AK6510C/12C has a HOLD pin that can hold the data transfer. When HOLD changes high to low while SCK is low, the data transfer stops. After the HOLD pin changes low to High while SCK is low, the data transfer starts again. While the data transfer is paused, AK6510C/12C ignores the clock on the SCK line. Write Protect AK6510C/12C has status registers. When the WPEN bit in the status registers is "1", Write Protect function is enabled. When WPEN bit is "1" and WP pin is low level, the status register is protected from write function. When WP pin becomes low level while the WRITE to the status register instruction is written, the AK6510C/12C doesn’t accept the instruction. When the WP pin changes low level while the internal programming, the programming function continues. When the WPEN bit is "0", WP pin function is disabled. Even if WP pin is fixed to low level, the WRITE function to the status register can be done. When the WP pin is high level, AK6510C/12C can accept all of READ and WRITE functions. DAP02E-04 2005/03 - 3 - ASAHI KASEI [AK6510C/12C] Pin Description CS (Chip Select Input) When CS changes high level to low level, the AK6510C/12C can receive the instructions. CS should be kept low level while receiving op-code, address and data, and while outputting data. When CS is high level, SO indicate Hi-Z. SCK (Serial Clock Input) The SCK clock pin is the synchronous clock input for input/output data. SI (Serial Data Input) The op-code, address, and data are written to the SI pin. SO (Serial Data Output) The SO pin outputs the data from memory array and status register. WP (Write Protect Input) The WP pin controls the write function to the status register. When the WPEN bit in the status register is "0", the function of WP pin becomes disable. Then the status register can be programmable when the WEN bit in the status register is "1". And it does not depend on the status of WP pin. When the WPEN bit is "1", the function of WP is enabled. Then the status register can not be programmable when the WEN bit is "1" and the status of WP pin is low. When the WPEN bit is "1", WP pin is high and WEN bit is "1", AK6510C/12C can accept the WRITE instruction to the status registers. During the instruction input, WP pin should keep high or low level. HOLD (Hold Input) The HOLD pin can hold the data transfer. When the HOLD pin changes hi to low while the SCK is low, the data transfer is held. And the transfer starts when the HOLD pin changes low to high while the SCK is low. While the holding the data transfer, AK6510C/12C ignores the clock signal on SCK pin. DAP02E-04 2005/03 - 4 - ASAHI KASEI [AK6510C/12C] Function Description AK6510C/12C has six instructions. The instruction can be input after the CS pin changes high to low. All the instructions are MSB first. Instruction Address Op-code Data Description READ 0000 X011 X X X A12-A8 A7-A0 D7-D0 (out) Read from Memory Array WRITE 0000 X010 X X X A12-A8 A7-A0 D7-D0 (in) Write to Memory Array WREN 0000 X110 ------ ------ Write Enable WRDI 0000 X100 ------ ------ Write Disable RDSR 0000 X101 Bit7-Bit0 (out) ------ ------ Read Status Register WRSR 0000 X001 Bit7-Bit0 (in) ------ ------ Write Status Register X: don’t care AK6510C: A12 is don’t care Table 1. Instruction set for AK6510C/12C WREN (WRITE ENABLE) / WRDI (WRITE DISABLE) The WRITE function can be accepted only in the status of Write Enable. After VCC is applied, AK6510C/12C is in the status of Write Disable. After the function of WRDI, AK6510C/12C cannot accept any programming function. CS SCK SI 0 0 1 0 2 0 3 4 X 0 5 1 6 1 7 0 Hi-Z SO X = don’t care WREN CS SCK SI SO 0 0 1 0 2 0 3 0 4 X 5 1 6 0 7 0 Hi-Z X = don’t care WRDI DAP02E-04 2005/03 - 5 - ASAHI KASEI [AK6510C/12C] RDSR (READ STATUS REGISTER) The RDSR function is used to read the data in the STATUS register. The STATUS register has RDY bit, WEN bit, BP0/BP1 bit and WPEN bit. RDSR function can be used to read READY/BUSY status bit, WRITE ENABLE/DISABLE bit, and BLOCK PROTECT bit. These bits can be set by WRSR function. CS SCK 0 SI 0 1 0 2 3 0 0 4 X 5 6 1 0 Hi-Z SO 7 8 9 10 11 12 13 14 1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 X = don’t care RDSR Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 WPEN X X X BP1 BP0 WEN RDY Register Definition WPEN WP pin set bit (programmable) See Table 3. BP0 / BP1 Block Protect bit for EEPROM memory array (programmable) See Table 4. WEN WRITE ENABLE / DISABLE bit (READ only) This is set by WREN/WRDI function. WEN=0 : WRITE DISABLE WEN=1 : WRITE ENABLE RDY READY/BUSY status bit (READ only) RDY=0 : READY RDY=1 : BUSY Table 2. Status Register Configuration DAP02E-04 2005/03 - 6 - ASAHI KASEI [AK6510C/12C] WRSR (WRITE STATUS REGISTER) The WRSR instruction can set the Write Protect Block size of the memory array. AK6510C/12C has 4 Blocks of memory arrays. Write Protect Block size can be selected from 1/4, 1/2 and whole memory array. The block, which is set by Write Protect, is Read only. BP0 bit, BP1 bit, and WPEN bit are programmable with EEPROM memory cell bits. The characteristics of those bits (WREN, tE/W, RDSR) are same as the EEPROM memory array. WP pin function can be set by WPEN (WRITE PROTECT ENABLE) bit which is defined by WRSR function. When WP pin is low level and WPEN bit is "1", the WRITE function to Status register, which has WPEN bit and BP0/BP1 bit, and to Write Disable Block is not performed. Then WRITE function is performed only to the Write enable block. When WP pin is "1" or WPEN bit is "0", then the function of WP pin is disabled and WRITE function to the Status Register is performed. WREN function should be done before WRSR function. And after the Programming function, AK6510C/12C becomes Write Disable status automatically. CS SCK SI 0 0 1 0 2 0 3 0 4 X 5 0 6 7 0 8 9 10 11 12 13 14 15 1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hi-Z SO X = don’t care WRSR WPEN Bit WP Pin WEN Bit Write Protected Block Not Protected Block Status Register 0 X 0 WRITE Disable WRITE Disable WRITE Disable 0 X 1 WRITE Disable WRITE Enable WRITE Enable 1 Low 0 WRITE Disable WRITE Disable WRITE Disable 1 Low 1 WRITE Disable WRITE Enable WRITE Disable X High 0 WRITE Disable WRITE Disable WRITE Disable X High 1 WRITE Disable WRITE Enable WRITE Enable Table 3. WPEN function Status Register bits BP1 BP0 0 0 0 1 1 0 1 1 Write Protected Block AK6510C AK6512C none none C00h - FFFh 1800h - 1FFFh 800h - FFFh 1000h - 1FFFh 000h - FFFh 0000h - 1FFFh Table 4. Write Protected Block Size DAP02E-04 2005/03 - 7 - ASAHI KASEI [AK6510C/12C] WRITE (WRITE SEQUENCE) WRITE instruction can start the WRITE function to the memory cell array. After CS pin changes high to low, op-code, address and data are input from SI pin. After the instruction input, the internal programming cycle starts when CS pin changes low to high. After the instructions are inputted, CS pin should change low to high after the last data bit (D0) inputs and before next SCK clock rises. Write function can start only at this timing. AK6510C/12C can indicate the BUSY status by using RDSR instruction and READ the RDY bit (Bit0) in the status register. RDY is "1" indicates AK6510C/12C is in the programming cycle, and RDY is "0" indicates AK6510C/12C is in the READY status. AK6510C/12C outputs the "FF" when RDSR instruction executes during the programming cycle. Only RDSR instruction can be accepted during programming cycle. AK6510C/12C has Page Write mode, which can write the data within 32 bytes with one programming cycle. The input data sent to the shift register within 32 bytes. If the number of bytes exceeded 32, the address counter rolls over to the first address of the page. Internal programming cycle starts after CS pin changes low to high. After WRITE instruction, AK6510C/12C changes to Write Disable status automatically. AK6510C/12C needs WREN instruction before every WRITE instruction. When WRITE instruction is done while AK6510C/12C is in Write Disable status, WRITE instructions are ignored and AK6510C/12C becomes standby status after CS changes to high. AK6510C/12C can accept the next instruction after CS becomes low. WRITE instruction cannot write the data into the address of the protected block. CS SCK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 22 23 24 25 30 31 Data(n) SI 0 0 0 0 X 0 1 0 X X X A12 A11 A10 A1 A0 D7 D6 D1 D0 Hi-Z SO CS SCK 32 33 34 35 36 37 38 39 40 Data(n+1) SI SO Data(n+31) D7 D6 D5 D4 D3 D2 D1 D0 D7 D0 D7 D6 D5 D4 D3 D2 D1 D0 Hi-Z X = don’t care AK6510C: A12 is don't care WRITE DAP02E-04 2005/03 - 8 - ASAHI KASEI [AK6510C/12C] READ (READ SEQUENCE) After CS changes high to low, the op-code and address are sent on SI pin and the data (D7-D0) read from SO pin. After 1 byte of data output, internal address register is incremented, and the next byte of data is outputted. After READ the data in the highest address, the address register rolls over to the lowest address. After the last bit of the address shift into the register, the input data on SI pin is ignored. CS SCK SI SO 0 0 1 0 2 0 3 0 4 X 5 0 6 1 7 1 8 X 9 X 10 11 12 13 X A12 A11 A10 Hi-Z 22 A1 23 24 25 29 30 A0 D7 D6 D2 D1 D0 X = don’t care AK6510C: A12 is don't care READ DAP02E-04 2005/03 - 9 - ASAHI KASEI [AK6510C/12C] Absolute Maximum Ratings Parameter Power Supply All Input Voltages with Respect to Ground Ambient Storage Temperature Symbol VCC VIO Min -0.6 -0.6 Max +6.5 VCC+0.6 Unit V V Tst -65 +150 °C Stress above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum conditions for extended periods may affect device reliability. Recommended Operating Condition Parameter Power Supply Ambient Operating Temperature Symbol VCC Ta DAP02E-04 Min 1.8 -40 Max 5.5 +85 Unit V °C 2005/03 - 10 - ASAHI KASEI [AK6510C/12C] Electrical Characteristics (1) D.C. ELECTRICAL CHARACTERISTICS (1.8V≤VCC≤5.5V, -40°C≤Ta≤85°C, unless otherwise specified) Parameter Current Dissipation (WRITE) Current Dissipation (READ) Current Dissipation (Standby) Input High Voltage Input Low Voltage Output High Voltage Symbol ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 ICCS Condition VCC=5.5V, fSCK=5.0MHz, VCC=2.5V, fSCK=2.5MHz, VCC=1.8V, fSCK=1.0MHz, VCC=5.5V, fSCK=5.0MHz, VCC=2.5V, fSCK=2.5MHz, VCC=1.8V, fSCK=1.0MHz, VCC=5.5V VIH1 VIH2 VIL1 VIL2 VOH1 2.5V≤VCC≤5.5V 1.8V≤VCC<2.5V 2.5V≤VCC≤5.5V 1.8V≤VCC<2.5V 4.5V≤VCC≤5.5V IOH=-2mA 2.5V≤VCC<4.5V IOH=-0.4mA 1.8V≤VCC<2.5V IOH=-0.1mA 4.5V≤VCC≤5.5V IOL=3.0mA 2.5V≤VCC<4.5V IOL=1.6mA 2.5V≤VCC<4.5V IOL=1.0mA 1.8V≤VCC<2.5V IOL=1.0mA VCC=5.5V, VIN=VCC/GND VOH2 VOH3 Output Low Voltage VOL1 VOL2 VOL3 VOL4 Input Leakage CS, SCK, DI pins WP, HOLD pins ILI Output Leakage SO pin ILO Min. Max. 2.0 1.5 1.0 1.0 0.2 0.1 0.8 Unit mA mA mA mA mA mA µA 0.7xVCC 0.8xVCC -0.3 -0.3 VCC-0.5 VCC+0.5 VCC+0.5 0.3xVCC 0.2xVCC V V V V V *1 *1 *1 *1 *1 *1 *2 VCC-0.2 V VCC-0.2 V VCC=5.5V, VOUT=VCC/GND 0.4 V 0.4 V 0.2 V 0.2 V ±1.0 µA ±1.0 µA *1: VIN=VIH/VIL, SO=open *2: CS=VCC, VIN=VCC/GND, WP,HOLD=VCC, SO=open (2) CAPACITANCE (Ta=25°C, fSCK=1MHz, VCC=5.0V) Parameter Output Capacitance SO pin Input Capacitance CS, SCK, SI pins Symbol CO VO=0V CIN Condition VIN=0V Min. Max. 8.0 Unit pF 6.0 pF Note: These parameters are not 100% tested. These are the sample value. DAP02E-04 2005/03 - 11 - ASAHI KASEI [AK6510C/12C] (3) A.C. ELECTRICAL CHARACTERISTICS 1 (1.8V≤VCC≤5.5V, -40°C≤Ta≤85°C, unless otherwise specified) Parameter SCK Frequency SCK Setup Time CS Setup Time SCK Pulse Width SCK Rise Time SCK Fall Time Data Setup Time *3 *3 Data Hold Time Data Rise Time Data Fall Time SO pin Output Delay SO pin Hi-Z Time SO pin Output Hold Time CS Hold Time SCK Hold Time CS High Time *3 *3 Symbol fSCK1 fSCK2 fSCK3 tSKSH1 tSKSH2 tSKSH3 tCSS1 tCSS2 tCSS3 tSKW1 tSKW2 tSKW3 tRC tFC tDIS1 tDIS2 tDIS3 tDIH1 tDIH2 tDIH3 tRD tFD tPD1 tPD2 tPD3 tOZ1 tOZ2 tOZ3 tOHD tCSH1 tCSH2 tCSH3 tSKH1 tSKH2 tSKH3 tCS1 tCS2 tCS3 Condition 4.5V≤VCC≤5.5V 2.5V≤VCC<4.5V 1.8V≤VCC<2.5V 4.5V≤VCC≤5.5V 2.5V≤VCC<4.5V 1.8V≤VCC<2.5V 4.5V≤VCC≤5.5V 2.5V≤VCC<4.5V 1.8V≤VCC<2.5V 4.5V≤VCC≤5.5V 2.5V≤VCC<4.5V 1.8V≤VCC<2.5V Min. Max. 5.0 2.5 1.0 50 50 50 90 200 400 90 200 400 2 2 4.5V≤VCC≤5.5V 2.5V≤VCC<4.5V 1.8V≤VCC<2.5V 4.5V≤VCC≤5.5V 2.5V≤VCC<4.5V 1.8V≤VCC<2.5V 20 40 60 30 50 100 2 2 60 150 340 100 240 500 4.5V≤VCC≤5.5V 2.5V≤VCC<4.5V 1.8V≤VCC<2.5V 4.5V≤VCC≤5.5V 2.5V≤VCC<4.5V 1.8V≤VCC<2.5V 4.5V≤VCC≤5.5V 2.5V≤VCC<4.5V 1.8V≤VCC<2.5V 4.5V≤VCC≤5.5V 2.5V≤VCC<4.5V 1.8V≤VCC<2.5V 4.5V≤VCC≤5.5V 2.5V≤VCC<4.5V 1.8V≤VCC<2.5V *3: These parameters are not 100% tested. DAP02E-04 0 90 200 400 50 50 50 100 200 300 Unit MHz MHz MHz ns ns ns ns ns ns ns ns ns µs µs ns ns ns ns ns ns µs µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns These are the sample value. 2005/03 - 12 - ASAHI KASEI [AK6510C/12C] (4) A.C. ELECTRICAL CHARACTERISTICS 2 (1.8V≤VCC≤5.5V, -40°C≤Ta≤85°C, unless otherwise specified) Parameter HOLD Setup Time 1 HOLD Hold Time 1 HOLD Setup Time 2 HOLD Hold Time 2 HOLD Low to Output Hi-Z HOLD High to Output Low-Z Selftimed Programming Time Endurance Symbol tHFS1 tHFS2 tHFS3 tHFH1 tHFH2 tHFH3 tHRS1 tHRS2 tHRS3 tHRH1 tHRH2 tHRH3 tHOZ1 tHOZ2 tHOZ3 tHPD1 tHPD2 tHPD3 tWR *4 Condition 4.5V≤VCC≤5.5V 2.5V≤VCC<4.5V 1.8V≤VCC<2.5V 4.5V≤VCC≤5.5V 2.5V≤VCC<4.5V 1.8V≤VCC<2.5V 4.5V≤VCC≤5.5V 2.5V≤VCC<4.5V 1.8V≤VCC<2.5V 4.5V≤VCC≤5.5V 2.5V≤VCC<4.5V 1.8V≤VCC<2.5V 4.5V≤VCC≤5.5V 2.5V≤VCC<4.5V 1.8V≤VCC<2.5V 4.5V≤VCC≤5.5V 2.5V≤VCC<4.5V 1.8V≤VCC<2.5V Min. 40 90 200 40 90 200 40 90 200 40 90 200 Max. 100 150 250 100 150 250 5 5.5V, 25°C, Page Write 1,000,000 *4: These parameters are not 100% tested. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms E/W cycles / Address These are the sample value. AC Measurement Condition Load Capacitance CL=100pF DAP02E-04 2005/03 - 13 - ASAHI KASEI [AK6510C/12C] Synchronous Data Timing tCS tCSS CS tSKSH tSKW tSKW tRC tFC SCK tDIS SI 0 tDIH tFD 0 tRD 0 Hi-Z SO Instruction Input "H" CS "L" tSKW tSKW SCK tDIS SI tDIH A1 A0 tPD SO Hi-Z tOHD D7 tPD D6 Data Output (READ) DAP02E-04 2005/03 - 14 - ASAHI KASEI [AK6510C/12C] tCS tCSS CS tCSH tSKH tSKSH SCK SI 0 tOHD tPD SO tOZ D1 D0 Hi-Z Data Output (READ) CS tCSH tSKH SCK SI SO D2 D1 D0 Hi-Z Data Input (WRITE) DAP02E-04 2005/03 - 15 - ASAHI KASEI [AK6510C/12C] "H" CS "L" tHFS tHRS tHFH tHRH SCK tDIS SI n+1 tHOZ SO Dn+1 n n-1 Dn Dn-1 tHPD Hi-Z Dn HOLD Hold DAP02E-04 2005/03 - 16 - IMPORTANT NOTICE • These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. 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