ASAHI KASEI [AKD5394A] AKD5394A AK5394A Evaluation Board Rev.B GENERAL DESCRIPTION AKD5394A is an evaluation board for AK5394A, the 24bit A/D converter for professional audio. It has analog input buffer circuits, clock generator circuits, and digital audio interfaces, therefore it can achieve the interface with digital audio systems via optical connector or BNC connector. And it can achieve the direct interface with AKM’s D/A converter evaluation boards via 10-line flat cable. Ordering guide AKD5394A --- AK5394A Evaluation Board FUNCTION • Analog input buffer circuits • Clock generator circuits • 2 type digital audio interfaces - Optical output or COAX output by DIT(AK4103A) - Direct interface with AKM’s D/A converter evaluation boards via 10-line flat cable • BNC connector for external clock input 3.0∼5.25V 4.75∼5.25V GND COAX AK4103A (DIT) Opt Out Lch Input Rch Buffer AK5394A D/A Data 10pin Header Clock Generator Figure 1. AKD5394A Block Diagram * Circuit diagram and PCB layout are attached at the end of this manual. < KM064804> 2005/05 -1- ASAHI KASEI [AKD5394A] EVALUATION BOARD MANUAL Operation sequence 1) Set up the power supply lines. [+15V] (Green) [-15V] (Blue) [5394_VA] (Red) [5394_VD] (Orange) [4103_VD] (Red) [AGND] (Black) [DGND] (Black) = +15V = -15V = 4.75~5.25V : VA of AK5394A = 3.0~5.25V : VD of AK5394A = 4.75~5.25V : VDD of AK4103A = 0V : Analog Ground(Include AGND and DGND of AK5394A) = 0V : Digital Ground(Logic part) When “5394_VD” is operated on 3.0~4.75V, JP15(IF/5V) should be connected to “5394_VD”. Each supply line should be distributed from the power supply unit. 2) Set-up the evaluation modes, jumper pins and DIP switches. (See the followings.) 3) Power on. The AK5394A and AK4103A should be reset once by bringing SW1 (PDN) to “L” after power-on. After that, release the reset by bringing SW1 (PDN) to “H”. Keep SW1(PDN) “H” during normal operation. < KM064804> 2005/05 -2- ASAHI KASEI [AKD5394A] Evaluation mode 1) Use DIT (Optical connector or BNC connector) <default> 2) Use AKM’s D/A evaluation board 3) Receive interface signal : MCLK, SCLK(BICK), LRCK from external source 1) Use DIT (Optical connector or BNC connector) <default> PORT2(TOTX176) or J5(TX) are used. It is able to send A/D converted data through optical connector or BNC connector. And it is able to connect to AKM’s D/A evaluation board and digital amp. When MCLK is received from external source through BNC connector (J6), JP2(CLK) should be connected to “BNC” side, and JP16(XTE) should be short. The setting of JP7, JP9, JP11, JP12 and JP13 should be adjusted to the AK5394A’s conditions(clock ratio, data format, etc).(Refer to setting of jumper pin.) JP2 JP11 JP13 CLK BICK LRCK1 HC74 12.288M X’tal 6.144M BNC 3.072M 74HC4040 Figure2. Setting of jumper pin (Use DIT) <default> 2) Use AKM’s D/A evaluation board It is able to evaluate AKM’s D/A evaluation board connecting to PORT3(EXT) via 10pin flat cable. When MCLK, SCLK(BICK) and LRCK are sent to a D/A board, setting of jumper pin is the same as “1)”. When MCLK, SCLK(BICK) and LRCK are received from a D/A board, setting of jumper pin is the same as “3)”. JP2 JP11 JP13 CLK BICK LRCK1 HC74 12.288M X’tal 6.144M BNC 3.072M 74HC4040 Figure3. Setting of jumper pin (Use AKM’s D/A evaluation board) 3) Receive interface signal : MCLK, SCLK(BICK), LRCK from external source PORT3(EXT) is used. JP11 and 12 should be open. The setting of JP7 and JP9 should be adjusted to the AK5394A’s conditions(clock ratio, data format, etc).(Refer to setting of jumper pin.) JP2 JP11 JP13 CLK BICK LRCK1 12.288M X’tal BNC HC74 6.144M 3.072M 74HC4040 Figure4. Setting of jumper pin (Receive interface signal) < KM064804> 2005/05 -3- ASAHI KASEI [AKD5394A] Setting of DIP switch 1. Polarity of DIP switch Refer to table below, before setting of DIP switch. (Normally, “ON” is “H”, “OFF” is “L”.) Polarity of DIP switch : SW2(AK5394A), SW3(AK4103A) DFS1 ON OFF H L V1 H L ON OFF DFS0 HPFE SMODE2 SMODE 1 H H H H L L L L Table1. Polarity of DIP switch: SW2 FS0 FS1 FS2 FS3 CKS0 CKS1 H H H H H H L L L L L L Table2. Polarity of DIP switch: SW3 ZCAL H L DIF H L 2. Setting of DIP switch : SW2(AK5394A), SW3(AK4103A) (1) Setting of DIP switch : SW2(AK5394A) Sampling Speed DFS1 (SW2-1) DFS0 (SW2-2) LRCK (fs) SCLK MCLK Normal Double Quad OFF OFF ON OFF ON OFF ~54kHz ~128fs 256fs ~108kHz ~64fs 128fs ~216kHz ~64fs 64fs (default) Table3. Setting of DFS1, DFS0 (In the case of Quad Speed, MCLK of AK4103A is 128fs.) SMODE2 (SW2-4) OFF OFF ON ON SMODE1 (SW2-5) Audio Format OFF Slave Mode (default) ON Master Mode OFF I2S Slave Mode ON I2S Master Mode Table4. Setting of SMODE2, SMODE1 [SW2-6]: Calibration pin “OFF”: VCOML, VCOMR (default) “ON”: Analog input pin (AINL±, AINR± ) [SW2-3]: HPFE “ON”: Enable “OFF”: Disable (default) < KM064804> 2005/05 -4- ASAHI KASEI [AKD5394A] (2) Setting of DIP switch : SW3(AK4103A) CKS1 (SW3-6) OFF OFF MCLK LRCK ON 128fs 28~216kHz OFF 256fs 28~108kHz (default) Table5.Setting of system clock DIF0 (SW3-8) OFF ON CKS0 (SW3-7) Audio Format BICK 24bit, Left Justified 48~128fs (default) 24bit, I2S 50~128fs Table6. Audio format of AK4103A [SW3-2,3,4,5] : Set sampling frequency of channel status. (default is all “OFF”.) [SW3-1] : Set validity of channel status. (default is “OFF”.) 3. Setting of clock Setting of clock of AK5394A and AK4103A LRCK(fs) MCLK 48kHz 256fs 96kHz 192kHz 128fs 64fs BICK 128fs 64fs 64fs 64fs JP9 JP11 JP12 JP13 6.144M 12.288M 48k HC74 3.072M 12.288M 6.144M 96k HC74 12.288M 12.288M 192k HC74 Table7. System clock example <KM064804> (default) 2005/05 -5- ASAHI KASEI [AKD5394A] Setting of jumper pin [JP1] (5394_VA) : select the source of power supply for VA pin of AK5394A. Short : supply from the regulator(T1) on board (default) (In this case, the jack of “5394_VA” should be open.) Open : supply from the jack of “5394_VA” [JP2] (CLK) : select the source of MCLK for AK5394A and AK4103A. (Excepting the case of receiving from external source, SCLK(BICK) and LRCK for AK5394A and AK4103A are generated by dividing MCLK which is selected on JP2.) X’tal : supply from X’tal oscillator(X1) on board. (default) (Use 24.5760MHz as frequency of X’tal Oscillator.) BNC : supply from external source through BNC connector(J6) [JP3, JP4, JP5, JP6] (BNC) : select the connector for analog input. Short : use BNC connectors(J2, J4). Open : use XLR(Cannon) connectors(J1, J3). (default) [JP7] (4103_MCLK) : select the frequency of MCLK for AK4103A. (Note1) CLK : x1 HC4040 : x 1/2 (default) [JP9] (5394_MCLK) : select the frequency of MCLK for AK5394A. (Note1) 24.576M (Note2) : x 1 12.288M (Note2) : x 1/2 (default) [JP11] (BICK) : select the frequency of SCLK(BICK) for AK5394A and AK4103A. (Note1) 12.288M (Note2) : x 1/2 6.144M (Note2) : x 1/4 (default) 3.072M (Note2) : x 1/8 [JP12] (LRCK) : select the frequency of LRCK for AK5394A and AK4103A. (Note1) 192k (Note2) : x 1/128 96k (Note2) : x 1/256 48k (Note2) : x 1/512 (default) [JP13] (LRCK1) : select the adjust of the phase of LRCK and SCLK(BICK) for AK5394A and AK4103A. 74HC4040 : supply LRCK without the adjust of the phase of LRCK and SCLK(BICK). 74HC74 : supply LRCK after the adjust of the phase of LRCK and SCLK(BICK) by 74HC74. (default) [JP15] (IF/5V) : select the source of power supply for digital logic part. 5394_VD : supply from the jack of “5394_VD” (default) (Use this jack when VD of AK5394A is operated in 3.3V.) 4103_VD : supply from the jack of “4103_VD”. [JP16] (XTE) : select X’tal oscillator(X1) on board. Short : not use X’tal oscillator(X1) on board. Open : use X’tal oscillator(X1) on board. (default) (Note1) Select the ratio to the frequency of (PORT3, J6 or X1). (Note2) The value assumed that the frequency of (PORT3, J6 or X1) is 24.576MHz. <KM064804> 2005/05 -6- ASAHI KASEI [AKD5394A] Function of the toggle SW [SW1](PDN) : Reset AK5394A and AK4103A, bringing it to “L” once, after power-on. And then, release the reset, bringing it to “H”. Keep it “H” during normal operation. (Upper side is “H”, and lower side is “L”.) Analog input buffer circuit An analog input buffer circuit example (1st order HPF; fc=0.70Hz, 2nd order LPF; fc=320kHz, gain=-14.5dB) is shown in Figure 5. The analog signal is able to input through XLR or BNC connectors. (For BNC input, jumper should be short. For XLR input, jumper should be open.) The input level of this circuit is +/-12.7Vpp (AK5394A: +/-2.4Vpp Typ.). When using this circuit, analog characteristics at fs=48kHz is DR=120dB, S/(N+D)=105dB. 4.7k 4.7k Analog In VP+ Vin- + 12.7Vpp 620 12.7Vpp Jumper 1n 68µ 3.3k Bias VPXLR 91 + 2.4Vpp AK5394A AIN+ NJM5534 NJM5534 2.2n VA+ 620 10k Bias + 10k 10µ 0.1µ 1n 68µ Jumper VA=+5V 3.3k Vin+ - 91 + 12.7Vpp NJM5534 Bias AK5394A AIN2.4Vpp VP=±15V Figure 5. Analog input buffer circuit example Fin 1Hz 10Hz Frequency Response -1.77dB -0.02dB Table 8. Frequency Response of HPF Fin 20kHz 40kHz 80kHz 6.144MHz Frequency Response 0.00dB 0.00dB 0.00dB -51.36dB Table 9. Frequency Response of LPF <KM064804> 2005/05 -7- ASAHI KASEI [AKD5394A] When capacitors more than 10µF are connected between VREF pin and GND The distortion at low frequency can be improved by connecting large capacitors C(Figure 6) to VREF pins. (Refer to Figure 7) C is C10, C13, C56 and C58 in circuit diagram. However, when the capacitors of VREF pins are larger than 10µF, it is possibility that the offset calibration does not performed correctly if the offset calibration cycle is started right after power-up. Because the internal VREF cannot settle to the appropriate voltage when the calibration cycle is completed. In this case, the offset calibration cycle should be started again after the VREF voltage settled. (Figure 8) The relationship between the capacitance and the VREF settling time is shown in Table 10. C C + + VREF+ AK5394A 0.22u VREF- Figure 6. VREF circuit example(C is C10, C13, C56 and C58 in circuit diagram) <KM064804> 2005/05 -8- ASAHI KASEI [AKD5394A] [Measurement Example] Ta=25°C; VA=5.0V; VD=3.3V; AGND, BGND, DGND=0V; fs=48kHz; 24 bit Output; BW=10Hz~20kHz; DFS0= “L”, DFS1= “L”, Using Audio Precision System Two. AK M A K5394A THD +N vs Frequency -60 -65 -70 -75 220µF -80 100µF -85 -90 d B F S -95 10µF -100 -105 -110 -115 -120 -125 1000µF -130 10 20 470µF 50 100 200 500 1k 2k 5k 10k 20k Hz la s t.at2 c Figure 7. THD+N vs. Frequency Capacitor C [µF] 1000 470 220 100 Settling Time T[s]=0.005 x C 5 2.4 1.1 0.5 Table 10. Capacitors connected between VREF and GND, and Settling Time Settling Time of VREF pin:T(s) 0.005 x C VA, VD 150ns~1ms tRTW tRTV RSTN tRCF CAL tRCR SDATA Figure 8. Reset & Calibration Timing <KM064804> 2005/05 -9- ASAHI KASEI [AKD5394A] MEASUREMENT RESULTS [Measurement condition] • Measurement unit : Audio Precision System Two Cascade(AP2C) / ROHDE & SCHWARZ, UPD04 (R&S) • MCLK : 12.288MHz • BICK : 128fs for 48kHz, 64fs for 96kHz and 192kHz • fs : 48kHz, 96kHz, 192kHz • BW : 10Hz∼20kHz (fs=48kHz) • Resolution : 24bit • Power Supply : VA=5V, VD=3.3V • Interface : DIT / Serial MUX : Room • Temperature 1. VREF cap = 10µF, Measurement Unit = AP2C ; I/F = Optical Parameter Input signal Measurement filter fs 48kHz BW 20kHz S/(N+D) 1kHz, -1dB 106.0 1kHz, -20dB 98.1 1kHz, -60dB 57.3 DR 1kHz, -60dB A-weighted 121.0 S/N no signal 118.7 A-weighted 121.1 Results 96kHz Fs/2 (=48kHz) 105.6 94.1 54.1 121.0 115.1 121.2 [dB] 2. VREF cap = 10µF, Meas. Unit = R&S ; I/F = Serial MUX Parameter Input signal Measurement filter Results fs 192kHz BW 80kHz S/(N+D) 1kHz, -1dB 105.1 1kHz, -20dB 91.0 1kHz, -60dB 54.1 DR 1kHz, -60dB A-weighted 119.0 S/N no signal 111.5 A-weighted 120.3 [dB] 3. Example measurement, VREF cap=1000µF, Meas. Unit = AP2C; I/F = Optical, Parameter Input signal Measurement filter Results fs 48kHz BW 20kHz S/(N+D) 1kHz, -1dB 111.1 DR 1kHz, -60dB A-weighted 121.6 S/N No signal A-weighted 121.4 [dB] <KM064804> 2005/05 - 10 - ASAHI KASEI [AKD5394A] Plots Measurement unit : Audio Precision, System two, Cascade (fs=48kHz,96kHz), ROHDE & SCHWARZ, UPD04 (fs=192kHz), VREF cap = 10µF 1. AP2C (FFT : BW=fs/2, point=16384) 1-1. fs=48kHz Figure 1-1-1. FFT (1kHz, –1dB input) Figure 1-1-2. FFT (1kHz, –60dB input) Figure 1-1-3. FFT (off the input) Figure 1-1-4. THD+N vs Input Frequency (-1dB input) Figure 1-1-5. THD+N vs Input Level (1kHz input) Figure 1-1-6. Linearity (fin=1kHz) Figure 1-1-7. Frequency Response (-1dB input) Figure 1-1-8. Cross-talk (-1dB input) 1-2. fs=96kHz Figure 1-2-1. FFT (1kHz, –1dB input) Figure 1-2-2. FFT (1kHz, –60dB input) Figure 1-2-3. FFT (off the input) Figure 1-2-4. THD+N vs Input Frequency (-1dB input) Figure 1-2-5. THD+N vs Input Level (1kHz input) Figure 1-2-6. Linearity (fin=1kHz) Figure 1-2-7. Frequency Response (-1dB input) Figure 1-2-8. Cross-talk (-1dB input) 2. R&S (FFT : BW=fs/2, point=8192) 2-1. fs=192kHz Figure 2-1-1. FFT (1kHz, –1dB input) Figure 2-1-2. FFT (1kHz, –60dB input) Figure 2-1-3. FFT (off the input) Figure 2-1-4. THD+N vs Input Frequency (-1dB input) Figure 2-1-5. THD+N vs Input Level (1kHz input) Figure 2-1-6. Linearity (fin=1kHz) Figure 2-1-7. Frequency Response (-1dB input) <KM064804> 2005/05 - 11 - ASAHI KASEI [AKD5394A] 1. AP2C 1-1. fs=48kHz AKM FFT plot(AK5394 Rev.B fs=48kHz, -1dB) +0 -10 -20 -30 -40 -50 -60 -70 d B F S -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 20 50 100 200 500 1k 2k 5k 10k 20k 5k 10k 20k Hz Figure 1-1-1. FFT (1kHz, –1dB input) AKM FFT plot(AK5394 Rev.B fs=48kHz, -60dB) +0 -10 -20 -30 -40 -50 -60 -70 d B F S -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 20 50 100 200 500 1k 2k Hz Figure 1-1-2. FFT (1kHz, –60dB input) <KM064804> 2005/05 - 12 - ASAHI KASEI [AKD5394A] AKM FFT plot(AK5394 Rev.B fs=48kHz) +0 -10 -20 -30 -40 -50 -60 -70 d B F S -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 20 50 100 200 500 1k 2k 5k 10k 20k 5k 10k 20k Hz Figure 1-1-3. FFT (off the input) AKM AK5394 R ev.B THD+N vs Frequency AV=5V, D V=3.3V +0 -10 -20 -30 -40 -50 -60 d B F S -70 -80 -90 -100 -110 -120 -130 -140 -150 20 50 100 200 500 1k 2k Hz Figure 1-1-4. THD+N vs Input Frequency (-1dB input) <KM064804> 2005/05 - 13 - ASAHI KASEI [AKD5394A] AKM AK5394 Rev.B THD +N vs Input Level AV=5V, D V=3.3V -90 -95 -100 -105 -110 -115 d B F S -120 -125 -130 -135 -140 -145 -150 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dB r Figure 1-1-5. THD+N vs Input Level (1kHz input) AKM AK5394 Rev.A Linearity AV=5V, DV=3.3V 02/23/01 15:08:56 +0 -10 -20 -30 -40 -50 -60 d B F S -70 -80 -90 -100 -110 -120 -130 -140 -150 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dB r Figure 1-1-6. Linearity (fin=1kHz) <KM064804> 2005/05 - 14 - ASAHI KASEI [AKD5394A] AKM AK5394 R ev.B Frequency Response AV=5V, D V=3.3V -0.9 -0.92 -0.94 -0.96 -0.98 d B F S -1 -1.02 -1.04 -1.06 -1.08 -1.1 20 50 100 200 500 1k 2k 5k 10k 20k 10k 20k Hz Figure 1-1-7. Frequency Response (-1dB input) AKM AK5394 Rev.A Crosstalk(Upper@ 20Hz: R -->Lch, Lower@20Hz:Lch-->Rch AV=5V, D V=3.3V -100 -105 -110 -115 -120 -125 -130 d B F S -135 -140 -145 -150 -155 -160 -165 -170 -175 -180 20 50 100 200 500 1k 2k 5k Hz Figure 1-1-8. Cross-talk (-1dB input) <KM064804> 2005/05 - 15 - ASAHI KASEI [AKD5394A] 1-2. fs=96kHz AKM FFT plot(AK5394 Rev.A fs=96kHz) +0 -20 -40 -60 d B F S -80 -100 -120 -140 -160 -180 20 50 100 200 500 1k 2k 5k 10k 20k 40k 5k 10k 20k 40k Hz Figure 1-2-1. FFT (1kHz, –1dB input) AKM FFT plot(AK5394 Rev.A fs=96kHz) +0 -20 -40 -60 d B F S -80 -100 -120 -140 -160 -180 20 50 100 200 500 1k 2k Hz Figure 1-2-2. FFT (1kHz, –60dB input) <KM064804> 2005/05 - 16 - ASAHI KASEI [AKD5394A] AKM FFT plot(AK5394 Rev.A fs=96kHz) +0 -20 -40 -60 d B F S -80 -100 -120 -140 -160 -180 20 50 100 200 500 1k 2k 5k 10k 20k 40k 5k 10k 20k 40k Hz Figure 1-2-3. FFT (1kHz, –60dB input) AKM AK5394 Rev.A THD +N vs Frequency, fs=96k AV=5V, D V=3.3V -60 -65 -70 -75 -80 -85 -90 d B F S -95 -100 -105 -110 -115 -120 -125 -130 20 50 100 200 500 1k 2k Hz Figure 1-2-4. FFT (off the input) <KM064804> 2005/05 - 17 - ASAHI KASEI [AKD5394A] AKM AK5394 Rev.B THD+N vs Input Level, fs=96k AV=5V, D V=3.3V -90 -95 -100 -105 -110 -115 d B F S -120 -125 -130 -135 -140 -145 -150 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dB r Figure 1-2-5. THD+N vs Input Level (1kHz input) AKM AK5394 Rev.B Linearity AV=5V, DV=3.3V 02/23/01 15:38:31 +0 -10 -20 -30 -40 -50 -60 d B F S -70 -80 -90 -100 -110 -120 -130 -140 -150 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dB r Figure 1-2-6. Linearity (fin=1kHz) <KM064804> 2005/05 - 18 - ASAHI KASEI [AKD5394A] AKM AK5394 Rev.B Frequency Response, fs=96k AV=5V, D V=3.3V -0.9 -0.92 -0.94 -0.96 -0.98 d B F S -1 -1.02 -1.04 -1.06 -1.08 -1.1 20 50 100 200 500 1k 2k 5k 10k 20k 40k 20k 40k Hz Figure 1-2-7. Frequency Response (-1dB input) AKM AK5394 Rev.B Crosstalk(Upper@ 100Hz: R -->Lch, Lower@100Hz:Lch-->Rch AV=5V, D V=3.3V -100 -105 -110 -115 -120 -125 -130 d B F S -135 -140 -145 -150 -155 -160 -165 -170 -175 -180 20 50 100 200 500 1k 2k 5k 10k Hz Figure 1-2-8. Cross-talk (-1dB input) <KM064804> 2005/05 - 19 - ASAHI KASEI [AKD5394A] 2-3. fs=192kHz Figure 2-1-1. FFT (1kHz, –1dB input) Figure 2-1-2. FFT (1kHz, –60dB input) <KM064804> 2005/05 - 20 - ASAHI KASEI [AKD5394A] Figure 2-1-3. FFT (off the input) Figure 2-1-4. THD+N vs Input Frequency (-1dB input) <KM064804> 2005/05 - 21 - ASAHI KASEI [AKD5394A] Figure 2-1-5. THD+N vs Input Level (1kHz input) Figure 2-1-6. Linearity (fin=1kHz) <KM064804> 2005/05 - 22 - ASAHI KASEI [AKD5394A] Figure 2-1-7. Frequency Response (-1dB input) <KM064804> 2005/05 - 23 - ASAHI KASEI [AKD5394A] Revision History Date (YY/MM/DD) Manual Revision Board Revision Reason 01/03/06 01/12/11 KM064800 KM064801 0 0 First edition 04/11/16 KM064802 1 Contents Device Name Change AK5394 ÆAK5394A Board Name Change AKD5394 ÆAKD5394A Unused input pins of CMOS-ICÆDGND U2(74HC14) : 11pinÆDGND 13pinÆDGND U13(74HCU04) : 11pinÆDGND 13pinÆDGND Analog input : Circuit Change AINL+ ÅÆ AINL(Exchange signal lines) AINR+ ÅÆ AINRError Correct Setting of jumper pin : Default setting : [JP1](5394_VA) : openÆshort [JP12](LRCK) : 96KÆ48K [JP16](XTE) : no descriptionÆopen Operation sequence : 1) Set up the power supply lines : Connector name : [4103]Æ[4103_VD] Jumper pin number : JP12(IF/5V)Æ JP15(IF/5V) Device name for DIT : AK4103ÆAK4103A Change figures and tables Evaluation mode : Setting of DIP switches Circuit Change (Additional description) 05/01/18 KM064803 2 Additional figure 05/05/19 KM064804 3 Analog input buffer circuit example Additional comment Setting of jumper pin Circuit Change (Resistance Value Change) Resistance: R27, R29: 4.7K Æ 10K <KM064804> 2005/05 - 24 - ASAHI KASEI [AKD5394A] IMPORTANT NOTICE • These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. • AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. • Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. • AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. • It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. <KM064804> 2005/05 - 25 - 3 2 5394_VD 1 5394_VA 5394_VA 5394_VD C7 C6 0.1u + 47u D C1 0.1u + C2 47u 5394_VA + 1 VL + VREFL+ VREFL- 3 VCOML AINL+ 4 AINL+ AINL- 5 AINL- ZCAL 6 ZCAL VREFR+ C56 10u 28 C55 0.22u C13 10u VREFR- 27 VCOMR 26 AINR+ 25 AINR+ AINR- 24 AINR- VA 23 + + 6 74HC14 0.22u C79 0.22u C 5 C14 0.1u 74HC14 C16 10u VL + C17 0.1u R1 10k 1 L D 0.1u U2C 9 H C5 0.1u + 2 1 C57 0.22u 2 C59 D1 1S2076A C4 1 IN 2 1 C10 10u C58 10u U2D C3 OUT U1 (short) 8 3 (short) L2 4103_RESETN NJM78M05FA 47u L1 C +15V T1 JP1 HIF3G-50P-2.54DSA (2x1) GND 4 2 5 U2A 2 74HC14 3 U2B R49 4 100 7 VD AGND 22 8 DGND BGND 21 9 CAL DFS1 20 DFS1 10 RSTN HPFE 19 HPFE 11 SMODE2 DFS0 18 + C15 10u 74HC14 C18 0.1u SW1 ATE1D-2M3-10 SMODE2 PDN SMODE1 R48 B 100 5394_LRCK R43 5394_SCLK 100 12 SMODE1 MCLK 17 13 LRCK FSYNC 16 14 SCLK SDATA 15 DFS0 R42 100 5394_MCLK R47 100 B 5394_FSYNC 5394_SDATA AK5394A 1 2 3 4 5 6 SW2 DSS106 5394_VD 12 11 10 9 8 7 AK5394_SW A RP1 M7-1-473 (47kx6) 6 5 4 3 2 1 11 DFS1 DFS0 HPFE SMODE2 SMODE1 ZCAL DFS1 DFS0 HPFE SMODE2 SMODE1 ZCAL U2E 10 A 74HC14 13 U2F 12 Title 74HC14 Size A3 Date: 5 4 3 2 AKD5394A Rev.B Document Number Rev AK5394A Thursday, May 19, 2005 Sheet 1 1 3 of 3 5 4 3 2 1 R22 620 C11 1n OP_AMPR11 3.3k 4 2 - 6 AINL- 3 JP3 HIF3G-50P-2.54DSA (2x1) BNC BiasL 10k R3 560 BiasL OP_AMP+ R21 620 C45 2.2n D 5394_VA R14 7 + U4 NJM5534D C19 68u + R12 91 D J1 XLIN Bal-(Low) 3 C75 + 10u 3 1 R16 0.1u 10k C20 (Open) 2 Bal+(High) 2 1 C21 1n C76 R17 4.7k GND OP_AMPJP4 HIF3G-50P-2.54DSA (2x1) BiasL + 2 3 6 R19 4.7k J2 BNC-R-PC LIN 7 BNC U5 NJM5534D OP_AMP+ 7 + U6 NJM5534D C22 68u + - 3 6 AINL+ R20 3.3k 4 4 OP_AMP- 2 - R23 91 OP_AMP+ C C R25 620 C12 1n OP_AMPR24 3.3k 4 2 + 3 U7 NJM5534D JP5 HIF3G-50P-2.54DSA (2x1) 5394_VA BNC BiasR OP_AMP+ R4 620 R27 R2 560 7 6 AINR- C23 68u + - R5 91 10k BiasR J3 XRIN C25 2.2n Bal-(Low) 3 3 2 C24 (Open) 2 Bal+(High) 1 C9 1n 1 B OP_AMP- 10k B JP6 HIF3G-50P-2.54DSA (2x1) BiasR 7 BNC U8 NJM5534D OP_AMP+ 2 3 6 R32 4.7k J4 BNC-R-PC RIN 7 C26 68u + + 3 R33 3.3k 4 4 2 + U9 NJM5534D R29 0.1u OP_AMP- - 6 AINR+ C77 R30 4.7k GND - R34 91 C78 + 10u OP_AMP+ -15V for NJM5534 2 OP_AMP+ C29 0.1u C30 10u C31 0.1u + C28 10u C32 10u C33 0.1u + + + C27 47u C60 10u C61 0.1u + L3 (short) C62 10u C63 0.1u + 1 C64 10u C65 0.1u A A +15V 1 C34 + 47u L4 for NJM5534 2 OP_AMP+ (short) + C35 10u C36 + 0.1u C37 10u C38 + 0.1u C39 10u C40 + 0.1u C66 10u C67 + 0.1u C68 10u C69 + 0.1u C70 10u C71 0.1u Title Size A3 Date: 5 4 3 2 AKD5394A Rev.B Document Number Analog Input Thursday, May 19, 2005 Sheet 1 2 Rev 3 of 3 5 4 3 2 1 TXP TX 4103_VD J5 BNC-R-PC T2 DA02 TXP 1 2 3 4 5 6 7 8 240 C41 0.1u 1k R36 R38 150 1:1 D SW3 DSS108 4103_VD DIF0 TXP C42 0.1u C43 10u 5394_SCLK R44 100 4103_MCLK 24.576M 5394_MCLK 4 11 3 U13B 74HCU04 U12 74HC4040 CLK Q1 Q2 RST Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 EXT_BICK JP11 HIF3G-50P-2.54DSA (3x2) BICK 9 7 6 5 3 2 4 13 12 14 15 1 HC74 12.288M 6.144M 3.072M SMODE1 JP12 HIF3G-50P-2.54DSA (3x2) LRCK D 3 CLK Q 5 Q 6 RP5 M6-1-473 (47kx5) 5 4 3 2 1 74HC74 2 X1 1 4103_VD BNC 4103_VD EXT_CLK 1M U13A 2 1 C53 74HCU04 5p R41 51 JP16 HIF3G-50P-2.54DSA (2x1) XTE C54 5p 1 2 R39 Xtal 5394_VD 3 24.576M JP2 HIF3G-50P-2.54DSA (3x1) CLK 10k 74HCU04 G DIR B 2 1 10 9 8 7 6 J6 BNC-R-PC A 5394_SCLK 5394_LRCK 5394_FSYNC 5 4 3 2 1 VL U15A 6 MCLK1 BICK 2 LRCk3 SDATA 4 FSYNC5 EXT U13E 11 10 19 1 18 17 16 15 14 13 12 11 PORT3 A1-10PA-2.54DSA VL R40 LRCK1 U13D 9 8 U11 74HC245 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 A8 B8 RP4 M6-1-473 (47kx5) R54 100 FSYNC 2 3 4 5 6 7 8 9 FSYNC 192k 96k 48k U13C 74HCU04 100 74HC74 74HCU04 B R53 EXT_LRCK JP13 HIF3G-50P-2.54DSA (3x1) 74HC4040 5 10 EXT_LRCK 8 C JP9 HIF3G-50P-2.54DSA (2x2) 5394_MCLK 5394_SDATA 100 Q 4103_MCLK 12.288M R52 9 4 100 EXT_BICK CLK HC4040 5394_LRCK R45 100 11 U15B Q JP7 HIF3G-50P-2.54DSA (2x2) 4103_MCLK 100 R51 D CKS1 CKS0 CLK R46 CKS0 CKS1 DIF0 12 4103_VD AK4103A C V1 FS0 FS1 FS2 FS3 CKS0 CKS1 DIF0 13 24 23 22 21 20 19 18 17 16 15 14 13 PR FS0 FS1 FS2 FS3 V1 U1 TRANS DIF2 RESETN DIF1 MCLK DIF0 SDTI TXP BICK TXN LRCK DVSS FS0/CSN DVDD FS1/CDTI CKS1 FS2/CCLK CKS0 FS3/CDTO BLS C1 ANS VL V1 FS0 FS1 FS2 FS3 CL 4103_RESETN R50 100 1 2 3 4 5 6 7 8 9 10 11 12 + U10 V1 D MODE RP2 M9-1-473 (47kx8) 1 2 3 4 5 6 7 8 9 4103_VD 16 15 14 13 12 11 10 9 10 R37 PR TX 4 3 2 1 CL PORT2 5 IN VCC IF 6 6 GND TOTX176 5 VL JP15 HIF3G-50P-2.54DSA (3x1) IF/5V for 74HC14,74HCU04, 74HC245,74HC74,74HC4040 4103_VD C73 0.1u + C44 47u C72 0.1u C74 0.1u C51 0.1u C8 0.1u C47 0.1u C81 10u + A U13F 13 12 Title 74HCU04 Size A3 Date: 5 4 3 2 AKD5394A Rev.B Document Number I/F and AK4103A Thursday, May 19, 2005 Sheet 1 3 of Rev 3 3