Data Sheet 26301.5F 8904 3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER WITH BACK-EMF SENSING A8904SLB (SOIC) Absolute Maximum Ratings Load Supply Voltage, VBB . . . . . . . . . . . . 15 V Output Current1, IOUT . . . . . . . . . . . . . . . . . . . . . ±1.4 A Peak Output Current (Brake)2, IOUT(BRK) . ±3.0 A Period2 for IOUT(BRK) to fall from ±3.0 A to ±1.4 A . . . . . . . . . . . . . . . 800 ms Logic Supply Voltage, VDD . . . . . . . . . . . 7.0 V Logic Input Voltage Range, VIN (continuous) . . . . . . -0.3 V to VDD + 0.3 V (tw <30 ns) . . . . . . . -1.0 V to VDD + 1.0 V Package Power Dissipation, PD . . See Graph Operating Temperature, TA . . . -20°C to +85°C Junction Temperature3, TJ . . . . . . . . . +150°C Storage Temperature,TS . . . . -55°C to +150°C 1Output current rating may be restricted to a value determined by system concerns and factors. These include: system duty cycle and timing, ambient temperature, and use of any heatsinking and/or forced cooling. For reliable operation, the specified maximum junction temperature should not be exceeded. 2Peak output current is a transient condition that occurs during braking when the motor acts as a generator. The 3 A level is based on the maximum peak of a sine wave that is damped. The maximum period between the initial brake being applied and the current through the drivers falling to 1.4 A should not exceed 800 ms. See Braking section for more information. 3Fault conditions that produce excessive junction temperature will activate device thermal shutdown circuitry. These conditions can be tolerated, but should be avoided. The A8904SLB and A8904SLP are three-phase brushless dc motor controller/drivers designed for applications where accurate control of highspeed motors is required. The three half-bridge outputs are low on-resistance n-channel DMOS devices capable of driving up to 1.2 A. The A8904 provides complete, reliable, self-contained back-EMF sensing, motor startup and running algorithms. A programmable digital frequency-locked loop speed control circuit together with the linear current control circuitry provides precise motor speed regulation. A serial port allows the user to program various features and modes of operation, such as the speed control parameters, startup current limit, sleep mode, direction, and diagnostic modes. The A8904 is fabricated in Allegro’s BCD (Bipolar CMOS DMOS) process, an advanced mixed-signal technology that combines bipolar, analog and digital CMOS, and DMOS power devices. The A8904SLB is provided in a 24-lead wide-body SOIC batwing package. The A8904SLP is provided in a thin (<1.2 mm), 28-lead TSSOP package with an exposed thermal pad. Each package type is available in a lead-free version (100% matte tin leadframe). Features Pin-for-pin replacement for A8902CLBA Startup commutation circuitry Sensorless commutation circuitry Option of external sector data tachometer signal Option of external speed control Oscillator operation up to 20 MHz Programmable overcurrent limit Transconductance gain options: 500 mA/V or 250 mA/V Programmable watchdog timer Directional control Serial Port Interface TTL-compatible inputs System diagnostics data out ported in real time Dynamic braking through serial port or external terminal Part Number A8904SLB-T A8904SLBTR-T A8904SLP-T A8904SLPTR-T Pb-free* Package Packing Yes Yes Yes Yes 24-pin SOIC 24-pin SOIC 28-pin TSSOP 28-pin TSSOP 31 per tube 450 per reel 50 per tube 4000 per reel *Pb-based variants are being phased out of the product line. The variants cited in this footnote are in production but have been determined to be LAST TIME BUY. This classification indicates that sale of this device is currently restricted to existing customer applications. The variants should not be purchased for new design applications because obsolescence in the near future is probable. Samples are no longer available. Status change: October 31, 2006. Deadline for receipt fo LAST TIME BUY orders: April 27, 2007. These variants include: A8904SLB, A8904SLBTR, A8904SLP, and A8904SLPTR. 8904 3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER Functional Block Diagram (A8904SLB terminal numbers shown) 2 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright © 2003 Allegro MicroSystems, Inc. 8904 3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER LB (SOIC) Package LP (TSSOP) Package A8904SLP (TSSOP) * Measured on “High-K” multi-layer PWB per JEDEC Standard JESD51-7. † Measured on typical two-sided PWB with power tabs (LB package) or thermal pad (LP package) connected to copper foil with an area of three square inches (1935 mm2). See Application Note 29501.5, Improving Batwing Power Dissipation, for additional information. www.allegromicro.com 3 8904 3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5.0 V Limits Characteristic Logic Supply Voltage Symbol VDD Logic Supply Current IDD Min. 4.5 Typ. 5.0 Max. 5.5 Units V Operating Sleep mode — — 7.5 250 10 500 mA µA Decreasing VDD Increasing VDD — — 3.6 3.9 — — V V Operating Operating 4.0 — — 4.0 14 8.0 V mA Sleep mode TJ — — 20 165 30 — µA °C Thermal Shutdown Hysteresis Output Drivers ∆TJ — 20 — °C Output Leakage Current IDSX VBB = 14 V, VOUT = 14 V, sleep mode VBB = 14 V, VOUT = 0 V — — 200 -2.0 300 -15 µA µA IOUT = 600 mA — 1.0 1.4 Ω VBB = 14 V, IOUT = IOUT(MAX), L = 3 mH IF = 1.0 A 14 — — 1.25 — 1.5 V V Undervoltage Threshold Load Supply Voltage Load Supply Current Thermal Shutdown Total Output ON Resistance (source + sink + RS) Output Sustaining Voltage Clamp Diode Forward Voltage UVLO VBB IBB rDS(on) VDS(sus) VF Test Conditions Operating Control Logic Logic Input Voltage VIN(0) SECTOR DATA, RESET, CLK, — — 0.8 V Logic Input Current VIN(1) IIN(0) CHIP SELECT, OSC VIN = 0 V 2.0 — — — — -0.5 V µA IIN(1) VBRK VIN = 5.0 V BRAKE Threshold — 1.5 — 1.75 ±1.0 2.0 µA V BRAKE Hysteresis Current BRAKE Current IBRKL IBRK VBRK = 750 mV Brake set, D2 = 1, IBRK = 750 mV — — 4.0 20 — — µA µA IOUT = 500 µA IOUT = -500 µA — 3.5 — — 1.5 — V V Charging Discharging, VCST = 2.5 V -9.0 — -10 500 -11 — µA µA DATA Output Voltage CST Current VOUT(0) VOUT(1) ICST CST Threshold VCSTH VCSTL High Low 2.25 0.85 2.5 1.0 2.75 1.15 V V Filter Current IFILTER Charging Discharging -9.0 9.0 -10 10 -11 11 µA µA Leakage, VFILTER = 2.5 V — 1.57 — 1.85 ±5.0 2.13 nA V Charging Discharging -18 32 -20 40 -22 48 µA µA ICD(DISCHRG)/ICD(CHRG) 1.8 2.25 2.0 2.5 2.2 2.75 — V — — 1.0 µA Filter Threshold CD Current (CD1 or CD2) CD Current Matching CD Threshold CD Input Leakage VFILTERTH ICD — VCDTH ICDIL Continued next page … 4 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 8904 3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER ELECTRICAL CHARACTERISTICS continued Limits Characteristic CWD Current Symbol ICWD Test Conditions Charging, D26 = 0, D27 = 0 Min. -9.0 Typ. -10 Max. -11 Units µA Charging, D26 = 0, D27 =1 Charging, D26 = 1 D27 = 0 -18 -27 -20 -30 -22 -33 µA µA Charging, D26 = 1, D27 =1 -40 0.25 -44 0.28 µA V CWD Threshold Voltage VTL -36 0.22 Max. FLL Oscillator Frequency VTH fOSC 2.25 20* 2.5 — 2.75 — V MHz Oscillator High Duration Oscillator Low Duration ton toff 20 20 — — — — ns ns Maximum Output Current IOUT(MAX) D3 = 0, D4 = 0, D28 = 0 D3 = 0, D4 = 1, D28 = 0 1.0 0.9 1.2 1.0 1.4 1.1 A A D3 = 1, D4 = 0, D28 = 0 D3 = 1, D4 = 1, D28 = 0 500 — 600 250 700 — mA mA D3 = 0, D4 = 0, D28 = 1 D3 = 0, D4 = 1, D28 = 1 500 415 600 500 700 585 mA mA D3 = 1, D4 = 0, D28 = 1 D3 = 1, D4 = 1, D28 = 1 — — 300 125 — — mA mA 210 420 250 500 290 580 mA/V mA/V 5.0 5.0 10 20 13 37 kΩ mV -5.0 -20 -37 mV Transconductance Gain gm Centertap Resistors Back-EMF Threshold with respect to VCTAP at FCOM transition RCT — D28 = 1 D28 = 0 Negative current is defined as coming out of (sourcing) the specified device terminal. * Operation at an oscillator frequency greater than the specified minimum value is possible but not waranteed. www.allegromicro.com 5 8904 3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER Serial Port Timing Conditions CHIP SELECT E A B CLOCK C D C D DATA Dwg. WP A. Minimum CHIP SELECT setup time before CLOCK rising edge ......... 100 ns B. Minimum CHIP SELECT hold time after CLOCK rising edge .............. 150 ns C. Minimum DATA setup time before CLOCK rising edge ....................... 150 ns D. Minimum DATA hold time after CLOCK rising edge ............................ 150 ns E. Minimum CLOCK low time before CHIP SELECT .................................. 50 ns F. Maximum CLOCK frequency .............................................................. 3.3 MHz G. Minimum CHIP SELECT high time ...................................................... 500 ns Note: the A8904 can be directly used in an existing A8902–A application, as the five most significant bits are reset to zero, which is the default condition for A8902–A operation. The only consideration when using the A8904 in an A8902-A application, is to ensure the minimum CHIP SELECT high time is at least 500 ns. 6 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 8904 3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER Terminal Functions Terminal Name Function LOAD SUPPLY A8904SLB (SOIC) A8904SLP (TSSOP) VBB; the 5 V or 12 V motor supply. 1 15 CD2 One of two capacitors used to generate the ideal commutation points from the back-EMF zero crossing points. 2 16 CWD Timing capacitor used by the watchdog circuit to blank out the back-EMF comparators during commutation transients, and to detect incorrect motor position. 3 17 CST Startup oscillator timing capacitor. 4 18 NC No( internal) connection. – 19 OUTA NC GROUND POWER GROUND NC Power amplifier A output to motor. 5 20 No (internal) connection. – 21 6-7 – Power ground. Power and logic ground and thermal heat sink. – 22* No (internal) connection. – 23 OUTB Power amplifier B output to motor. 8 24 OUTC Power amplifier C output to motor. 9 25 Motor centertap connection for back-EMF detection circuitry. 10 26 Active low turns ON all three sink drivers shorting the motor windings to ground. External capacitor and resistor at BRAKE provide brake delay. The brake function can also be controlled via the serial port. 11 27 External reservoir capacitor used to hold charge to drive the source drivers’ gates. Also provides power for brake circuit. 12 28 Analog ground. – 1* Analog voltage input/output to control motor current. Also, compensation node for internal speed control loop. CENTERTAP BRAKE CRES ANALOG GROUND FILTER 13 2 SECTOR DATA External tachometer input. Can use sector or index pulses from disk to provide precise motor speed feedback to internal frequency-locked loop. 14 3 LOGIC SUPPLY VDD; the 5 V logic supply. 15 4 OSCILLATOR DATA OUT NC GROUND DIGITAL GROUND RESET NC CHIP SELECT CLOCK DATA IN CD1 Clock input for the speed reference counter. 16 5 Thermal shutdown indicator, FCOM, TACH, or SYNC signals available in real time, controlled by 2-bit multiplexer via serial port. 17 6 No (internal) connection. – 7 18-19 – Logic ground. – 8* When pulled low forces the chip into sleep mode; clears all serial port bits. 20 9 Power and logic ground and thermal heat sink. No (internal) connection. – 10 Strobe input (active low) for data word. 21 11 Clock input for serial port. 22 12 Sequential data input for the serial port. 23 13 One of two capacitors used to generate the ideal commutation points from the back-EMF zero crossing points. 24 14 * For the A8904SLP, ground terminals 1, 8, and 22 must be connected together externally. www.allegromicro.com 7 8904 3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER Functional Description Overview of operation. Each electrical revolution contains six states that control the three half-bridge outputs. Optimized switching from state to state is achieved through the adaptive commutation circuitry. During any state, one output is high, one is low and the other is high impedance. The backEMF at the high-impedance output is sensed and compared to the voltage of the centertap and when the two signals are equivalent, the FCOM signal toggles. A controlled delay is then introduced before the sequencer commutates into the next state. Linear current-mode control is employed to provide precision control of the motor speed while maintaining extremely low electrical noise emissions. The speed control is realized through a frequency-locked loop that processes the sensed back-EMF signals from the stator phases to eventually produce a TACH signal. The TACH signal is then compared to the desired programmed speed, to produce an error. The error signal is then used to linearly control the current through the low-side DMOS power devices to obtain the correct speed. Alternative control schemes can be introduced, giving the user maximum flexibility and optimization for each application. An external tachometer signal applied to the SECTOR DATA input, along with the internal speed reference can be used for high-precision speed control. As another alternative, the user can introduce external speed control by driving the FILTER terminal directly. Start-up routines are inherent in the solution to guarantee reliable start-up. During start-up, a YANK feature allows rapid transition to the nominal operating condition on the FILTER terminal. This feature is also available when the external speed control is used. Dynamic braking can be introduced by either the external BRAKE terminal or through the brake bit in the serial port. A serial port allows the user to program various features and modes of operation, such as motor speed, internal or external speed control, internal or external speed reference, current limit, sleep mode, direction, charge current (for blanking pulse), motor poles, transconductance gain, and various diagnostic outputs. Full device protection is incorporated, including programmable overcurrent limit, thermal shutdown, and undervoltage shutdown on the logic supply. Power outputs. The power outputs of the A8904 are nchannel DMOS transistors with a total source plus sink rDS(on) of typically 1 Ω. An internal charge pump provides a voltage rail above the load supply for driving the high-side DMOS gates. Intrinsic ground clamp and flyback diodes provide protection when switching inductive loads. These diodes will also rectify the motor back-EMF during power-down conditions. If neces- 8 sary, a transient voltage supply can be provided, by connecting an external Schottky power diode or pass FET in series, between the power source and the load supply (VBB). This FET or diode effectively isolates the low impedance path through the power source. A filter capacitor is also required to ‘hold up’ the rectified signal, and is connected between the load supply and ground. Back-EMF sensing motor startup and running algorithm. The A8904 provides a complete self-contained back-EMF sensing, startup and running commutation scheme. A state machine with six states, (shown in the tables below for both forward and reverse direction) controls the three halfbridge outputs. In each state, one output is high (sourcing current), one low (sinking current), and one is OFF (high impedance or ‘Z’). Motor back-EMF is sensed at the output that is OFF. Sequencer State (forward direction) OUTA OUTB OUTC 1 High Z Low 2 High Low Z 3 Z Low High 4 Low Z High 5 Low High Z 6 Z High Low Sequencer State (reverse direction) 1 6 5 4 3 2 OUTA High Z Low Low Z High OUTB Z High High Z Low Low OUTC Low Low Z High High Z At start-up, the outputs are always enabled in state 1. The back-EMF is examined at the OFF output by comparing the output voltage to the motor centertap voltage at CENTERTAP. The motor will then either step forward, step backward or remain stationary (if in a null-torque position). If the motor does not move during the initial start-up state, the outputs are commutated automatically by the start-up oscillator. When suitable back-EMF signals are detected, the start-up oscillator is overridden and the corresponding timing clock is generated, providing synchronous back-EMF commutation. The start-up oscillator period is determined by tCST = (VCSTH - VCSTL) x CST / IST(charge) where CST is the start-up capacitor. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 8904 3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER Functional Description (cont’d) If the motor moves, the back-EMF detection and direction circuit waits for the correct polarity of back-EMF zero crossing (output crossing through centertap). If the correct polarity of back-EMF is not detected, a watchdog circuit commutates the output until the correct back-EMF is detected. Correct backEMF sensing is indicated by the FCOM signal, which toggles every time the back-EMF completes a zero crossing (see waveforms below). FCOM is available at the DATA OUT terminal. The typical delta voltage change during normal operation in the commutation capacitors (CD1 & CD2), will range between 1.5 V and 2.0 V. The commutation capacitor values can be determined from: CDX = ICD x t / VCD True back-EMF zero crossings are used by the adaptive commutation delay circuit to advance the state sequencer (commutate) at the proper time to synchronously run the motor. See next section. Adaptive commutation delay. The adaptive commutation delay circuit uses the back-EMF zero-crossing indicator signal (FCOM) to determine an optimal commutation time for efficient synchronous switching of the output drivers. When the FCOM signal changes state, one of the delay capacitors (CD1 or CD2) is discharged at approximately twice the rate of the charging current. When the capacitor reaches the 2.5 V threshold, a commutation occurs. During this discharge period, the other delay capacitor is being charged in anticipation of the next FCOM state change. In addition, there is an interruption to the charging, which is set by the blanking duration (see waveform below, VCWD, and next section). This additional charging delay causes the commutation to occur at slightly less than 50% of the FCOM on or off duration, to compensate for delays caused by winding inductance. www.allegromicro.com where VCD = 1.5 V, ICD = 20 µA, and t = (60/rpm)/(#motor poles x 3), duration of each state. To avoid the capacitors charging to the supply rail, the value selected should provide adequate margin, taking into account the effects of capacitor tolerance, charging current, etc. Blanking and watchdog timing functions. The blanking and watchdog timing functions are derived from one timing capacitor CWD . During normal commutation, at the beginning of each new sequencer state, a blanking signal is created until the watchdog capacitor CWD is charged to the threshold VTL (see waveforms below). This blanking signal prohibits the back-EMF comparators from tripping due to the discharging of inductive energy and voltage settling transients during sequence state transitions. The duration of this blanking signal depends on the size of the CWD capacitor and the programmed charge current, ICWD (via D2627). This blanking pulse also interrupts the commutation delay capacitors CD1 and CD2 from charging (see previous section). The ability to select the minimum charge current for CWD is particularly useful during start-up, where the duration of the diode recirculation current is highest. In applications where high motor speeds are experienced, the charge current can be increased so that the blanking period does not encroach significantly into the period of each sequencer state and does not cause 9 8904 3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER Functional Description (cont’d) unbalance in the commutation points. It is recommended to select the value of CWD in the actual application circuit with the A8904 put into step mode. CST should be reselected (only for this test), to be between 4.7 µF and 10 µF, so that the motor comes to rest between steps and the maximum diode conduction time can be measured. The value of CWD can be determined as: CWD = ICWD x td / VTL where td = measured diode conduction, ICWD = charge current at start-up, and VTL = 250 mV. V TL V CWD t BLANK BLANK Dwg. W P-022 Normal commutation V TH V TL V CWD t BLANK BLANK t WD Dwg. W P-021 Watchdog-triggered commutation After the watchdog capacitor CWD charges to the VTL threshold, and if the correct polarity of back-EMF signal is detected, the back-EMF detection circuit discharges CWD to zero volts (see waveform above) and the circuit is ready to detect the next backEMF zero crossing. If the correct polarity of back-EMF is not detected between the blanking period, tBLANK, and the watchdog period, tWD, then the back-EMF detection circuit does not allow the watchdog capacitor CWD to be discharged and the watchdog circuit commutates the outputs to the next sequencer state (see waveform above). This mode of operation continues until a suitable back-EMF signal is detected. This function is useful in preventing excessive reverse rotation, and helps in resynchronising (or starting) with a moving spindle. 10 The duration of the watchdog-triggered commutation is determined by: tWD = VTH x CWD / ICWD where ICWD = normal charge current. Speed control. The actual speed of the motor is measured by either internally sensing the back-EMFs or by an external scheme via the SECTOR DATA terminal. A TACH signal is produced from these signals, which is then compared against the desired speed, which is programmed into a 14-bit counter (see diagram and waveforms below - assumes internal scheme used). The resulting error signal, ERROR, is then used to charge or discharge the FILTER terminal capacitor depending on whether the motor is running too slow or too fast. The FILTER terminal voltage is used to linearly drive the low-side MOSFETs to match the desired speed. Each back-EMF signal detected causes the state of the FCOM signal to change. The number of FCOM transitions per mechanical revolution is equal to the number of poles times 3. For example, with a 4-pole motor (as shown on next page), the number of FCOM transitions will equal 12 per mechanical revolution. The number of poles are programmed via serial port bits D20 and D21. There are six electrical states per electrical revolution, therefore, for this example, there are 12 commutations or two electrical revolutions per mechanical revolution. The TACH signal changes state once per mechanical revolution and as well as providing information on the actual motor speed is also used to trigger the REF counter which contains the information on the desired motor speed. Alternatively an external TACH signal can be used, an explanation of which is presented in the Sector Mode Section. The duration of REF is set by programming the counter to count the desired number of OSCILLATOR cycles, according to the following: total count = 60 x fOSC / desired motor speed (rpm) where the total count (number of oscillator cycles) is equal to the sum of the count numbers selected through bits D5 to D18 in the serial port and fOSC corresponds to the OSCILLATOR frequency. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 8904 3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER Functional Description (cont’d) Speed error detection Speed error signals A speed error signal is created by integrating the differences between the TACH and REF signal. If the TACH signal goes low before the REF signal then an ERROR FAST is produced and if the TACH signal goes low after the REF signal then an ERROR SLOW is produced. The error signal generated enables the appropriate current source (see diagram next page) to either charge or discharge the filter components on the FILTER terminal. www.allegromicro.com The FILTER voltage is then used to provide linear current control in the windings via the transconductance stage (see diagram next page). The output current is sensed through an internal sense resistor, RS. The voltage across the sense resistor is compared to the lowest of either one-tenth of the voltage at the FILTER terminal, minus the filter threshold voltage, or to the maximum current limit reference. Alternatively, external control of the FILTER terminal can be introduced by disabling the frequency-lock loop circuitry (D24 = 1). The transconductance function is defined as: IOUT = (VFILTER – VFILTERTH) / (10 x RS x G) where RS is nominally 200 mΩ, VFILTERTH is approximately 1.85 V, G = 1, when D28 = 0 and gain = 500 mA/V or G = 2, when D28 = 1 and gain = 250 mA/V. The closed loop control response of the overall system is shaped via the filter components that are introduced at the FILTER terminal. Clamping the current to a level defined by the serial port (D3 & D4) provides output current limit protection. This feature is particularly useful where high transient currents are experienced, e.g., during start-up. Once normal running conditions are reached, the current limit can be appropriately reduced. Note that the current limit is scaled according to the gm value selected. 11 8904 3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER Functional Description (cont’d) Speed and current control Sector mode. An external tachometer signal, such as sector or index pulses, can be used to create the TACH signal, rather than the internally generated once-around scheme. The external signal is applied to the SECTOR DATA terminal and the serial port bit (D19 = 1) must be programmed to enable this feature. In applications where both internal and external TACH signals are used, it is important to only switch between modes when the SYNC signal on DATA OUT is low. This ensures the speed control information that is being processed during the transition, is not corrupted. SYNC is accessed through the DATA OUT multiplexer, which is controlled by D22 & D23. DATA OUT. The DATA OUT terminal is the output of a 2-bit input multiplexer controlled by D22 & D23 of the serial port. Data available are TACH signal (internally or externally generated), SYNC signal, FCOM signal, and thermal shutdown (LOW = A8904 operating within thermal limits, HIGH = thermal shutdown has occurred). Speed loop initialization (YANK). To ensure rapid transition from start-up to the normal operating condition, the FILTER terminal is pulled up to the filter threshold voltage, 12 VFILTERTH, by the internal YANK command and the initial output current will be set to the maximum selected current limit. This condition is maintained until the motor reaches the correct speed and the first ERROR FAST signal is produced which removes the YANK and allows linear current control. The YANK feature is also activated when an external speed control scheme is used (D24 = 1). To ensure the YANK is released at start-up by the internal speed control, it is important to ensure the speed reference is set at a lower speed than what the motor is designed to run at. Note that when the serial port is programmed to run initially, the default condition for the speed is set for the slowest condition so this will guarantee the YANK to be released. It is important when using external speed control that, as a minimum, the number of poles, speed control mode, and speed reference are programmed in the serial port. Forward/reverse. Directional control is managed through D25 in the serial port. Serial port. Control features and diagnostic data selection are communicated to the A8904 through the 29-bit serial port. See serial port timing diagrams on page 6. When CHIP SELECT is low, data is written to the serial port on the positive edge of the clock with the MSB (D28) fed in first. At the end of 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 8904 3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER Functional Description (cont’d) the write cycle, the CHIP SELECT goes high, the serial port is disabled and no more data can be transferred. In addition, the data written to the serial port is latched and becomes active. If a word of less than 29 bits is sent, the unused most significant bits that are not programmed, are reset to zero. There are no compatibility issues when using the A8904 in an existing A8902-A application as the five MSBs are reset to zero, which is the default condition for A8902-A operation. The only consideration when using the A8904 in an A8902-A application is to ensure the minimum CHIP SELECT high time is at least 500 ns. D0 - Sleep/Run Mode; LOW = Sleep, HIGH = Run. This bit allows the device to be powered down when not in use. D1 - Step Mode; LOW = Normal Operation, HIGH = Step Only. When in the step-only mode the back-EMF commutation circuitry is disabled and the start-up oscillator commutates the power outputs. This mode is intended for device and system testing. D2 - Brake; LOW = Run, HIGH = Brake. D3, D4, and D28 - The output current limit is set by D3 & D4; D28 sets the transconductance gain. Current limit Transconductance D3 D4 D28 (typical) gain 0 0 0 1.2 A 500 mA/V 0 1 0 1.0 A 500 mA/V 1 0 0 600 mA 500 mA/V 1 1 0 250 mA 500 mA/V 0 0 1 600 mA 250 mA/V 0 1 1 500 mA 250 mA/V 1 0 1 300 mA 250 mA/V 1 1 1 125 mA 250 mA/V D5 to D18 - 14-bit word, active low. Programs the count number to produce the corresponding REF signal, which indicates the desired motor speed. Bit number Count number D5 16 D6 32 D7 64 D8 128 D9 256 D10 512 D11 1,024 D12 2,048 D13 4,096 D14 8,192 D15 16,384 D16 32,768 D17 65,536 D18 131,072 D19 - Speed control mode; LOW = internal, once-around speed signal, HIGH = external sector data. D20 and D21 - Programs the number of motor poles for the once-around FCOM counter. D20 D21 Motor poles 0 0 8 0 1 4 1 0 16 1 1 12 D22 and D23 - Controls the multiplexer for DATA OUT. See DATA OUT Section for status definitions. D22 D23 DATA OUT 0 0 TACH (once around or sector) signal 0 1 Thermal shutdown 1 0 SYNC signal 1 1 FCOM signal D24 - Speed Reference. LOW = Internal, using back-EMF technique, HIGH = External (internal control disabled). D25 - Direction. LOW = Forward, HIGH = Reverse. D26 and D27 - Programs the charging current for the watchdog capacitor. This function is used for adjusting the blanking duration and also the watchdog commutation period. D26 0 0 1 1 www.allegromicro.com D27 0 1 0 1 Watchdog charge current (typical) -10 µA -20 µA -30 µA -40 µA 13 8904 3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER Functional Description (cont’d) D28 - Programs the transconductance gain. LOW = 500 mA/V, HIGH = 250 mA/V. Reset. When the RESET terminal is pulled low, all the serial port bits are reset to LOW and the part operates in sleep mode. Undervoltage lockout, VDD. When an undervoltage condition occurs, all the serial port bits are reset to LOW and the part operates in sleep mode. Charge pump. The charge pump is required to provide a voltage rail above the load supply for driving the high-side DMOS gates. In addition the charge pump supply capacitor, CRES, also powers the brake control circuit during power-down conditions. CRES should be 220 nF. Braking. A dynamic braking feature of the A8904 shorts the three motor windings to ground. This is accomplished by turning the three source drivers OFF and the three sink drivers ON. Activation of the brake can be implemented through the BRAKE input or through the D2 bit in the serial port. During braking, the motor is effectively acting as three sinewave voltage generators, 120° out of phase, where the voltage developed by each of the windings is proportional to the motor speed and constant. The current through any sink driver is simply the generated voltage divided by the center tap to OUT resistance plus the sink driver resistance. As the motor tends to slow during the braking process, both the generated voltage and the corresponding current decreases. When selecting a motor to use where braking will be applied, it is important to characterize the application to ensure that when braking is applied, the peak current in the sink drivers does not exceed 3A and the period from the peak current to the maximum current limit of the drivers does not exceed 800 ms. Another consideration is the thermals of the solution, where repeated spin-up followed by brake cycles could cause excessive junction temperatures. The supply voltage for the brake circuit is derived from the charge pump supply capacitor, CRES. With CRES chosen to be 220 nF, the brake circuit will function for at least 100 ms after a power failure. In certain applications such as disk drives, it is desirable to include a brake delay to allow sensitive circuitry such as the disk 14 head to retract before activating the spindle motor brake. The brake delay can be simply implemented by using an external RC and diode to control the brake terminal. BRAKE FAULT V FAULT – V D BRAKE ACTIVATED CB R V B t BRK BRK Dwg. OP-004 The brake delay can be set using the equation: tBRK = –RBCB x ln (VBRK / [VFAULT – VD]). Once the brake is activated, the three sink drivers will remain active until the supply rails fall below the operating range. It is recommended that the part is reset before restarting. Centertap. It is recommended that the centertap connection of the motor be connected to the CENTERTAP terminal. If the centertap of the motor is not connected to the CENTERTAP terminal, the A8904 internally emulates the centertap voltage of the motor through a series of 10 kΩ resistors connected between each output and CENTERTAP. This technique does not provide ideal commutation points. External component selection. All capacitors should be rated to at least 25 V and the dielectric should be X7R, apart from the start-up capacitor CST, which can be Z5U dielectric or equivalent and the input capacitor Cfilter, which should be an electrolytic type of value greater than 100 µF, 35 V, Iripple > 100 mA. If the solution experiences ambient temperatures of greater than 70°C then Cfilter should be rated for 105°C. All resistors are at least 1/8 W and have a tolerance of ±5%. In noise-sensitive systems where electromagnetic interference is an issue, or to stabilize the current waveforms with certain motors, it may be necessary to add RC snubbers across the motor windings as shown in the application circuit on the next page. The A8904 solution should be relatively noise immune from the effects of switching voltage spikes etc. if the correct watchdog capacitor has been selected for optimum blanking and good layout practices are implemented. At the range of operating frequencies that the current pulses are drawn out of the load supply, it is the capacitance reactance 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 8904 3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER as opposed to the ESR that dominates the overall impedance of the input filter, Cfilter. Therefore, it is possible to reduce conducted electromagnetic emissions further, by simply increasing the value of Cfilter. In extremely sensitive systems, it may be necessary to introduce a differential mode inductor in series with the load supply line. Layout considerations. The TSSOP part (A8904SLP) has three separate ground connections, analog, digital, and power that must be connected together externally. A ground plane should be used to provide heat sinking for the power switches and the reduction of potential noise pick-up through inductive loops and radiated emissions. The ground plane should cover the area beneath the A8904 and extend beyond the outline to form a plane around all the external components. The exposed thermal pad of the TSSOP part should be connected to the ground plane. Filter components, especially Cfilter, timing, and delay capacitors should be positioned as close as possible to the device terminals. It is also imperative that the traces to the serial port and oscillator are as short and as wide as possible to reduce stray inductance and prevent potential data corruption. In addition, these traces should be positioned well away from any noisy signals. Typical application (A8904SLB) www.allegromicro.com 15 8904 3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER A8904SLB (SOIC) 24 13 0.012 0.009 0.419 0.394 0.2992 0.2914 0.050 0.016 0.020 0.013 1 2 3 0.6141 0.5985 0.050 0° TO 8° BSC Dimensions in Inches (for reference only) NOTE 1 NOTE 3 0.0926 0.1043 0.0040 Dwg. MA-008-25A in MIN. 24 0.32 0.23 10.65 10.00 7.60 7.40 1.27 0.40 0.51 0.33 1 2 1.27 3 15.60 15.20 0° BSC TO 8° NOTE 1 NOTE 3 Dimensions in Millimeters (controlling dimensions) 2.65 2.35 0.10 MIN. Dwg. MA-008-25A mm NOTES: 1. 2. 3. 4. 16 Webbed lead frame. Leads 6, 7, 18, and 19 are internally one piece. Lead spacing tolerance is non-cumulative. Exact body and lead configuration at vendor’s option within limits shown. Supplied in standard sticks/tubes of 31 devices or add “TR” to part number for tape and reel. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 8904 3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER A8904SLP (TSSOP) Dimensions in Inches (for reference only) Dimensions in Millimeters (controlling dimensions) NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Supplied in standard sticks/tubes of 49 devices or add “TR” to part number for tape and reel. www.allegromicro.com 17 8904 3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. 18 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000