Si6924AEDQ Vishay Siliconix N-Channel 2.5-V (G-S) Battery Switch, ESD Protection FEATURES PRODUCT SUMMARY VDS (V) 28 RDS(on) (Ω) ID (A) 0.033 at VGS = 4.5 V 4.6 0.038 at VGS = 3.0 V 4.3 0.042 at VGS = 2.5 V 4.1 • • • • • • Halogen-free Low RDS(on) VGS Max Rating: 14 V Exceeds 2 kV ESD Protection 28 V VDS Rated Symmetrical Voltage Blocking (Off Voltage) RoHS COMPLIANT DESCRIPTION The Si6924AEDQ is a dual N-Channel MOSFET with ESD protection and gate over-voltage protection circuitry incorporated into the MOSFET. The device is designed for use in Lithium Ion battery pack circuits. The common-drain construction takes advantage of the typical battery pack topology, allowing a further reduction of the device’s onresistance. The 2-stage input protection circuit is a unique design, consisting of two stages of back-to-back zener diodes separated by a resistor. The first stage diode is designed to absorb most of the ESD energy. The second stage diode is designed to protect the gate from any remaining ESD energy and over-voltages above the gates inherent safe operating range. The series resistor used to limit the current through the second stage diode during over voltage conditions has a maximum value which limits the input current to ≤ 10 mA at 14 V and the maximum toff to 12 µs. The Si6924AEDQ has been optimized as a battery or load switch in Lithium Ion applications with the advantage of both a 2.5 V RDS(on) rating and a safe 14 V gate-to-source maximum rating. APPLICATION CIRCUITS ESD and Overvoltage Protection D ESD and Overvoltage Protection R** G S Battery Protection Circuit *Thermal connection to drain pins is required to achieve specific performance Figure 1. Typical Use In a Lithium Ion Battery Pack Document Number: 72215 S-81056-Rev. B, 12-May-08 **R typical value is 3.3 kΩ by design. See Typical Characteristics, Gate-Current vs. Gate-Source Voltage, Page 3. Figure 2. Input ESD and Overvoltage Protection Circuit www.vishay.com 1 Si6924AEDQ Vishay Siliconix FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION *D *D 3.3 kΩ TSSOP-8 3.3 kΩ G1 D 1 S1 2 S1 3 G1 4 Si6924AEDQ G2 8 D 7 S2 6 S2 5 G2 S1 S2 N-Channel Top View Ordering Information: Si6924AEDQ-T1-GE3 (Lead (Pb)-free and Halogen-free) N-Channel *Thermal connection to drain pins is required to achieve specific performance. Figure 3. Figure 4. ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted Parameter Symbol 10 s Steady State Drain-Source Voltage, Source-Drain Voltage VDS 28 Gate-Source Voltage VGS ± 14 Continuous Drain-to-Source Current (TJ = 150 °C)a TA = 25 °C TA = 70 °C Pulsed Source Current (Diode Conduction)a IS TA = 25 °C TA = 70 °C PD 4.6 4.1 3.2 20 1.2 A 0.9 1.3 1.0 0.84 0.64 TJ, Tstg Operating Junction and Storage Temperature Range V 3.7 IDM Pulsed Drain-to-Source Current Maximum Power Dissipationa ID Unit - 55 to 150 W °C THERMAL RESISTANCE RATINGS Parameter Maximum Junction-to-Ambienta Maximum Junction-to-Foot (Drain) Symbol t ≤ 10 s Steady State Steady State RthJA RthJF Typical Maximum 71 95 96 125 56 70 Unit °C/W Notes: a. Surface Mounted on FR4 board. www.vishay.com 2 Document Number: 72215 S-81056-Rev. B, 12-May-08 Si6924AEDQ Vishay Siliconix SPECIFICATIONS TJ = 25 °C, unless otherwise noted Parameter Symbol Test Conditions Min. VGS(th) VDS = VGS, ID = 250 µA 0.6 Typ. Max. Unit 1.5 V Static Gate Threshold Voltage VDS = 0 V, VGS = ± 4.5 V ±1 µA VDS = 0 V, VGS = ± 14 V ± 20 mA Gate-Body Leakage IGSS Zero Gate Voltage Drain Current IDSS On-State Drain Currentb ID(on) VDS ≥ 5 V, VGS = 5 V VGS = 4.5 V, ID = 4.6 A 0.022 0.033 RDS(on) VGS = 3.0 V, ID = 4.3 A 0.025 0.038 VGS = 2.5 V, ID = 4.1 A 0.029 0.042 gfs VDS = 10 V, ID = 4.6 A 25 VSD IS = 1.2 A, VGS = 0 V 0.7 1.1 6.5 10 Drain-Source On-State Resistanceb Forward Transconductanceb Diode Forward Voltage b VDS = 22.4 V, VGS = 0 V 1 VDS = 22.4 V, VGS = 0 V, TJ = 55 °C 5 µA 10 A Ω S V Dynamica Qg Total Gate Charge Gate-Source Charge Qgs Gate-Drain Charge Qgd Turn-On Delay Time td(on) VDS = 10 V, VGS = 4.5 V, ID = 4.6 A VDD = 10 V, RL = 10 Ω ID ≅ 1 A, VGEN = 4.5 V, RG = 6 Ω tr Rise Time td(off) Turn-Off Delay Time tf Fall Time nC 1.2 1.5 0.95 1.5 1.4 2.1 7 11 3.1 5 µs Notes: a. Guaranteed by design, not subject to production testing. b. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 0.020 10,000 0.015 I GSS - Gate Current (A) I GSS - Gate Current (mA) 1,000 0.010 0.005 100 TJ = 150 °C 10 1 0.1 TJ = 25 °C 0.01 0.001 0.000 0 3 6 9 12 VGS - Gate-to-Source Voltage (V) Gate-Current vs. Gate-Source Voltage Document Number: 72215 S-81056-Rev. B, 12-May-08 15 0 2 4 6 8 10 12 14 VGS - Gate-to-Source Voltage (V) Gate Current vs. Gate-Source Voltage www.vishay.com 3 Si6924AEDQ Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 25 25 VGS = 5 thru 2,5 V 20 I D - Drain Current (A) I D - Drain Current (A) 20 15 2V 10 15 10 TC = 125 °C 5 5 25 °C - 55 °C 0 0.00 0.25 0.50 0.75 1.00 1.25 0 0.0 1.50 1.0 2.0 2.5 VGS - Gate-to-Source Voltage (V) Output Characteristics Transfer Characteristics 3.0 V GS - Gate-to-Source Voltage (V) 5 0.04 VGS = 2.5 V 0.03 0.02 VGS = 4.5 V VGS = 3 V 0.01 0.00 VDS = 10 V ID = 4.6 A 4 3 2 1 0 0 4 8 12 16 20 0 1 2 ID - Drain Current (A) 4 5 6 7 Gate Charge 1.8 1.6 3 Qg - Total Gate Charge (nC) On-Resistance vs. Drain Current 20 VGS = 4.5 V ID = 4.6 A 10 I S - Source Current (A) RDS(on) - On-Resistance (Normalized) 1.5 VDS - Drain-to-Source Voltage (V) 0.05 RDS(on) - On-Resistance (Ω) 0.5 1.4 1.2 1.0 TJ = 150 °C TJ = 25 °C 0.8 0.6 - 50 1 - 25 0 25 50 75 100 125 TJ - Junction Temperature (°C) On-Resistance vs. Junction Temperature www.vishay.com 4 150 0 0.4 0.6 0.8 1.0 1.2 VSD - Source-to-Drain Voltage (V) Source-Drain Diode Forward Voltage Document Number: 72215 S-81056-Rev. B, 12-May-08 Si6924AEDQ Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 0.10 0.4 0.08 0.2 0.06 V GS(th) Variance (V) R DS(on) - On-Resistance (Ω) ID = 250 µA ID = 4.6 AA 0.04 0.0 - 0.2 - 0.4 0.02 - 0.6 - 50 0.00 0 1 2 3 4 5 - 25 0 25 50 75 100 125 150 TJ - Temperature (°C) VGS - Gate-to-Source Voltage (V) On-Resistance vs. Gate-to-Source Voltage Threshold Voltage 100 60 Limited by R DS(on)* 50 ID - Drain Current (A) 10 Power (W) 40 30 20 1 ms 1 10 ms 100 ms 0.1 1s TC = 25 °C Single Pulse 10 10 s DC 0.01 0 0.01 0.001 0.1 1 10 0.1 Time (s) 1 10 100 VDS - Drain-to-Source Voltage (V) * VGS > minimum VGS at which RDS(on) is specified Single Pulse Power Safe Operating Area 2 Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5 0.2 Notes: 0.1 0.1 PDM 0.05 t1 t2 1. Duty Cycle, D = 0.02 t1 t2 2. Per Unit Base = RthJA = 96 °C/W 3. TJM - TA = PDMZthJA(t) Single Pulse 0.01 10 -4 10 -3 4. Surface Mounted 10 -2 10 -1 1 10 100 600 Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Ambient Document Number: 72215 S-81056-Rev. B, 12-May-08 www.vishay.com 5 Si6924AEDQ Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 2 Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 10 -4 10 -3 10 -2 10 -1 Square Wave Pulse Duration (s) 1 10 Normalized Thermal Transient Impedance, Junction-to-Foot Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?72215. www.vishay.com 6 Document Number: 72215 S-81056-Rev. B, 12-May-08 Package Information Vishay Siliconix TSSOP: 8ĆLEAD JEDEC Part Number: MO-153 R 0.10 Corners) e A1 A A2 D 0.25 (Gage Plane) E1 MILLIMETERS E C L B Document Number: 71201 06-Jul-01 R 0.10 (4 Corners) oK1 L1 Dim A A1 A2 B C D E E1 e L L1 Y oK1 Min Nom Max – – 1.20 0.05 0.10 0.15 0.80 1.00 1.05 0.19 0.28 0.30 – 0.127 – 2.90 3.00 3.10 6.20 6.40 6.60 4.30 4.40 4.50 – 0.65 – 0.45 0.60 0.75 0.90 1.00 1.10 – – 0.10 0_ 3_ 6_ ECN: S-03946—Rev. G, 09-Jul-01 DWG: 5844 www.vishay.com 1 AN1001 Vishay Siliconix LITTLE FOOTR TSSOP-8 The Next Step in Surface-Mount Power MOSFETs Wharton McDaniel and David Oldham When Vishay Siliconix introduced its LITTLE FOOT MOSFETs, it was the first time that power MOSFETs had been offered in a true surface-mount package, the SOIC. LITTLE FOOT immediately found a home in new small form factor disk drives, computers, and cellular phones. The new LITTLE FOOT TSSOP-8 power MOSFETs are the natural evolutionary response to the continuing demands of many markets for smaller and smaller packages. LITTLE FOOT TSSOP-8 MOSFETs have a smaller footprint and a lower profile than LITTLE FOOT SOICs, while maintaining low rDS(on) and high thermal performance. Vishay Siliconix has accomplished this by putting one or two high-density MOSFET die in a standard 8-pin TSSOP package mounted on a custom leadframe. THE TSSOP-8 PACKAGE LITTLE FOOT TSSOP-8 power MOSFETs require approximately half the PC board area of an equivalent LITTLE FOOT device (Figure 1). In addition to the reduction in board area, the package height has been reduced to 1.1 mm. This is the low profile demanded by applications such as PCMCIA cards. It reduces the power package to the same height as many resistors and capacitors in 0805 and 0605 sizes. It also allows placement on the “passive” side of the PC board. The standard pinouts of the LITTLE FOOT TSSOP-8 packages have been changed from the standard established by LITTLE FOOT. This change minimizes the contribution of interconnection resistance to rDS(on) and maximizes the transfer of heat out of the package. Figure 2 shows the pinouts for a single-die TSSOP. Notice that both sides of the package have Source and Drain connections, whereas LITTLE FOOT has the Source and Gate connections on one side of the package, and the Drain connections are on the opposite side. Drain Drain Source Source Source Source Gate Figure 2. Top View Drain Pinouts for Single Die TSSOP Figure 3 shows the standard pinouts for a dual-die TSSOP-8. In this case, the connections for each individual MOSFET occupy one side. Drain 1 Side View Drain 2 Source 1 Source 2 Source 1 Source 2 Gate 1 Figure 1. An TSSOP-8 Package Next to a SOIC-8 Package with Views from Both Top and Side Document Number: 70571 12-Dec-03 Figure 3. Gate 2 Pinouts for Dual-Die TSSOP www.vishay.com 1 AN1001 Vishay Siliconix Because the TSSOP has a fine pitch foot print, the pad layout is somewhat more demanding than the layout of the SOIC. Careful attention must be paid to silkscreen-to-pad and soldermask-to-pad clearances. Also, fiduciary marks may be required. The design and spacing of the pads must be dealt with carefully. The pads must be sized to hold enough solder paste to form a good joint, but should not be so large or so placed as to extend under the body, increasing the potential for solder bridging. The pad pattern should allow for typical pick and place errors of 0.25 mm. See Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs, (http://www.vishay.com/doc?72286), for the recommended pad pattern for PC board layout. THERMAL ISSUES LITTLE FOOT TSSOP MOSFETs have been given thermal ratings using the same methods used for LITTLE FOOT. The maximum thermal resistance junction-to-ambient is 83_C/W for the single die and 125_C/W for dual-die parts. TSSOP relies on a leadframe similar to LITTLE FOOT to remove heat from the package. The single- and dual-die leadframes are shown in Figure 4. Figure 5. The actual test is based on dissipating a known amount of power in the device for a known period of time so the junction temperature is raised to 150_C. The starting and ending junction temperatures are determined by measuring the forward drop of the body diode. The thermal resistance for that pulse width is defined by the temperature rise of the junction above ambient and the power of the pulse, DTja/P. Figure 6 shows the single pulse power curve of the Si6436DQ laid over the curve of the Si9936DY to give a comparison of the thermal performance. The die in the two devices have equivalent die areas, making this a comparison of the packaging. This comparison shows that the TSSOP package performs as well as the SOIC out to 150 ms, with long-term performance being 0.5 W less. Although the thermal performance is less, LITTLE FOOT TSSOP will operate in a large percentage of applications that are currently being served by LITTLE FOOT. 14.0 12.0 a) 8-Pin Single-Pad TSSOP Power (W) 10.0 8.0 6.0 Si9936 4.0 Si6436 2.0 0.0 0.1 b) 8-Pin Dual-Pad TSSOP Figure 4. Leadframe The MOSFETs are characterized using a single pulse power test. For this test the device mounted on a one-square-inch piece of copper clad FR-4 PC board, such as those shown in Figure 5. The single pulse power test determines the maximum amount of power the part can handle for a given pulse width and defines the thermal resistance junction-to-ambient. The test is run for pulse widths ranging from approximately 10 ms to 100 seconds. The thermal resistance at 30 seconds is the rated thermal resistance for the part. This rating was chosen to allow comparison of packages and leadframes. At longer pulse widths, the PC board thermal charateristics become dominant, making all parts look the same. www.vishay.com 2 Figure 6. 1 Time (Sec.) 10 100 Comparison of Thermal Performance CONCLUSION TSSOP power MOSFETs provide a significant reduction in PC board footprint and package height, allowing reduction in board size and application where SOICs will not fit. This is accomplished using a standard IC package and a custom leadframe, combining small size with good power handling capability. For the TSSOP-8 package outline visit: http://www.vishay.com/doc?71201 For the SOIC-8 package outline visit: http://www.vishay.com/doc?71192 Document Number: 70571 12-Dec-03 AN806 Vishay Siliconix Mounting LITTLE FOOTR TSSOP-8 Power MOSFETs Wharton McDaniel Surface-mounted LITTLE FOOT power MOSFETs use integrated circuit and small-signal packages which have been been modified to provide the heat transfer capabilities required by power devices. Leadframe materials and design, molding compounds, and die attach materials have been changed, while the footprint of the packages remains the same. See Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFET, (http://www.vishay.com/doc?72286), for the basis of the pad design for a LITTLE FOOT TSSOP-8 power MOSFET package footprint. In converting the footprint to the pad set for a power device, designers must make two connections: an electrical connection and a thermal connection, to draw heat away from the package. In the case of the TSSOP-8 package, the thermal connections are very simple. Pins 1, 5, and 8 are the drain of the MOSFET for a single MOSFET package and are connected together. In the dual package, pins 1 and 8 are the two drains. For a small-signal device or integrated circuit, typical connections would be made with traces that are 0.020 inches wide. Since the drain pins also provide the thermal connection to the package, this level of connection is inadequate. The total cross section of the copper may be adequate to carry the current required for the application, but it presents a large thermal impedance. Also, heat spreads in a circular fashion from the heat source. In this case the drain pins are the heat sources when looking at heat spread on the PC board. 0.284 7.6 0.032 0.8 0.026 0.66 0.018 0.45 0.073 1.78 0.122 3.1 The pad patterns with copper spreading for the single-MOSFET TSSOP-8 (Figure 1) and dual-MOSFET TSSOP-8 (Figure 2) show the starting point for utilizing the board area available for the heat-spreading copper. To create this pattern, a plane of copper overlies the drain pins. The copper plane connects the drain pins electrically, but more importantly provides planar copper to draw heat from the drain leads and start the process of spreading the heat so it can be dissipated into the ambient air. These patterns use all the available area underneath the body for this purpose. 0.284 7.6 0.032 0.8 0.026 0.66 0.018 0.45 0.073 1.78 0.122 3.1 0.091 1.65 FIGURE 2. Dual MOSFET TSSOP-8 Pad Pattern with Copper Spreading Since surface-mounted packages are small, and reflow soldering is the most common way in which these are affixed to the PC board, “thermal” connections from the planar copper to the pads have not been used. Even if additional planar copper area is used, there should be no problems in the soldering process. The actual solder connections are defined by the solder mask openings. By combining the basic footprint with the copper plane on the drain pins, the solder mask generation occurs automatically. A final item to keep in mind is the width of the power traces. The absolute minimum power trace width must be determined by the amount of current it has to carry. For thermal reasons, this minimum width should be at least 0.020 inches. The use of wide traces connected to the drain plane provides a low impedance path for heat to move away from the device. 0.118 3.54 FIGURE 1. Single MOSFET TSSOP-8 Pad Pattern with Copper Spreading Document Number: 70738 17-Dec-03 www.vishay.com 1 Application Note 826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR TSSOP-8 0.092 (2.337) 0.026 (4.623) (1.016) 0.182 0.040 (6.655) 0.262 (0.660) 0.014 0.012 (0.356) (0.305) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Return to Index APPLICATION NOTE Document Number: 72611 Revision: 21-Jan-08 www.vishay.com 27 Legal Disclaimer Notice Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. 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It is the customer’s responsibility to validate that a particular product with the properties described in the product specification is suitable for use in a particular application. Parameters provided in datasheets and/or specifications may vary in different applications and performance may vary over time. All operating parameters, including typical parameters, must be validated for each customer application by the customer’s technical experts. Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein. Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the Vishay product could result in personal injury or death. Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk and agree to fully indemnify and hold Vishay and its distributors harmless from and against any and all claims, liabilities, expenses and damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that Vishay or its distributor was negligent regarding the design or manufacture of the part. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners. Document Number: 91000 Revision: 11-Mar-11 www.vishay.com 1