CVPD-920 Model 9X14 mm SMD, 3.3V, LVPECL Frequency Range: Frequency Pulling: Temperature Range: (Option X) Storage: Input Voltage: Control Voltage: Input Current: Output: Symmetry: Rise/Fall Time: Linearity: Logic: Disable Time: Start-up Time: Phase Jitter: 12KHz to 80MHz Phase Noise: 10Hz 100Hz 1KHz 10KHz 100KHz Aging: 50MHz to 125MHz ±20ppm APR Min 0°C to 70°C -40°C to 85°C -55°C to 120°C 3.3V ±0.3V 1.65V ±1.65V 88mA Max Differential LVPECL 45/55% Max @ 50% Vcc 1ns Max @ 20% to 80% Vcc ±10% Max Terminated to Vcc-2V into 50 ohms "0" = Vcc-1.85V Min, Vcc-1.62V Max "1" = Vcc-1.02V Min, Vcc-0.81V Max 200ns 1ms Typ., 2ms Max 0.5psec Typ., 1psec RMS Max -65dBc/Hz Typical -98dBc/Hz Typical -125dBc/Hz Typical -140dBc/Hz Typical -145dBc/Hz Typical <3ppm 1st/yr, <1ppm every year thereafter Designed to meet today's requirements for 3.3V Differential LVPECL applications. The CVPD-920 is produced using our cost saving FR5 PCB and UM-1 overtone crystal technology. This design offers considerable cost savings over other HFF VCXO products when broad frequency pulling is not required. Also available in 14 pin dip fully hermetic package. SUGGESTED PAD LAYOUT 0.360 (9.14) 0.040 (1.01) 0.100 (2.54) 0.560 (14.2) 0.560 (14.2) CRYSTEK P/N Frequency Date Code 0.210 (5.3) 1 2 3 6 5 4 0.050 (1.27) 0.070 (1.77) 0.090 (2.28) 0.200 (5.08) 0.280 (7.11) 0.200 (5.08) RECOMMENDED REFLOW SOLDERING PROFILE TEMPERATURE Ramp-Up 3°C/Sec Max. Critical Temperature Zone Ramp-Down 6°C/Sec. 260°C 217°C Crystek Part Number Guide CVPD-920 X - 100.000 #1 200°C #2 #3 #4 #1 Crystek 9x14 SMD PECL VCXO #2 Model 920 #3 Temp. Range: Blank = 0/70°C, X=-40/85°C #4 Frequency in MHz: 3 or 6 decimal places 150°C Preheat 180 Secs. Max. 8 Minutes Max. 90 Secs. Max. 260°C for 10 Secs. Max. NOTE: Reflow Profile with 240°C peak also acceptable. PIN Function 1 2 3 4 5 6 Control Volt E/D GND OUT COUT Vcc Example: CVPD-920X-25-100.000 = 3.3V, 45/55, -40/85°C, 25ppm, 100.000 MHz Enable/Disable Function Pin 2 Output Pin Open "0" level Vcc-1.620V Max "1" level Vcc-1.025V Min Active Active Disabled Disabled State: Pin 4 will assume a fixed level of logic "0" Pin 5 will assume a fixed level of logic "1" Specifications subject to change without notice. CRYSTEK CORPORATION TD-030701 Rev. D 12730 Commonwealth Drive • Fort Myers, Florida 33913 Phone: 239-561-3311 • 800-237-3061 Fax: 239-561-1025 • www.crystek.com