3D3424 MONOLITHIC QUAD 4-BIT PROGRAMMABLE DELAY LINE (SERIES 3D3424) FEATURES • • • • • • • • • • • PACKAGES Four indep’t programmable lines on a single chip All-silicon CMOS technology Low quiescent current (5mA typical) Leading- and trailing-edge accuracy Vapor phase, IR and wave solderable Increment range: 1ns through 300ns Delay tolerance: 3% or 2ns (see Table 1) Line-to-line matching: 1% or 1ns typical Temperature stability: ±1.5% typical (-40C to 85C) Vdd stability: ±0.5% typical (3.0V to 3.6V) Minimum input pulse width: 10% of total delay I1 1 14 VDD SC 2 13 AL I2 3 12 O1 I3 4 11 SO I4 5 10 O2 SI 6 9 O3 GND 7 8 O4 I1 SC I2 I3 I4 SI GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD AL O1 SO O2 O3 O4 SOIC-14 3D3424D-xx DIP-14 3D3424-xx For mechanical dimensions, click here. For package marking details, click here. FUNCTIONAL DESCRIPTION PIN DESCRIPTIONS The 3D3424 device is a small, versatile, quad 4-bit programmable monolithic delay line. Delay values, programmed via the serial interface, can be independently varied over 15 equal steps. The step size (in ns) is determined by the device dash number. Each input is reproduced at the corresponding output without inversion, shifted in time as per user selection. For each line, the delay time is given by: I1-I4 O1-O4 AL SC SI SO VDD GND TDn = T0 + An * TI Signal Inputs Signal Outputs Address Latch In Serial Clock In Serial Data In Serial Data Out 3.3V Ground where T0 is the inherent delay, An is the delay address of the n-th line and TI is the delay increment (dash number). The desired addresses are shifted into the device via the SC and SI inputs, and the addresses are latched using the AL input. The serial interface can also be used to enable/disable each delay line. The 3D3424 operates at 3.3 volts and has a typical T0 of 9ns. The 3D3424 is CMOS-compatible, capable of sourcing or sinking 4mA loads, and features both rising- and falling-edge accuracy. The device is offered in a standard 14-pin auto-insertable DIP and a space saving surface mount 14-pin SOIC. TABLE 1: PART NUMBER SPECIFICATIONS Part Number 3D3424-1 3D3424-1.5 3D3424-2 3D3424-4 3D3424-5 3D3424-10 3D3424-15 3D3424-20 3D3424-40 3D3424-50 3D3424-100 3D3424-200 3D3424-300 DELAYS & TOLERANCES (NS) Delay Inherent Total Relative Step Delay Delay Tolerance 1.0 ± 0.50 9.0 ± 2.0 24.0 ± 2.0 3% or 0.50ns 1.5 ± 0.75 9.0 ± 2.0 31.5 ± 2.0 3% or 0.50ns 2.0 ± 1.00 9.0 ± 2.0 39.0 ± 2.0 3% or 0.75ns 4.0 ± 2.00 9.0 ± 2.0 69.0 ± 2.0 3% or 0.75ns 5.0 ± 2.50 9.0 ± 2.0 84.0 ± 2.5 3% or 0.75ns 10 ± 2.50 9.0 ± 2.0 159 ± 5.0 3% or 1.25ns 15 ± 3.75 9.0 ± 2.0 234 ± 7.5 3% or 1.88ns 20 ± 5.00 9.0 ± 2.0 309 ± 10 3% or 2.50ns 40 ± 10.0 9.0 ± 2.0 609 ± 20 3% or 5.00ns 50 ± 10.0 9.0 ± 2.0 759 ± 25 3% or 6.25ns 100 ± 12.5 9.0 ± 2.0 1509 ± 50 3% or 12.5ns 200 ± 20.0 9.0 ± 2.0 3009 ± 100 3% or 25.0ns 300 ± 30.0 9.0 ± 2.0 4509 ± 150 3% or 37.5ns INPUT RESTRICTIONS Max Frequency Min Pulse Width Recom’d Absolute Recom’d Absolute 13.8 MHz 166 MHz 36 ns 3.0 ns 10.5 MHz 111 MHz 48 ns 4.5 ns 8.5 MHz 83 MHz 59 ns 6.0 ns 4.8 MHz 41 MHz 104 ns 12.0 ns 4.0 MHz 33 MHz 126 ns 15.0 ns 2.1 MHz 33 MHz 239 ns 15.0 ns 1.4 MHz 22 MHz 351 ns 22.5 ns 1.0 MHz 16 MHz 464 ns 30.0 ns 550 KHz 8.3 MHz 914 ns 60.0 ns 440 KHz 6.6 MHz 1.2 us 75.0 ns 220 KHz 3.3 MHz 2.3 us 150 ns 110 KHz 1.6 MHz 4.5 us 300 ns 74 KHz 1.1 MHz 6.8 us 450 ns NOTE: Any increment between 1ns and 300ns not shown is also available as standard See page 4 for details regarding input restrictions 2006 Data Delay Devices Doc #06020 6/6/2006 DATA DELAY DEVICES, INC. 3 Mt. Prospect Ave. Clifton, NJ 07013 1 3D3424 APPLICATION NOTES THEORY OF OPERATION PROGRAMMED DELAY INTERFACE The quad 4-bit programmable 3D3424 device architecture is comprised of four independently operating delay lines. Each delay line produces at its output a replica of the signal present at its input, shifted in time. A single delay line is comprised of a number of delay cells connected in series. Delay selection is achieved by routing one output in each string of cells to its respective output pin (O1-O4). The delay of each of the four lines can be controlled independently, via the serial interface, as described in the next section. Figure 1 illustrates the main functional blocks of the 3D3424 device. Since the device is a CMOS design, all unused input pins must be returned to well defined logic levels (VDD or GND). The delays are adjusted by first shifting a 20-bit programming word into the device via the SC and SI pins, then strobing the AL signal to latch the values. The bit sequence is shown in Table 2, and the associated timing diagram is shown in Figure 2. Each line has associated with it an enable bit. Setting this bit low will force the corresponding delay line output to a high impedance state, while setting it high returns the line to its normal operation. The device contains an SO output, which can be used to cascade multiple devices, as shown in Figure 3. The change in delay from one address setting to the next is called the increment, or LSB. It is nominally equal to the device dash number. The minimum delay, achieved by setting the address of a line to zero, is called the inherent delay. TABLE 2: BIT SEQUENCE For best performance, it is essential that the power supply pin be adequately bypassed and filtered. In addition, the power bus should be of as low an impedance construction as possible. Power planes are preferred. Also, signal traces should be kept as short as possible. DELAY LINE I4 O4 DELAY LINE I3 O3 DELAY LINE I2 O2 DELAY LINE I1 ADDR4 ADDR3 AL Bit ADDR2 ADDR1 O1 ENABLES 20-BIT LATCH SI SO 20-BIT SHIFT REGISTER SC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Delay Line 4 3 2 1 1 2 3 4 Function Output Enable Output Enable Output Enable Output Enable Address Bit 3 Address Bit 2 Address Bit 1 Address Bit 0 Address Bit 3 Address Bit 2 Address Bit 1 Address Bit 0 Address Bit 3 Address Bit 2 Address Bit 1 Address Bit 0 Address Bit 3 Address Bit 2 Address Bit 1 Address Bit 0 Figure 1: Functional block diagram tLW LATCH (AL) tCW tCW tCSL CLOCK (SC) SERIAL INPUT (SI) SERIAL OUTPUT (SO) DELAY TIMES tDSC tDHC NEW BIT 1 NEW BIT 2 NEW BIT 20 tPCQ OLD BIT 1 OLD BIT 2 OLD BIT 20 NEW BIT 1 tLDX tLDV NEW VALUES PREVIOUS VALUES Figure 2: Serial interface timing diagram Doc #06020 6/6/2006 DATA DELAY DEVICES, INC. Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com 2 3D3424 APPLICATION NOTES (CONT’D) DELAY ACCURACY DELAY STABILITY There are a number of ways of characterizing the delay accuracy of a programmable line. The first is the differential nonlinearity (DNL), also referred to as the increment error. It is defined as the deviation of the delay step at a given address from its nominal value. For all dash numbers, the DNL is within 1/2 LSB at every address (see Table 1: Delay Step). The delay of CMOS integrated circuits is strongly dependent on power supply and temperature. The 3D3424 utilizes novel compensation circuitry to minimize the delay variations induced by fluctuations in power supply and/or temperature. With regard to stability, the delay of the 3D3424 at a given address, i, can be split into two components: the inherent delay (T0) and the relative delay (Ti – T0). These components exhibit very different stability coefficients, both of which must be considered in very critical applications. The integrated nonlinearity (INL) is determined by first constructing the least-squares best fit straight line through the delay-versus-address data. The INL is then the deviation of a given delay from this line. For all dash numbers, the INL is within 1.0 LSB at every address. The thermal coefficient of the relative delay is limited to ±250 PPM/C, which is equivalent to a variation, over the -40C to 85C operating range, of ±1.5% from the room-temperature delay settings. This holds for dash numbers greater than 1.5. For smaller dash numbers, the thermal drift will be larger and will always be positive. The thermal coefficient of the inherent delay is nominally +25ps/C for all dash numbers. The relative error is defined as follows: erel = (Ti – T0) – i * Tinc where i is the address, Ti is the measured delay at the i’th address, T0 is the measured inherent delay, and Tinc is the nominal increment. It is very similar to the INL, but simpler to calculate. For most dash numbers, the relative error is less than 1/8 LSB at every address (see Table 1: Relative Tolerance). The power supply sensitivity of the relative delay is ±0.5% over the 3.0V to 3.6V operating range, with respect to the delay settings at the nominal 3.3V power supply. This holds for all dash numbers greater than 1.5. For smaller dash numbers, the voltage sensitivity will be greater and will always be negative. The sensitivity of the inherent delay is nominally -5ps/mV for all dash numbers. The absolute error is defined as follows: eabs = Ti – (Tinh + i * Tinc) where Tinh is the nominal inherent delay. The absolute error tolerance is given for addresses 0 and 15 (see Table 1: Inherent Delay, Total Delay, respectively). At any intermediate address, the tolerance can be found via linear interpolation of the address 0 & address 15 tolerances. The matching error is a measure of how well the delay of the four lines track each other when they are all programmed to the same address. The lines are typically matched to within 1% or 1ns, whichever is greater, for all addresses and all dash numbers. 3D3424 SI FROM WRITING DEVICE SO SC AL 3D3424 SI SC SO 3D3424 SI AL SC SO AL TO NEXT DEVICE Figure 3: Cascading Multiple Devices Doc #06020 6/6/2006 DATA DELAY DEVICES, INC. 3 Mt. Prospect Ave. Clifton, NJ 07013 3 3D3424 APPLICATION NOTES (CONT’D) INPUT SIGNAL CONSIDERATIONS The frequency and/or pulse width (high or low) of operation may adversely impact the specified delay and increment accuracy of the particular device. The reasons for the dependency of the output delay accuracy on the input signal characteristics are varied and complex. Therefore, a recommended and an absolute maximum operating input frequency and a recommended and an absolute minimum operating pulse width have been specified. OPERATING FREQUENCY The absolute maximum operating frequency specification, tabulated in Table 1, determines the highest frequency of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable duty cycle distortion. The recommended maximum operating frequency specification determines the highest frequency of the delay line input signal for which the output delay accuracy is guaranteed. Operation above the recommended maximum frequency will cause the delays to shift slighty with respect to their values at low-frequency operation. The magnitudes of these deviations will increase as the absolute maximum frequency is approached. However, if the input frequency and pulse width remain constant, the device will exhibit the same delays from one period to the next (ie, no appreciable jitter). OPERATING PULSE WIDTH The absolute minimum operating pulse width (high or low) specification, tabulated in Table 1, determines the smallest pulse width of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable pulse width distortion. Doc #06020 6/6/2006 The minimum operating pulse width (high or low) specification determines the smallest pulse width of the delay line input signal for which the output delay accuracy tabulated in Table 1 is guaranteed. Operation below the recommended minimum pulse width will cause the delays to shift slighty with respect to their values at long-pulse-width operation. The magnitudes of these deviations will increase as the absolute minimum pulse width is approached. However, if the input pulse width and frequency remain constant, the device will exhibit the same delays from one period to the next (ie, no appreciable jitter). PROGRAMMED DELAY UPDATE A delay line is a memory device. It stores information present at the input for a time equal to the delay setting before presenting it at the output. Each 4-bit delay line in the 3D3424 is represented by 15 serially connected delay elements (individually addressed by the programming data), each capable of storing data for a time equal to the device increment (step time). The delay line memory property, in conjunction with the operational requirement of “instantaneously” connecting the delay element addressed by the programming data to the output, may inject spurious information onto the output data stream. In order to ensure that spurious outputs do not occur, it is essential that the input signal be idle (held high or low) for a short duration prior to updating the programmed delay. This duration is given by the maximum programmable delay. Satisfying this requirement allows the delay line to “clear” itself of spurious edges. Once the new address is loaded, the input signal can begin to switch. DATA DELAY DEVICES, INC. Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com 4 3D3424 DEVICE SPECIFICATIONS TABLE 3: ABSOLUTE MAXIMUM RATINGS PARAMETER DC Supply Voltage Input Pin Voltage Input Pin Current Storage Temperature Lead Temperature SYMBOL VDD VIN IIN TSTRG TLEAD MIN -0.3 -0.3 -10 -55 MAX 7.0 VDD+0.3 10 150 300 UNITS V V mA C C NOTES 25C 10 sec TABLE 4: DC ELECTRICAL CHARACTERISTICS (-40C to 85C, 3.0V to 3.6V) PARAMETER Static Supply Current* High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current High Level Output Current SYMBOL IDD VIH VIL IIH IIL IOH MIN Low Level Output Current IOL Output Rise & Fall Time TYP 5.0 MAX 7.0 -0.1 -0.1 0.0 0.0 -8.0 0.8 0.1 0.1 -6.0 6.0 7.5 mA 2 ns 2.0 TR & TF *IDD(Dynamic) = 4 * CLD * VDD * F where: CLD = Average capacitance load/line (pf) F = Input frequency (GHz) UNITS mA V V µA µA mA NOTES VDD = 3.6V VIH = VDD VIL = 0V VDD = 3.0V VOH = 2.4V VDD = 3.0V VOL = 0.4V CLD = 5 pf Input Capacitance = 10 pf typical Output Load Capacitance (CLD) = 25 pf max TABLE 5: AC ELECTRICAL CHARACTERISTICS (-40C to 85C, 3.0V to 3.6V) PARAMETER Latch Width Data Setup to Clock Data Hold from Clock Clock Width (High or Low) Clock Setup to Latch Clock to Serial Output Latch to Delay Valid Latch to Delay Invalid Input Pulse Width Input Period Input to Output Delay SYMBOL TLW tDSC tDHC tCW tCSL tPCQ tLDV tLDX tWI Period tPLH, tPHL MIN 10 10 1 15 20 TYP MAX 12 35 20 45 5 10 20 UNITS ns ns ns ns ns ns ns ns % of Total Delay % of Total Delay ns NOTES 1 1 See Table 1 See Table 1 See Text NOTES: 1 - Refer to PROGRAMMED DELAY UPDATE section Doc #06020 6/6/2006 DATA DELAY DEVICES, INC. 3 Mt. Prospect Ave. Clifton, NJ 07013 5 3D3424 SILICON DELAY LINE AUTOMATED TESTING TEST CONDITIONS INPUT: Ambient Temperature: 25oC ± 3oC Supply Voltage (VDD): 5.0V ± 0.1V Input Pulse: High = 3.3V ± 0.1V Low = 0.0V ± 0.1V Source Impedance: 50Ω Max. Rise/Fall Time: 3.0 ns Max. (measured between 0.6V and 2.7V ) Pulse Width: PWIN = 1.25 x Total Delay Period: PERIN = 2.5 x Total Delay OUTPUT: Rload: Cload: Threshold: 10KΩ ± 10% 5pf ± 10% 1.65V (Rising & Falling) Device Under Test Digital Scope 10KΩ 470Ω 5pf NOTE: The above conditions are for test only and do not in any way restrict the operation of the device. PRINTER COMPUTER SYSTEM REF PULSE GENERATOR IN1 DEVICE UNDER IN2 TEST (DUT) IN3 IN4 OUT TRIG OUT1 OUT2 OUT3 OUT4 IN TRIG DIGITAL SCOPE/ TIME INTERVAL COUNTER Figure 4: Test Setup PERIN PW IN tRISE INPUT SIGNAL tFALL VIH 2.7V 1.65V 0.6V 2.7V 1.65V 0.6V tPLH OUTPUT SIGNAL VIL tPHL 1.65V VOH 1.65V VOL Figure 5: Timing Diagram Doc #06020 6/6/2006 DATA DELAY DEVICES, INC. Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com 6