ESTEK MC34063A

34063
Description
The MC34063A Series is a monolithic control circuit containing the primary functions required for DC-to-DC converters.
These devices consist of an internal temperature compensated reference, comparator, controlled duty cycle oscillator
with an active current limit circuit, driver and high current output switch. This series was specifically designed to be
incorporated in Step-Down and Step-Up and Voltage-Inverting applications with a minimum number of external
components.
Features
•
•
•
•
•
•
•
Operation from 3.0 V to 40 V Input
Low Standby Current
Current Limiting
Output Switch Current to 1.5 A
Output Voltage Adjustable
Frequency Operation to 100 kHz
Precision 2% Reference
Plastic Package
Pin Connections
Internal Block Digram
Driver
Collector
1
8
S
Q
Q2
R
Ipk
Q1
7
Sense
Ipk
Oscillator
100
2
CT
3
VCC
Comparator
Inverting
Input
Switch
Collector
6
Comparator
Switch
Emitter
Timing
Capacitor
1.25 V
Reference
4
5
Gnd
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34063
Absolute Maximum Ratings
Symbol
VCC
VIR
Parameter
VC(switch)
Power Supply Voltage
Comparator Input Voltage Range
Switch Collector Voltage
VE(switch)
VCE(switch)
VC(driver)
IC(driver)
ISW
Switch Emitter Voltage (V PIN1 = 40 V)
Switch Collector to Emitter Voltage
Driver Collector Voltage
Driver Collector Current (Note 1)
Switch Current
TJ
Operating Junction Temperature
TA
Operating Ambient Temperature Range
Tstg
Storage Temperature Range
Maximum
Units
40
-0.3 to +40
40
Vdc
Vdc
Vdc
40
40
40
100
1.5
Vdc
Vdc
Vdc
mA
A
+150
°C
0 to +70
°C
-65 to +150
°C
Electrical Characteristics
(Vcc=5.0V, Ta=Tlow
specified)
to Thigh , unless otherwise
Characteristics
OSCILLATOR
Frequency (Vpin5 = 0V, CT = 1.0 nF, TA = 25°C)
Charge Current(VCC = 5.0V to 40V, TA = 25°C)
Discharge Current (V CC = 5.0V to 40V, TA = 25°C)
Discharge to Charge Current Ratio (Pin 7 to V CC, TA = 25°C)
Current Limit Sense Voltage (I chg = Idischg, TA = 25°C)
OUTPUT SWITCH (NOTE 2)
Saturation Voltage, Darlington Connection (I SW = 1.0 A, Pins 1, 8 connected)
Saturation Voltage, Darlington Connection (I SW = 1.0 A, Rpin 8 = 82Ω to VCC , Forced β ≅ 20)
DC Current Gain (ISW = 1.0 A, VCE = 5.0 V, TA = 25°C)
Collector Off-State Current (V CE = 40 V)
COMPARATOR
Threshold Voltage
(TA=25°C)
(TA =Tlow to Thigh)
Threshold Voltage Line Regulation
(Vcc=3.0 V to 40 V)
Input Bias Current
(Vin=0 V)
TOTAL DEVICE
Supply Current (Vcc = 5.0 V to 40 V, CT = 1.0 nF, Pin 7 = V CC, Vpin 5 > Vth, Pin 2 =
Gnd, remaining pins open)
Symbol
Min
Typ
Max
Units
fOSC
Ichg
Idischg
Idischg /
Ichg
Vipk(sence)
24
24
140
5.2
33
35
220
6.5
42
42
260
7.5
kHz
µA
µA
–
250
300
350
mV
VCE(sat)
VCE(sat)
hFE
IC(off)
–
–
50
–
1.0
0.45
75
40
1.3
0.7
–
100
V
V
–
µA
Vth
Regline
V
1.225 1.25
1.21
–
–
1.4
1.275
1.29
5.0
mV
IIB
–
-20
-400
nA
ICC
–
–
4.0
mA
NOTES : 1.Maximum package power dissipation limits must be observed.
2.Low duty cycle pulse techniques are used during test to maintain junction temperature
as close to ambient temperature as possible
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34063
Typical Performance Characteristics
Figure 1. Output Switch On-Off Time versus
Oscillator Timing Capacitor
Figure 2. Timing Capacitor Waveform
A
Figure 3. Emitter Follower Configuration Output
Saturation Voltage versus Emitter Current
versus
Figure 4. Common Emitter Configuration
Output Switch Saturation Voltage
Collector Current
Figure 5. Current Limit Sense Voltage
versus Temperature
Figure 6. Standby Supply Current versus
Supply Voltage
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34063
Typical Applications Circuit
Figure 1. Step-Up Converte .r
Note: R to 0 for constant Vin
Figure 2b. External NPN Saturated Switch.
Figure 2a. External NPN Switch.
Figure 2. External Current Boost Connections for I
P
eak Greater than
1.5
.A
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34063
Figure 3. Step-Down Converte .r
Figure 4a. External NPN Switch.
Figure 4b. External PNP Suturated Switch.
Figure 4. External Current Boost Connections for I
P
eak Greater than
1.5
.A
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34063
Figure 5. Voltage Inverting Converte .r
Figure 6a. External NPN Switch.
Figure 6b. External PNP Saturated Switch.
Figure 6. External Current Boost Connections for I
P
eak Greater than
1.5
.A
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34063
Design Formula Table
Calculation
Step-Up
ton/toff
+
V V
in
−
−
out
Step-Down
V
in
(min)
in
(min)
V
V
out
sat
(ton+toff)max
t
2 I
RSC

(max)
 on

f -5
4.0x10
ton

+ 1


V −sat  ×t
on (max)
I pk ( switchV) 



CO
9
f
in
min
4.0 x 10-5
ton
2I out(max)
0.3/lpk(switch)
L(min)
+VF
V +V
in
sat
V
1
out
1
f -5
4.0 x 10
lpk(switch)
+ VF
−Vsat −
V
1
CT
Voltage-Inverting
0.3/lpk(switch)
I pk ( switch )
( t 8V

+ 1

0.3/lpk(switch)
Vin (min) V sat V
−

out 

 × on (max)
I pk ( switch )


I out ton
Vripple ( pp )


ont
2I
+
t
ripple ( pp )
)
Vin(min) V

sat
 I
pk ( switch)

9
−
 t on(max)


tI
Vripple ( pp )
TERMS AND DEFINITIONS
Vsat Saturation voltage of the output switch.
VF Forward voltage drop of the output rectifier.
The following power supply characteristics must be chosen:

R
Vout = .1 25 1+

R

1

Vin Nominal input voltage.
Vout Desired output voltage,
Iout Desired output current.
fmin Minimum desired output switching frequency at the selected values of V in and IO.
Vripple(p-p) –Desired peack-to-peack output ripple voltage. In practice, the calculated capacitor value will need to be increased due to its
equivalent series resistance and board layout. The ripple voltage should be kept to a low value since it will directly affect the
line and load regulation.
Ordering Information
O RDERING NUM BER
34063A
Address :
P ACK AGE
SOP-8 /DIP-8
M ARKING
MC34063A
6A06--6A07
Rm 6A07,Changyin Office Building ,No.88,Yong Ding Road,Hai Dian District ,Beijing
Postalcode:100039
Tel: 86-010-58895780 / 81 / 82 / 83 / 84
Fax : 010-58895793
Http://www.estek.com.cn
Email:sales@estek.com.cn
REV No:01-060810
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