HANBit HMD1M36M3EG 4Mbyte(1Mx36) 72-pin SIMM EDO with Parity MODE, 1K Ref. 5V Part No. HMD1M36M3EG GENERAL DESCRIPTION The HMD1M36M3EG is a 1M x 36 bit dynamic RAM high-density memory module. The module consists of two CMOS 1M x 16 bit DRAMs in 42-pin TSOP packages and one CMOS 1M x 4bit Quad CAS DRAM in 28pin SOJ package mounted on a 72-pin. A 0.1 or 0.22uF decoupling capacitor is mounted on the printed circuit board for each DRAM components. The module is a single In-line memory module with edge connections and is intended for mounting in to 72pin edge connector sockets. All module components may be powered from a single 5V DC power supply. All inputs and outputs are TTL-compatible. PIN ASSIGNMENT FEATURES w Part Identification HMD1M36M3EG- 1K Cycles/16ms Ref, Gold w Access times : 50, 60ns w High-density 4MByte design w Single +5V ±0.5V power supply wJEDEC standard pinout w EDO Mode operation w TTL compatible inputs and outputs w FR4-PCB design OPTIONS MARKING w Timing PIN SYMBOL PIN SYMBOL PIN SYMBOL 1 Vss 25 DQ24 49 DQ9 2 DQ0 26 DQ7 50 DQ27 3 DQ18 27 DQ25 51 DQ10 4 DQ1 28 A7 52 DQ28 5 DQ19 29 NC 53 DQ11 6 DQ2 30 Vcc 54 DQ29 7 DQ20 31 A8 55 DQ12 8 DQ3 32 A9 56 DQ30 9 DQ21 33 NC 57 DQ13 10 Vcc 34 /RAS0 58 DQ31 11 NC 35 DQ26 59 Vcc 50ns access -5 12 A0 36 DQ8 60 DQ32 60ns access -6 13 A1 37 DQ17 61 DQ14 14 A2 38 DQ35 62 DQ33 15 A3 39 Vss 63 DQ15 16 A4 40 /CAS0 64 DQ34 17 A5 41 /CAS2 65 DQ16 18 A6 42 /CAS3 66 NC 19 NC 43 /CAS1 67 PD1 w Packages 72-pin SIMM M PRESENCE DETECT PINS Pin 50ns 60ns PD1 Vss Vss 20 DQ4 44 /RAS0 68 PD2 PD2 NC NC 21 DQ22 45 NC 69 PD3 PD3 Vss NC 22 DQ5 46 NC 70 PD4 23 DQ23 47 /WE 71 NC 24 DQ6 48 NC 72 Vss PD4 Vss NC PERFORMANCE RANGE Speed tRAC tCAC tRC tHPC 5 50ns 13ns 90ns 26ns 6 60ns 15ns 110ns 30ns URL:www.hbe.co.kr REV.1.0(August.2002) 1 HANBit Electronics Co.,Ltd. HANBit HMD1M36M3EG FUNCTIONAL BLOCK DIAGRAM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U0 /RAS0 /RAS /CAS0 /LCAS /CAS1 /UCAS /OE /W /RAS /CAS0 /CAS1 /CAS2 /CAS3 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 A0-A11 DQ16 U1 /W DQ0 DQ1 DQ2 DQ3 A0-A11 U2 /RAS /CAS2 /LCAS /CAS3 /UCAS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 A0-A11 DQ15 /OE W DQ0-DQ7 DQ9-DQ16 DQ8 DQ17 DQ26 DQ35 DQ18-DQ25 DQ27-DQ34 /W A0-A11 Vcc URL:www.hbe.co.kr REV.1.0(August.2002) 2 0.1uF or 0.22uF To all DRAMs Capacitor for each DRAM HANBit Electronics Co.,Ltd. HANBit HMD1M36M3EG Vss Absolute Maximum Ratings PARAMETER SYMBOL RATING VIN ,OUT -1V to 7.0V Voltage on Vcc Supply Relative to Vss Vcc -1V to 7.0V Power Dissipation PD 9W TSTG -55oC to 150oC Voltage on Any Pin Relative to Vss Storage Temperature Short Circuit Output Current IOS 50mA w Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED DC OPERATING CONDITIONS ( Voltage reference to VSS, TA=0 to 70 o C ) PARAMETER SYMBOL MIN TYP. MAX UNIT Supply Voltage Vcc 4.5 5.0 5.5 V Ground Vss 0 0 0 V Input High Voltage VIH 2.4 - Vcc+1 V Input Low Voltage VIL -1.0 - 0.8 V DC AND OPERATING CHARACTERISTICS SYMBOL SPEED MIN MAX UNITS -5 - 990 mA -6 - 900 mA - 18 mA -5 - 990 mA -6 - 900 mA -5 - 990 mA -6 - 900 mA - 9 mA -5 - 990 mA -6 - 900 mA Il(L) -40 45 µA IO(L) -5 5 µA ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 VOH 2.4 - V VOL - 0.4 V ICC1 : Operating Current * (/RAS , /CAS , Address cycling @t RC=min.) URL:www.hbe.co.kr REV.1.0(August.2002) 3 HANBit Electronics Co.,Ltd. HANBit HMD1M36M3EG ICC2 : Standby Current ( /RAS=/CAS=VIH ) ICC3 : /RAS Only Refresh Current * ( /CAS=VIH, /RAS, Address cycling @tRC=min ) ICC4 : Fast Page Mode Current * (/RAS=VIL, /CAS, Address cycling @tPC=min ) ICC5 : Standby Current (/RAS=/CAS=Vcc-0.2V ) ICC6 : /CAS-Before-/RAS Refresh Current * (/RAS and /CAS cycling @t RC=min ) IIL : Input Leakage Current (Any input 0V ≤ VIN ≤ 6.5V, all other pins not under test = 0V) IOL : Output Leakage Current (Data out is disabled, 0V ≤ VOUT ≤ 5.5V VOH : Output High Voltage Level (IOH= -5mA ) VOL : Output Low Voltage Level (IOL = 4.2mA ) * NOTE: ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1 and ICC3, address cad be changed maximum once while /RAS=VIL. In ICC4, address can be changed maximum once within one page mode cycle. CAPACITANCE o ( TA=25 C, Vcc = 5V, f = 1Mz ) DESCRIPTION SYMBOL MIN MAX UNITS Input Capacitance (A0-A10) CIN1 - 65 pF Input Capacitance (/W) C IN2 - 80 pF Input Capacitance (/RAS0) CIN3 - 50 pF Input Capacitance (/CAS0-/CAS3) CIN4 - 40 pF Input/Output Capacitance (DQ0-31) CDQ1 - 20 pF AC CHARACTERISTICS o ( 0 C ≤ TA ≤ 70oC , Vcc = 5V±10%, See notes 1,2.) -5 STANDARD OPERATION -6 SYMBOL UNIT MIN MAX MAX Random read or write cycle time tRC Access time from /RAS tRAC 50 60 ns Access time from /CAS tCAC 13 15 ns Access time from column address tAA 25 30 ns /CAS to output in Low-Z tCLZ 3 Output buffer turn-off delay tOFF 3 13 3 15 ns Transition time (rise and fall) tT 2 50 2 50 ns /RAS precharge time tRP 30 /RAS pulse width tRAS 50 /RAS hold time tRSH 13 15 ns /CAS hold time tCSH 38 45 ns /CAS pulse width tCAS 8 10K 10 10K ns /RAS to /CAS delay time tRCD 20 37 20 45 ns /RAS to column address delay time tRAD 15 25 15 30 ns URL:www.hbe.co.kr REV.1.0(August.2002) 4 90 MIN 110 ns 3 ns 40 10K 60 ns 10K ns HANBit Electronics Co.,Ltd. HANBit HMD1M36M3EG /CAS to /RAS precharge time tCRP 5 5 ns Row address set-up time tASR 0 0 ns Row address hold time tRAH 10 10 ns Column address set-up time tASC 0 0 ns Column address hold time tCAH 8 10 ns Column Address to /RAS lead time tRAL 25 30 ns Read command set-up time tRCS 0 0 ns Read command hold referenced to /CAS tRCH 0 0 ns Read command hold referenced to /RAS tRRH 0 0 ns Write command hold time tWCH 10 10 ns Write command hold referenced to /RAS tWCR 50 50 ns Write command pulse width tWP 10 10 ns Write command to /RAS lead time tRWL 13 15 ns Write command to /CAS lead time tCWL 8 10 ns Data-in set-up time tDS 0 0 ns Data-in hold time tDH 8 10 ns Data-in hold referenced to /RAS tDHR 50 50 ns Refresh period tREF Write command set-up time tWCS 0 0 ns /CAS setup time (C-B-R refresh) tCSR 5 5 ns /CAS hold time (C-B-R refresh) tCHR 10 10 ns /RAS precharge to /CAS hold time tRPC 5 5 ns Access time from /CAS precharge tCPA Fast page mode cycle time tPC 40 40 ns /CAS precharge time (Fast page) tCP 8 10 ns /RAS pulse width (Fast page ) tRASP 50 /W to /RAS precharge time (C-B-R refresh) tWRP 10 10 ns /W to /RAS hold time (C-B-R refresh) tWRH 10 10 ns /CAS precharge(C-B-R counter test) tCPT 20 20 ns 64 64 30 200K 35 60 200K ns ns ns NOTES 1.An initial pause of 200µs is required after power-up followed by any 8 /RAS-only or /CAS-before-/RAS refresh cycles before proper device operation is achieved. 2.VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs. 3.Measured with a load equivalent to 2TTL loads and 100pF 4.Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by t CAC. 5.Assumes that tRCD ≥ tRCD(max) 6. tAR, tWCR, tDHR are referenced to tRAD(max) URL:www.hbe.co.kr REV.1.0(August.2002) 5 HANBit Electronics Co.,Ltd. HANBit HMD1M36M3EG 7.This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V OH or VOL. 8. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameter. They are included in the data sheet as electrical characteristic only. If t WCS ≥ tWCS(min) the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle. 9. Either tRCH or tRRH must be satisfied for a read cycle. 10. These parameters are referenced to the /CAS leading edge in early write cycles and to the /W leading edge in readwrite cycles. 11. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only. If tRAD is greater than the specified tRAD(max) limit. then access time is controlled by tAA. PACKAGING INFORMATION 107.95 mm 101.19 mm 3.18 ±0.51 R1.57 mm 3.38 mm 18.52 10.16 mm 6.35 mm R1.57±10 mm 6.35 mm 2.03 6.35 95.25 mm 5.08 MAX 2.54 mm 0.25 mm MAX MIN Gold : 1.04±0.10 mm Solder:0.914±0.10mm 1.27 1.29±0.08 mm ORDERING INFORMATION Part Number Density Org. Package HMD1M36M3EG-5 1MByte X36 72 Pin-DIMM HMD1M36M3EG-6 1MByte x 36 72 Pin-DIMM URL:www.hbe.co.kr REV.1.0(August.2002) 6 Component Vcc MODE SPEED 3EA 5V FP 60ns 3EA 5V FP 70ns Number HANBit Electronics Co.,Ltd. HANBit URL:www.hbe.co.kr REV.1.0(August.2002) HMD1M36M3EG 7 HANBit Electronics Co.,Ltd.