HANBit HMD8M32M4G 32Mbyte(8Mx32) 72-pin SIMM, FP Mode, 4K Ref. 5V Part No. HMD8M32M4, HMD8M32M4G GENERAL DESCRIPTION The HMD8M32M4 is a 8M x 32bit dynamic RAM high density memory module. The module consists of four CMOS 4M x 16 bit DRAMs in 50-pin TSOP packages mounted on a 72-pin, double-sided, FR-4-printed circuit board. A 0.1uF or 0.22uF decoupling capacitor is mounted on the printed circuit board for each DRAM components. The module is a single In-line memory module with edge connections and is intended for mounting in to 72-pin edge connector sockets. All module components may be powered from a single 5V DC power supply and all inputs and outputs are TTL-compatible. FEATURES PIN ASSIGNMENT w Part Identification HMD8M32M4----4K Cycles/64ms Ref, Solder HMD8M32M4G- 4K Cycles/64ms Ref, Gold PIN SYMBOL PIN SYMBOL PIN SYMBOL 1 Vss 25 DQ22 49 DQ8 w Access times : 50, 60ns 2 DQ0 26 DQ7 50 DQ24 w High-density 32MByte design 3 DQ16 27 DQ23 51 DQ9 w Single +5V ±0.5V power supply 4 DQ1 28 A7 52 DQ25 w JEDEC Standard pinout 5 DQ17 29 A11 53 DQ10 w Fast Page mode operation 6 DQ2 30 Vcc 54 DQ26 w TTL compatible inputs and outputs 7 DQ18 31 A8 55 DQ11 w FR4-PCB design 8 DQ3 32 A9 56 DQ27 9 DQ19 33 NC 57 DQ12 10 Vcc 34 NC 58 DQ28 11 NC 35 NC 59 Vcc A0 36 NC 60 DQ29 OPTIONS MARKING w Timing 50ns access -5 12 60ns access -6 13 A1 37 NC 61 DQ13 14 A2 38 NC 62 DQ30 15 A3 39 Vss 63 DQ14 16 A4 40 /CAS0 64 DQ31 17 A5 41 /CAS2 65 DQ15 18 A6 42 /CAS3 66 NC 19 A10 43 /CAS1 67 PD1 w Packages 72-pin SIMM M PRESENCE DETECT PINS Pin 50ns 60ns PD1 NC NC 20 DQ4 44 /RAS0 68 PD2 PD2 Vss Vss 21 DQ20 45 /RAS1 69 PD3 22 DQ5 46 NC 70 PD4 23 DQ21 47 /WE 71 NC 24 DQ6 48 NC 72 Vss PD3 Vss NC PD4 Vss NC PERFORMANCE RANGE Speed tRAC tCAC tRC 5 50ns 13ns 90ns 6 60ns 15ns 110ns URL:www.hbe.co.kr REV.1.0 (August.2002) -1- HANBit Electronics Co.,Ltd. HANBit HMD8M32M4G FUNCTIONAL BLOCK DIAGRAM U1 /RAS0 /RAS /CAS0 /LCAS /CAS1 /UCAS /OE /W DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U4 DQ0-15 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 A0-A11 DQ15 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U3 /RAS /RAS0 /LCAS /CAS2 /UCAS /OE /W DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 /RAS1 /LCAS /CAS0 /UCAS /CAS1 /OE /W A0-A11 U6 DQ16-31 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 A0-A11 DQ15 /CAS3 /RAS /RAS /RAS1 /LCAS /CAS2 /UCAS /CAS3 /OE /W A0-A11 /WE A0-A11 Vcc Vss URL:www.hbe.co.kr REV.1.0 (August.2002) 0.1uFor0.22uFCapacitor foreachDRAM -2- To all DRAMs HANBit Electronics Co.,Ltd. HANBit HMD8M32M4G ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING VIN ,OUT -1V to 7.0V Voltage on Vcc Supply Relative to Vss Vcc -1V to 7.0V Power Dissipation PD 4W TSTG -55oC to 150oC Voltage on Any Pin Relative to Vss Storage Temperature Short Circuit Output Current IOS 50mA w Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED DC OPERATING CONDITIONS ( Voltage reference to VSS, TA=0 to 70 o C ) PARAMETER SYMBOL MIN TYP. MAX UNIT Supply Voltage Vcc 4.5 5.0 5.5 V Ground Vss 0 0 0 V Input High Voltage VIH 2.4 - Vcc+1 V Input Low Voltage VIL -1.0 - 0.8 V DC AND OPERATING CHARACTERISTICS SYMBOL SPEED MIN MAX UNITS -5 - 736 Ma 656 Ma ICC1 -6 ICC2 Don't care - 32 Ma -5 - 736 MA -6 - 656 MA -5 - 656 MA -6 - 576 MA Don't care - 16 MA -5 - 736 MA -6 - 656 MA Il(L) -20 80 µA IO(L) -20 10 µA VOH 2.4 - V VOL - 0.4 V ICC3 ICC4 ICC5 ICC6 ICC1 : Operating Current * (/RAS , /CAS , Address cycling @t RC=min.) ICC2 : Standby Current ( /RAS=/CAS=VIH ) ICC3 : /RAS Only Refresh Current * ( /CAS=V IH, /RAS, Address cycling @tRC=min ) URL:www.hbe.co.kr REV.1.0 (August.2002) -3- HANBit Electronics Co.,Ltd. HANBit HMD8M32M4G ICC4 : Fast Page Mode Current * (/RAS=VIL, /CAS, Address cycling @tPC=min ) ICC5 : Standby Current (/RAS=/CAS=Vcc-0.2V ) ICC6 : /CAS-Before-/RAS Refresh Current * (/RAS and /CAS cycling @t RC=min ) IIL : Input Leakage Current (Any input 0V ≤ VIN ≤ 6.5V, all other pins not under test = 0V) IOL : Output Leakage Current (Data out is disabled, 0V ≤ VOUT ≤ 5.5V VOH : Output High Voltage Level (IOH= -5mA ) VOL : Output Low Voltage Level (IOL = 4.2mA ) * NOTE: ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1 and ICC3, address cad be changed maximum once while /RAS=VIL. In ICC4, address can be changed maximum once within one page mode cycle. CAPACITANCE o ( TA=25 C, Vcc = 5V, f = 1Mz ) DESCRIPTION SYMBOL MIN MAX UNITS Input Capacitance (A0-A11) CIN1 - 100 PF Input Capacitance (/W) C IN2 - 130 PF Input Capacitance (/RAS0) CIN3 - 40 pF Input Capacitance (/CAS0-/CAS3) CIN4 - 30 pF Input/Output Capacitance (DQ0-31) CDQ1 - 20 pF AC CHARACTERISTICS o ( 0 C ≤ TA ≤ 70oC , Vcc = 5V±10%, See notes 1,2.) -5 STANDARD OPERATION -6 SYMBOL UNIT MIN MAX MAX Random read or write cycle time tRC Access time from /RAS tRAC 50 60 ns Access time from /CAS tCAC 13 15 ns Access time from column address tAA 25 30 ns /CAS to output in Low-Z tCLZ 0 Output buffer turn-off delay tOFF 0 13 0 13 ns Transition time (rise and fall) tT 3 50 3 50 ns /RAS precharge time tRP 30 /RAS pulse width tRAS 50 /RAS hold time tRSH 13 15 ns /CAS hold time tCSH 50 60 ns /CAS pulse width tCAS 13 10K 15 10K ns /RAS to /CAS delay time tRCD 20 37 20 45 ns /RAS to column address delay time tRAD 15 25 15 30 ns /CAS to /RAS precharge time tCRP 5 5 ns Row address set-up time tASR 0 0 ns Row address hold time tRAH 10 10 ns URL:www.hbe.co.kr REV.1.0 (August.2002) 90 MIN -4- 110 ns 0 ns 40 10K 60 ns 10K ns HANBit Electronics Co.,Ltd. HANBit HMD8M32M4G Column address set-up time tASC 0 0 ns Column address hold time tCAH 10 10 ns Column Address to /RAS lead time tRAL 25 30 ns Read command set-up time tRCS 0 0 ns Read command hold referenced to /CAS tRCH 0 0 ns Read command hold referenced to /RAS tRRH 0 0 Write command hold time tWCH 10 10 ns Write command pulse width tWP 10 10 ns Write command to /RAS lead time tRWL 15 15 ns Write command to /CAS lead time tCWL 13 15 ns Data-in set-up time tDS 0 0 ns Data-in hold time tDH 10 15 ns Refresh period tREF Write command set-up time tWCS 0 0 ns /CAS setup time (C-B-R refresh) tCSR 5 5 ns /CAS hold time (C-B-R refresh) tCHR 10 10 ns /RAS precharge to /CAS hold time tRPC 5 5 ns Access time from /CAS precharge tCPA Fast page mode cycle time tPC 35 45 ns /CAS precharge time (Fast page) tCP 10 10 ns /RAS pulse width (Fast page ) tRASP 50 /W to /RAS precharge time (C-B-R refresh) tWRP 10 10 ns /W to /RAS hold time (C-B-R refresh) tWRH 10 10 ns /CAS precharge(C-B-R counter test) tCPT 20 30 ns 64 64 30 200K ns 35 60 200K ns ns ns NOTES 1.An initial pause of 200µs is required after power-up followed by any 8 /RAS-only or /CAS-before-/RAS refresh cycles before proper device operation is achieved. 2.VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs. 3.Measured with a load equivalent to 1TTL loads and 100pF 4.Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. 5.Assumes that tRCD ≥ tRCD(max) 6. tAR, tWCR, tDHR are referenced to tRAD(max) 7.This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V OH or VOL. 8. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameter. They are included in the data sheet as electrical characteristic only. If t WCS ≥ tWCS(min) the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle. 9. Either tRCH or tRRH must be satisfied for a read cycle. 10. These parameters are referenced to the /CAS leading edge in early write cycles and to the /W leading edge in readwrite cycles. 11. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only. If tRAD is greater than the specified tRAD(max) limit. then access time is controlled by tAA. URL:www.hbe.co.kr REV.1.0 (August.2002) -5- HANBit Electronics Co.,Ltd. HANBit HMD8M32M4G TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE /RAS tRC tRAS VIH- tRP VILtCRP /UCAS,/LCAS A tCSH tRCD VIL- tCAS tRAD tASR tRAH tCAH tASC VIHVIL- ROW ADDRESS tRAL COLUMN ADDRESS tRCS VIH- tOFF tOEZ tAA VIH- DQ0-DQ15 tRCH tRRH /W V IL- /OE tCRP tRSH VIH- tOEA VIL- tCAC tCLZ tRAC VOHVOL- tOEZ DATA-OUT OPEN TIMING WAVEFORM OF WRITE CYCLE (EARLY WRITE) NOTE : Dout = Open tRC /RAS VIH- tRP tRAS VILtCRP tCSH tRCD /UCAS,/LCAS VIL- tCAS tRAD tASR tRAH VIHA V IL- /W VIHVIL- tCRP tRSH VIH- ROW ADDRESS tCAH tASC tRAL COLUMN ADDRESS tCWL tRWL tWCS tWCH tWP /OE VIHVILtDS DQ0-DQ15 VOHVOL- URL:www.hbe.co.kr REV.1.0 (August.2002) tDH DATA-IN -6- HANBit Electronics Co.,Ltd. HANBit HMD8M32M4G PACKAGING INFORMATION 107.95 mm 101.19 mm R1.57 mm 3.38 mm R3.18±0.51m 18.52mm 10.16 mm 6.35 mm R1.57±10 mm 6.35 mm 2.03mm 6.35mm 95.25 mm 7.68mm MAX 2.54 mm 0.25 mm MAX MIN Gold : 1.04±0.10 mm Solder:0.914±0.10mm 1.27mm 1.29±0.08 mm ORDERING INFORMATION Part Number Density Org. Package Vcc SPEED HMD8M32M4G-5 32MByte 8MX 32bit 72 Pin-SIMM 5.0V 50ns HMD8M32M4G-6 32MByte 8MX 32bit 72 Pin-SIMM 5.0V 60ns URL:www.hbe.co.kr REV.1.0 (August.2002) -7- HANBit Electronics Co.,Ltd.