HANBIT HMN1288DV-85I

HANBit
HMN1288DV
Non-Volatile SRAM Module 1Mbit (128K x 8-Bit), 32Pin-DIP, 3.3V
Part No. HMN1288DV
GENERAL DESCRIPTION
The HMN1288DV Nonvolatile SRAM is a 1,048,576-bit static RAM organized as 131,072 bytes by 8 bits.
The HMN1288DV has a self-contained lithium energy source provide reliable non -volatility coupled with the unlimited
write cycles of standard SRAM and integral control circuitry, which constantly monitors the single 3.3V, supply for an outof-tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on to sustain
the memory until after VCC returns valid and write protection is unconditionally enabled to prevent garbled data. In addition
the SRAM is unconditionally write-protected to prevent an inadvertent write operation. At this time the integral energy
source is switched on to sustain the memory until after V CC returns valid.
The HMN1288DV uses extremely low standby current CMOS SRAM ’s, coupled with small lithium coin cells to provide
non-volatility without long write-cycle times and the write-cycle limitations associated with EEPROM.
FEATURES
w Access time : 70, 85, 120, 150 ns
PIN ASSIGNMENT
w High-density design : 1Mbit Design
w Battery internally isolated until power is applied
NC
w Industry-standard 32-pin 128K x 8 pinout
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
w Unlimited write cycles
w Data retention in the absence of V CC
w 10-years minimum data retention in absence of power
w Automatic write-protection during power-up/power-down
cycles
w Data is automatically protected during power loss
w Conventional SRAM operation; unlimited write cycles
OPTIONS
MARKING
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
NC
/WE
A13
A8
A9
A11
/OE
A10
/CE
DQ7
DQ6
DQ5
DQ4
DQ3
32-pin Encapsulated Package
w Timing
70 ns
- 70
85 ns
- 85
120 ns
-120
150 ns
-150
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HMN1288DV
FUNCTIONAL DESCRIPTION
The HMN1288DV executes a read cycle whenever /WE is inactive(high) and /CE is active(low). The address specified by
the address inputs(A 0-A16) defines which of the 131,072 bytes of data is accessed. Valid data will be available to the eight
data output drivers within tACC (access time) after the last address input signal is stable.
When power is valid, the HMN1288DV operates as a standard CMOS SRAM. During power -down and power-up cycles,
the HMN1288DV acts as a nonvolatile memory, automatically protectin g and preserving the memory contents.
The HMN1288DV is in the write mode whenever the /WE and /CE signals are in the active (low) state after address inputs
are stable. The later occurring falling edge of /CE or /WE will determine the start of the write cycle. The write cycle is
terminated by the earlier rising edge of /CE or /WE. All address inputs must be kept valid throughout the write cycle. /WE
must return to the high state for a minimum recovery time (t WR) before another cycle can be initiated. The /OE control
signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output bus been enabled
(/CE and /OE active) then /WE will disable the outputs in t ODW from its falling edge.
The HMN1288DV provides full functional capability for Vcc greater than 3.0V and write protects by 2.8 V nominal. Powerdown/power-up control circuitry constantly monitors the V CC supply for a power-fail-detect threshold VPFD. When VCC falls
below the V PFD threshold, the SRAM automatically write-protects the data. All inputs to the RAM become “don’t care” and
all outputs are high impedance. As Vcc falls below approximately 3 V, the power switching circuit connects the lithium
energy soure to RAM to retain data. During power-up, when Vcc rises above approximately 3.0 volts, the power switching
circuit connects external Vcc to the RAM and disconnects the lithium energy source. Normal RAM operation can resume
after Vcc exceeds 4.5 volts.
BLOCK DIAGRAM
/OE
PIN DESCRIPTION
/WE
A0-A16 : Address Input
A0-A16
128K x 8
SRAM
Block
DQ0-DQ7
/CE : Chip Enable
Vss : Ground
Power
/CE
/CE CON
Power – Fail
Control
DQ0-DQ7 : Data In / Data Out
VCC
/WE : Write Enable
/OE : Output Enable
Lithium
Cell
VCC : Power (+3.3V)
NC : No Connection
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HMN1288DV
TRUTH TABLE
MODE
/OE
/CE
/WE
I/O OPERATION
POWER
Not selected
X
H
X
High Z
Standby
Output disable
H
L
H
High Z
Active
Read
L
L
H
DOUT
Active
Write
X
L
L
DIN
Active
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
VCC
-0.5V to Vcc+0.5
VT
-0.3V to 4.6V
Operating temperature
TOPR
0 to 70°C
Storage temperature
TSTG
-65°C to 150°C
TSOLDER
260°C
DC voltage applied on V CC relative to V SS
DC Voltage applied on any pin excluding V CC relative
to VSS
Soldering temperature
CONDITIONS
VT≤ VCC+0.3
For 10 second
NOTE: Permanent device damage may occur if Absolute Maximum Ratings are exceeded.
Functional operation should be restricted to the Recommended DC Operating Condit ions detailed in this data sheet.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS ( TA= TOPR )
PARAMETER
SYMBOL
MIN
TYPICAL
MAX
Supply Voltage
VCC
4.5V
5.0V
5.5V
Ground
VSS
0
0
0
Input high voltage
VIH
2.2
-
Vcc+0.3V
Input low voltage
VIL
-0.3
-
0.8V
NOTE: Typical values indicate operation at TA = 25℃
CAPACITANCE (TA=25℃ , f=1MHz, VCC=5.0V)
DESCRIPTION
Input Capacitance
Input/Output Capacitance
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CONDITIONS
SYMBOL
MAX
MIN
UNIT
Input voltage = 0V
CIN
10
-
pF
Output voltage = 0V
CI/O
10
-
pF
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HMN1288DV
DC ELECTRICAL CHARACTERISTICS (TA= TOPR, VCCmin ≤ VCC ≤ VCCmax )
PARAMETER
CONDITIONS
Input Leakage Current
VIN=VSS to VCC
/CE=VIH or /OE=VIH
Output Leakage Current
or /WE=VIL
SYMBOL
MIN
TYP.
MAX
UNIT
ILI
-
-
± 3.0
µA
ILO
-
-
± 3.0
µA
Output high voltage
IOH=-1.0mA
VOH
2.4
-
-
V
Output low voltage
IOL= 2.0mA
VOL
-
-
0.4
V
VPFD
2.8
2.9
3.0
V
ISB
-
-
0.6
㎃
ISB1
-
-
30
µA
ICC
-
12
㎃
VSO
-
-
V
Threshold
Power-fail Deselect Voltage
Select
Voltage
(THS = VSS )
Standby supply current
/CE=2.2v
/CE≥ VCC-0.2V,
0V≤ VIN≤ 0.2V,
Standby supply current
or VIN≥ VCC-0.2V
Operating
Power
supply
current
/CE=VIL, II/O=0㎃ ,
VIN = VIL or V IH, Read
Supply switch-over voltage
2.5
NOTE: Typical values indicate operation at TA = 25℃ .
CHARACTERISTICS (Test Conditions)
PARAMETER
Input pulse levels
0 to 3V
Input rise and fall times
5 ns
Input and output timing
1.5V
reference levels
Output load
(including scope and jig)
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+5V
VALUE
1.9KΩ
DOUT
1KΩ
( unless otherwise specified)
Figure 1.
Output Load A
See Figures 1and 2
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+5V
1.9KΩ
DOUT
100㎊
1KΩ
5㎊
Figure 2.
Output Load B
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HANBit
HMN1288DV
READ CYCLE (TA= TOPR, VCCmin ≤ VCC≤ VCCmax )
PARAMETER
SYMBOL
Read Cycle Time
tRC
-70
CONDITIONS
-85
-120
-150
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
70
-
85
-
120
-
150
-
ns
Address Access Time
tACC
Output load A
-
70
-
85
-
120
-
150
ns
Chip enable access time
tACE
Output load A
-
70
-
85
-
120
-
150
ns
Output enable to Output valid
tOE
Output load A
-
35
-
45
-
60
-
70
ns
Chip enable to output in low Z
tCLZ
Output load B
5
-
5
-
5
-
10
-
ns
Output enable to output in low Z
tOLZ
Output load B
5
-
0
-
0
-
5
-
ns
Chip disable to output in high Z
tCHZ
Output load B
0
25
0
35
0
45
0
60
ns
Output disable to output high Z
tOHZ
Output load B
0
25
0
25
0
35
0
50
ns
Output hold from address change
tOH
Output load A
10
-
10
-
10
-
10
-
ns
WRITE CYCLE (TA= TOPR, Vccmin ≤ Vcc ≤ Vccmax )
PARAMETER
SYMBOL
-70
CONDITIONS
MIN
-85
MAX
MIN
-120
MAX
-150
UNI
MIN
MAX
Min
Max
T
Write Cycle Time
tWC
70
-
85
-
120
-
150
-
ns
Chip enable to end of write
tCW
Note 1
65
-
75
-
100
-
100
-
ns
Address setup time
tAS
Note 2
0
-
0
-
0
-
0
-
ns
Address valid to end of write
tAW
Note 1
65
-
75
-
100
-
90
-
ns
Write pulse width
tWP
Note 1
55
-
65
-
85
-
90
-
ns
Write recovery time (write cycle 1)
tWR1
Note 3
5
-
5
-
5
-
5
-
ns
Write recovery time (write cycle 2)
tWR2
Note 3
15
-
15
-
15
-
15
-
ns
Data valid to end of write
tDW
30
-
35
-
45
-
50
-
ns
Data hold time (write cycle 1)
tDH1
Note 4
0
-
0
-
0
-
0
-
ns
Data hold time (write cycle 2)
tDH2
Note 4
10
-
10
-
10
-
0
-
ns
Write enabled to output in high Z
tWZ
Note 5
0
25
0
30
0
40
0
50
ns
Output active from end of write
tOW
Note 5
5
-
0
-
0
-
5
-
ns
NOTE: 1. A write ends at the earlier transition of /CE going high and /WE going high.
2. A write occurs during the over lap of allow /CE and a low /WE. A write begins at the later transition of /CE
going low and /WE going low.
3. Either t WR1 or tWR2 must be met.
4. Either t DH1 or tDH2 must be met.
5. If /CE goes low simultaneously w ith /WE going low or after /WE going low, the outputs remain in high impedance state.
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HMN1288DV
POWER-DOWN/POWER-UP CYCLE
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP.
MAX
UNIT
VPFD(max) to VPFD(min) VCC Fail Time
tF
300
-
-
µs
VPFD(max) to VSS VCC Fail Time
tFB
150
-
-
µs
VPFD(max) to VPFD(min) VCC Rise Time
tR
10
-
-
µs
250
µs
Delay after Vcc slews down
Write Protect Time
tWPT
past VPFD before SRAM is
40
Write-protected.
Chip Enable Recovery
tCER
40
-
120
ms
VSS to VPFD (min) VCC Rise Time
tRB
1
-
-
µs
TIMING WAVEFORM
- READ CYCLE NO.1 (Address Access)*
1,2
tRC
Address
tACC
tOH
Previous Data Valid
DOUT
Data Valid
- READ CYCLE NO.2 (/CE Access)*1,3,4
tRC
CE
tACE
tCHZ
tCLZ
DOUT
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High-Z
High-Z
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HMN1288DV
- READ CYCLE NO.3 (/OE Access)
*1,5
tRC
Address
tACC
/OE
tOE
DOUT
NOTES:
tOHZ
tOLZ
Data Valid
High-Z
High-Z
1. /WE is held high for a read cycle.
2. Device is continuously sele cted: /CE = /OE =V IL.
3. Address is valid prior to or coincident with /CE transition low.
4. /OE = V IL.
5. Device is continuously selected: /CE = V IL
- WRITE
*1,2,3
CYCLE NO.1 (/WE-CONTROLLED)
tWC
Address
tAW
tWR1
tCW
/CE
tAS
tWP
/WE
tDW
DIN
tDH1
Data-in Valid
tWZ
DOUT
High-Z
Data Undefined (1)
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tOW
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HMN1288DV
*1,2,3,4,5
- WRITE CYCLE NO.2 (/CE-Controlled)
tWC
Address
tAW
tAS
tWR2
tCW
/CE
tWP
/WE
tDH2
tDW
Data-in
DIN
tWZ
DOUT
Data
NOTE:
High-Z
Undefined
1. /CE or /WE must be high during address transition.
2. Because I/O may be active (/OE low) during this period, data input signals of opposite
polarity to the outputs must not be applied.
3. If /OE is high, the I/O pins remain in a state of high impedance.
4. Either t WR1 or tWR2 must be met.
5. Either t DH1 or tDH2 must be met.
- POWER-DOWN/POWER-UP
TIMING
tPF
VCC
4.75
VPFD
VPFD
4.25
VSO
VSO
tFS
tWPT
tPU
tCER
tDR
/CE
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HMN1288DV
PACKAGE DIMENSION
Dimension
Min
Max
A
1.680
1.680
B
0.720
0.740
C
0.365
0.375
D
0.015
0.025
E
0.008
0.013
F
0.590
0.630
G
0.015
0.021
H
0.090
0.110
I
0.080
0.110
J
0.120
0.160
J
A
I
H
G
B
C
D
E
F
All dimensions are in inches.
ORDERING INFORMATION
H M N 1288 D V - 70 I
Operating Temp. : Blank = Commercial (0 to 70 °C )
I = Industrial (-40 to 85°C)
Speed options : 70 = 70 ns , 85 = 85 ns
120 = 120 ns, 150 = 150 ns
Operating Voltage : 3.3V
Dip type package
Device : 128K x 8 bit
Nonvolatile SRAM
HANBit Memory Module
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