HM5116405 Series HM5117405 Series 16 M EDO DRAM (4-Mword 4-bit) 4 k Refresh/2 k Refresh ADE-203-633D (Z) Rev. 4.0 Nov. 1997 Description The Hitachi HM5116405 Series, HM5117405 Series are CMOS dynamic RAMs organized 4,194,304-word 4-bit. They employ the most advanced CMOS technology for high performance and low power. The HM5116405 Series, HM5117405 Series offer Extended Data Out (EDO) Page Mode as a high speed access mode. They have package variations of standard 26-pin plastic SOJ and standard 26-pin plastic TSOP II. Features Single 5 V ( 10%) Access time: 50 ns/60 ns/70 ns (max) Power dissipation Active mode : 495 mW/440 mW/385 mW (max) (HM5116405 Series) : 550 mW/495 mW/440 mW (max) (HM5117405 Series) Standby mode : 11 mW (max) : 0.83 mW (max) (L-version) EDO page mode capability Long refresh period 4096 refresh cycles : 64 ms (HM5116405 Series) : 128 ms (L-version) 2048 refresh cycles : 32 ms (HM5117405 Series) : 128 ms (L-version) 3 variations of refresh -only refresh -beforeHidden refresh refresh HM5116405 Series, HM5117405 Series Battery backup operation (L-version) Test function 16-bit parallel test mode Ordering Information Type No. Access time Package HM5116405S-5 HM5116405S-6 HM5116405S-7 50 ns 60 ns 70 ns 300-mil 26-pin plastic SOJ (CP-26/24DB) HM5116405LS-5 HM5116405LS-6 HM5116405LS-7 50 ns 60 ns 70 ns HM5117405S-5 HM5117405S-6 HM5117405S-7 50 ns 60 ns 70 ns HM5117405LS-5 HM5117405LS-6 HM5117405LS-7 50 ns 60 ns 70 ns HM5116405TS-5 HM5116405TS-6 HM5116405TS-7 50 ns 60 ns 70 ns HM5116405LTS-5 HM5116405LTS-6 HM5116405LTS-7 50 ns 60 ns 70 ns HM5117405TS-5 HM5117405TS-6 HM5117405TS-7 50 ns 60 ns 70 ns HM5117405LTS-5 HM5117405LTS-6 HM5117405LTS-7 50 ns 60 ns 70 ns 2 300-mil 26-pin plastic TSOP II (TTP-26/24DA) HM5116405 Series, HM5117405 Series Pin Arrangement HM5116405S/LS Series HM5116405TS/LTS Series VCC 1 26 VSS VCC 1 26 VSS I/O1 2 25 I/O4 I/O1 2 25 I/O4 I/O2 3 24 I/O3 I/O2 3 24 I/O3 4 23 4 23 5 22 5 22 A11 6 21 A9 A11 6 21 A9 A10 8 19 A8 A10 8 19 A8 A0 9 18 A7 A0 9 18 A7 A1 10 17 A6 A1 10 17 A6 A2 11 16 A5 A2 11 16 A5 A3 12 15 A4 A3 12 15 A4 13 14 VSS 13 14 VSS VCC VCC (Top view) (Top view) Pin Description Pin name Function A0 to A11 Address input I/O1 to I/O4 Row/Refresh address A0 to A11 Column address A0 to A9 Data input/Data output Row address strobe Column address strobe Write enable Output enable VCC Power supply VSS Ground 3 HM5116405 Series, HM5117405 Series Pin Arrangement HM5117405S/LS Series VCC HM5117405TS/LTS Series 1 26 VSS I/O1 2 25 I/O4 I/O2 3 24 I/O3 4 1 26 VSS I/O1 2 25 I/O4 I/O2 3 24 I/O3 23 4 23 5 22 5 22 NC 6 21 A9 NC 6 21 A9 A10 8 19 A8 A10 8 19 A8 A0 9 18 A7 A0 9 18 A7 A1 10 17 A6 A1 10 17 A6 A2 11 16 A5 A2 11 16 A5 A3 12 15 A4 A3 12 15 A4 13 14 VSS 13 14 VSS VCC VCC VCC (Top view) (Top view) Pin Description Pin name Function A0 to A10 Address input I/O1 to I/O4 Row/Refresh address A0 to A10 Column address A0 to A10 Data input/Data output Row address strobe Column address strobe Write enable Output enable VCC Power supply VSS Ground NC No connection 4 HM5116405 Series, HM5117405 Series Block Diagram (HM5116405 Series) Timing and control A0 Column decoder A1 to • • • Column 4M array address buffers A9 • • • Row address Row decoder 4M array I/O buffers 4M array I/O1 to I/O4 buffers A10 4M array A11 5 HM5116405 Series, HM5117405 Series Block Diagram (HM5117405 Series) Timing and control A0 Column decoder A1 to • • • Column 4M array address buffers A10 • • • Row address Row decoder 4M array I/O buffers 4M array buffers 4M array 6 I/O1 to I/O4 HM5116405 Series, HM5117405 Series Absolute Maximum Ratings Parameter Symbol Value Unit Voltage on any pin relative to V SS VT –1.0 to +7.0 V Supply voltage relative to VSS VCC –1.0 to +7.0 V Short circuit output current Iout 50 mA Power dissipation PT 1.0 W Operating temperature Topr 0 to +70 C Storage temperature Tstg –55 to +125 C Recommended DC Operating Conditions (Ta = 0 to +70 C) Parameter Symbol Min Typ Max Unit Note Supply voltage VCC 4.5 5.0 5.5 V 1 Input high voltage VIH 2.4 — 6.5 V 1 Input low voltage VIL –1.0 — 0.8 V 1 Note: 1. All voltage referred to VSS. 7 HM5116405 Series, HM5117405 Series DC Characteristics (Ta = 0 to +70 C, V CC = 5 V 10%, VSS = 0 V) (HM5116405 Series) HM5116405 -5 -6 -7 Parameter Symbol Min Max Min Max Min Max Unit Test conditions Operating current*1 , * 2 I CC1 — 90 — 80 — 70 mA t RC = min Standby current I CC2 — 2 — 2 — 2 mA TTL interface , = VIH Dout = High-Z — 1 — 1 — 1 mA CMOS interface , VCC – 0.2 V Dout = High-Z I CC2 — 150 — 150 A CMOS interface , VCC – 0.2 V Dout = High-Z I CC3 — 90 — 80 — 70 mA t RC = min I CC5 — 5 — 5 — 5 mA = VIH = VIL Dout = enable I CC6 — 90 — 80 — 70 mA t RC = min EDO page mode current*1, * 3 I CC7 — 80 — 70 — 65 mA t HPC = min Battery backup current I CC10 — 350 — 350 A CMOS interface Dout = High-Z, CBR refresh: tRC = 31.3 s t RAS 0.3 s Input leakage current I LI –10 10 –10 10 –10 10 A 0V Output leakage current I LO –10 10 –10 10 –10 10 A 0 V Vin 7 V Dout = disable Output high voltage VOH 2.4 VCC 2.4 VCC 2.4 VCC V High Iout = –2 mA Output low voltage VOL 0 0.4 0.4 0.4 V Low Iout = 2 mA Standby current (L-version) -only refresh current*2 1 Standby current* -beforecurrent refresh 0 150 — 350 — 0 Vin 7V Notes : 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while = VIL. 3. Address can be changed once or less while = VIH. 8 HM5116405 Series, HM5117405 Series DC Characteristics (Ta = 0 to +70 C, V CC = 5 V 10%, VSS = 0 V) (HM5117405 Series) HM5117405 -5 Parameter -6 -7 Symbol Min Max Min Max Min Max Unit Test conditions Operating current* , * 2 I CC1 — 100 — Standby current I CC2 — 2 — 1 I CC2 — 150 — 150 — I CC3 — 100 — 90 I CC5 — 5 5 I CC6 — 100 — EDO page mode current*1, * 3 I CC7 — 90 — Battery backup current I CC10 — 350 — Input leakage current I LI –10 10 –10 10 Output leakage current I LO –10 10 –10 10 Output high voltage VOH 2.4 VCC 2.4 VCC 2.4 VCC V High Iout = –2 mA Output low voltage VOL 0 0.4 0.4 0.4 V Low Iout = 2 mA 1 Standby current (L-version) -only refresh current*2 Standby current*1 -beforecurrent refresh 90 — 80 mA t RC = min — 2 — 2 mA TTL interface , = VIH Dout = High-Z — 1 — 1 mA CMOS interface , VCC – 0.2 V Dout = High-Z 150 A CMOS interface , VCC – 0.2 V Dout = High-Z — 80 mA t RC = min — 5 mA = VIH = VIL Dout = enable 90 — 80 mA t RC = min 80 — 75 mA t HPC = min 350 A CMOS interface Dout = High-Z, CBR refresh: tRC = 62.5 s t RAS 0.3 s –10 10 A 0V –10 10 A 0 V Vin 7 V Dout = disable — 0 350 — 0 Vin 7V Notes : 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while = VIL. 3. Address can be changed once or less while = VIH. 9 HM5116405 Series, HM5117405 Series Capacitance (Ta = 25 C, V CC = 5 V 10%) Parameter Symbol Typ Max Unit Notes Input capacitance (Address) CI1 — 5 pF 1 Input capacitance (Clocks) CI2 — 7 pF 1 — 7 pF 1, 2 Output capacitance (Data-in, Data-out) CI/O Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. = VIH to disable Dout. 10 HM5116405 Series, HM5117405 Series AC Characteristics (Ta = 0 to +70 C, VCC = 5 V 10%, VSS = 0 V) *1, *2 , *18 Test Conditions Input rise and fall time: 2 ns Input levels: VIL = 0 V, V IH = 3 V Input timing reference levels: 0.8 V, 2.4 V Output timing reference levels: 0.8 V, 2.0 V Output load: 1 TTL gate + C L (100 pF) (Including scope and jig) Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters) HM5116405/HM5117405 -5 -6 -7 Parameter Symbol Min Max Min Max Min Max Unit Random read or write cycle time t RC 84 — 104 — 124 — ns precharge time t RP 30 — 40 — 50 — ns precharge time t CP 7 — 10 — 13 — ns pulse width t RAS 50 10000 60 pulse width 10000 70 Notes 10000 ns t CAS 7 10000 10 10000 13 10000 ns Row address setup time t ASR 0 — 0 — 0 — ns Row address hold time t RAH 7 — 10 — 10 — ns Column address setup time t ASC 0 — 0 — 0 — ns Column address hold time t CAH 7 — 10 — 13 — ns t RCD 11 37 14 45 14 52 ns 3 to column address delay time t RAD 9 25 12 30 12 35 ns 4 hold time t RSH 10 — 13 — 13 — ns hold time t CSH 35 — 40 — 45 — ns to delay time t CRP 5 — 5 — 5 — ns to Din delay time t OED 13 — 15 — 18 — ns 5 delay time from Din t DZO 0 — 0 — 0 — ns 6 t DZC 0 — 0 — 0 — ns 6 tT 2 50 2 50 2 50 ns 7 to precharge time delay time from Din Transition time (rise and fall) 11 HM5116405 Series, HM5117405 Series Read Cycle HM5116405/HM5117405 -5 -6 -7 Parameter Symbol Min Max Min Max Min Max Unit Notes Access time from t RAC — 50 — 60 — 70 ns 8, 9, 20 Access time from t CAC — 13 — 15 — 18 ns 9, 10, 17, 20 Access time from address t AA — 25 — 30 — 35 ns 9, 11, 17, 20 Access time from t OEA — 13 — 15 — 18 ns 9, 20 Read command setup time t RCS 0 — 0 — 0 — ns Read command hold time to t RCH 0 — 0 — 0 — ns Read command hold time from t RCHR 50 — 60 — 70 — ns Read command hold time to t RRH 0 — 0 — 0 — ns Column address to lead time t RAL 25 — 30 — 35 — ns Column address to lead time t CAL 15 — 18 — 23 — ns 12 12 t CLZ 0 — 0 — 0 — ns Output data hold time t OH 3 — 3 — 3 — ns Output data hold time from t OHO 3 — 3 — 3 — ns Output buffer turn-off time t OFF — 13 — 15 — 15 ns 13, 22 Output buffer turn-off to t OEZ — 13 — 15 — 15 ns 13 to Din delay time t CDD 13 — 15 — 18 — ns 5 Output data hold time from t OHR 3 — 3 — 3 — ns 22 Output buffer turn-off to t OFR — 13 — 15 — 15 ns 22 Output buffer turn-off to t WEZ — 13 — 15 — 15 ns t WED 13 — 15 — 18 — ns to Din delay time t RDD 13 — 15 — 18 — ns next t RNCD 50 — 60 — 70 — ns to output in low-Z to Din delay time 12 delay time 22 HM5116405 Series, HM5117405 Series Write Cycle HM5116405/HM5117405 -5 -6 -7 Parameter Symbol Min Max Min Max Min Max Unit Notes Write command setup time t WCS 0 — 0 — 0 — ns 14 Write command hold time t WCH 7 — 10 — 13 — ns Write command pulse width t WP 7 — 10 — 10 — ns Write command to lead time t RWL 7 — 10 — 13 — ns Write command to lead time t CWL 7 — 10 — 13 — ns Data-in setup time t DS 0 — 0 — 0 — ns 15 Data-in hold time t DH 7 — 10 — 13 — ns 15 Notes Read-Modify-Write Cycle HM5116405/HM5117405 -5 -6 -7 Parameter Symbol Min Max Min Max Min Max Unit Read-modify-write cycle time t RWC 111 — 135 — 161 — ns to delay time t RWD 67 — 79 — 92 — ns 14 to delay time t CWD 30 — 34 — 40 — ns 14 t AWD 42 — 49 — 57 — ns 14 t OEH 13 — 15 — 18 — ns Column address to delay time hold time from Refresh Cycle HM5116405/HM5117405 -5 Parameter Symbol -6 -7 Min Max Min Max Min Max Unit setup time (CBR refresh cycle) t CSR 5 — 5 — 5 — ns hold time (CBR refresh cycle) t CHR 7 — 10 — 10 — ns setup time (CBR refresh cycle) t WRP 0 — 0 — 0 — ns hold time (CBR refresh cycle) t WRH 7 — 10 — 10 — ns t RPC 5 — 5 — 5 — ns precharge to hold time Notes 13 HM5116405 Series, HM5117405 Series EDO Page Mode Cycle HM51W16405/HM51W17405 -5 -6 -7 Symbol Min Max Min Max Min Max EDO page mode cycle time t HPC 20 — EDO page mode pulse width t RASP — 100000 — Access time from precharge t CPA — 28 — 35 28 — 35 — low t DOH 3 — 3 hold time referred t COL 7 — to t COP 5 — t RCHC 28 — Parameter hold time from precharge t CPRH Output data hold time from setup time Read command hold time from precharge 25 — — 30 Unit Notes ns 21 100000 ns 16 — 40 ns 9, 17, 20 40 — ns — 3 — ns 10 — 13 — ns 5 — 5 — ns 35 — 40 — ns 100000 — 9, 17 EDO Page Mode Read-Modify-Write Cycle HM5116405/HM5117405 -5 Parameter Symbol EDO page mode read- modify-write t HPRWC cycle time delay time from precharge t CPW -6 -7 Min Max Min Max Min Max Unit Notes 57 — 68 — 79 ns 45 — 54 — 62 ns 14 Notes Test Mode Cycle *19 HM5116405/HM5117405 -5 Parameter -6 -7 Symbol Min Max Min Max Min Max Unit Test mode setup time t WTS 0 — 0 — 0 — ns Test mode hold time t WTH 7 — 10 — 10 — ns Refresh (HM5116405 Series) Parameter Symbol Max Unit Notes Refresh period t REF 64 ms 4096 cycles Refresh period (L-version) t REF 128 ms 4096 cycles 14 HM5116405 Series, HM5117405 Series Refresh (HM5117405 Series) Parameter Symbol Max Unit Notes Refresh period t REF 32 ms 2048 cycles Refresh period (L-version) t REF 128 ms 2048 cycles Notes: 1. AC measurements assume t T = 2 ns. 2. An initial pause of 200 s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing -only refresh or -beforerefresh). If -beforerefresh cycles are the internal refresh counter is used, a minimum of eight required. 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if t RCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 5. Either t OED or tCDD must be satisfied. 6. Either t DZO or tDZC must be satisfied. 7. V IH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and VIL (max). 8. Assumes that t RCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF. 10. Assumes that t RCD tRCD (max) and tRCD + t CAC (max) tRAD + t AA (max). 11. Assumes that t RAD tRAD (max) and tRCD + t CAC (max) tRAD + t AA (max). 12. Either t RCH or tRRH must be satisfied for a read cycles. 13. t OFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t WCS , t RWD, t CWD, t AWD and t CPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t WCS tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD tRWD (min), tCWD tCWD (min), and tAWD tAWD (min), or tCWD tCWD (min), tAWD tAWD (min) and tCPW t CPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. These parameters are referred to leading edge in early write cycles and to leading edge in delayed write or read-modify-write cycles. 16. t RASP defines pulse width in EDO page mode cycles. 17. Access time is determined by the longest among t AA , t CAC and t CPA. 18. In delayed write or read-modify-write cycles, must disable output buffer prior to applying data to device. 19. The 16M DRAM offers a 16-bit time saving parallel test mode. Address CA0 and CA1 for the 4M 4 are don’t care during test mode. Test mode is set by performing a -and-before(WCBR) cycle. In 16-bit parallel test mode, data is written into 4 bits in parallel at each I/O (I/O1 to I/O4) and read out from each I/O. If 4 bits of each I/O are equal (all 1s or 0s), data output pin is a high state during test mode read cycle, then the device has passed. If they are not equal, data output pin is a low state, then the device has failed. Refresh during test mode operation can be performed by normal read cycles or by WCBR refresh cycles. 15 HM5116405 Series, HM5117405 Series To get out of test mode and enter a normal operation mode, perform either a regular beforerefresh cycle or -only refresh cycle. 20. In a test mode read cycle, the value of tRAC , t AA, t CAC and t CPA is delayed by 2 ns to 5 ns for the specified value. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. 21. t HPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode cycle (EDO read cycles. If both write and read operation are mixed in a EDO page mode cycle (tCAS + tCP + 2 tT) becomes greater page mode mix cycle (1), (2)), minimum value of than the specified t HPC (min) value. The value of cycle time of mixed EDO page mode is shown in EDO page mode mix cycle (1) and (2). and . Data output turns off and becomes high impedance from later risting edge of Hold time and turn off time are specified by the timing specifications of later rising edge of and between t OHR and t OH , and between t OFR and t OFF. 22. Data output turns off and becomes high impedance from later rising edge of and . Hold time and turn off time are specified by the timing specifications of later rising edge of and between t OHR and t OH and between tOFR and t OFF. 23. XXX: H or L (H: V IH (min) VIN VIH (max), L: VIL (min) VIN VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or VIL. 16 HM5116405 Series, HM5117405 Series Timing Waveforms*23 Read Cycle t RC t RAS t CSH t CRP t RCD t RSH t CAS tT t RAD t ASR Address t RP t RAH Row t RAL t ASC t CAL t CAH Column t RRH t RCHR t RCH t RCS t WED t DZC t CDD t RDD High-Z Din t DZO t OED t OEA t OEZ t OHO t OFF t CAC t AA t OH t OFR t OHR t RAC t CLZ t WEZ Dout Dout Early Write Cycle 17 HM5116405 Series, HM5117405 Series tRC tRAS tRP tCSH tCRP tRCD tRSH tCAS tT tASR Address tRAH Row tASC tCAH Column tWCS tWCH tDS Din Dout tDH Din High-Z* * t WCS 18 t WCS (min) HM5116405 Series, HM5117405 Series Delayed Write Cycle*18 t RC t RAS t RP RAS t CRP t CSH t RCD t RSH t CAS tT CAS t ASR Address t RAH t ASC Row t CAH Column t CWL t RWL t WP t RCS WE t DZC Din t DS High-Z t DH Din t DZO t OEH t OED OE t OEZ t CLZ High-Z Dout Invalid Dout 19 HM5116405 Series, HM5117405 Series Read-Modify-Write Cycle*18 t RWC t RAS t RP tT t RCD t CAS t CRP t RAD t ASR Address tRAH t ASC Row t CAH Column t RCS t CWD tCWL t AWD t RWL t RWD t WP t DZC t DH t DS High-Z Din Din t OED t DZO t OEH t OEA t CAC t OEZ t AA t RAC t OHO Dout Dout t CLZ -Only Refresh Cycle 20 High-Z HM5116405 Series, HM5117405 Series t RC t RAS t RP tT t CRP t RPC t ASR Address t CRP t RAH Row t OFR t OFF Dout High-Z 21 HM5116405 Series, HM5117405 Series -Before- Refresh Cycle t RC t RP t RPC t RAS t CSR t RP t CHR t RPC tT t CP t WRP t WRH t CP Address t OFR t OFF Dout 22 High-Z t CRP HM5116405 Series, HM5117405 Series Hidden Refresh Cycle t RC t RAS t RP t RC t RAS t RC t RP t RAS t RP tT t RSH t CHR t CRP t RCD t RAD t ASR t RAH Address t RAL t ASC Row t CAH Column t RCS t RRH t WRH t WRP t WRP tWRH t RRH t RCH t WED t DZC t CDD t RDD High-Z Din t DZO t OED t OEA t CAC t AA t RAC t OFF t OH t CLZ Dout t OEZ t WEZ t OHO Dout t OFR t OHR 23 HM5116405 Series, HM5117405 Series EDO Page Mode Read Cycle t RP t RNCD tT t CSH t CP t HPC t CAS tASR Address tRAH tASC Row t CP t HPC t CPRH t CP t tCAS tCAS t RCHC t RCH t RCS tCAH Column 1 t ASC t CAH t ASC t CAH Column 2 Column 3 t CAL t CRP RSH t CAS t RCHR t RCS t HPC t RASP t CAL t RRH t RCH t RAL t CAH tASC t WED Column 4 t CAL t CAL tRDD tCDD tDZC High-Z Din tCOL tDZO tAA tCAC tCAC tAA tWEZ 24 tCPA tAA tCAC tOEZ tOHO tDOH Dout 1 Dout 2 Dout 2 tOFR tOHR tOEZ tAA tOEZ tOEA tRAC Dout tOED tCPA tCPA tOEA tCOP tOHO Dout 3 tOHO tOFF tOH tCAC tOEA Dout 4 HM5116405 Series, HM5117405 Series EDO Page Mode Early Write Cycle tRASP tT tCSH tASR Address Row tRAH tASC tDS Dout tCAH Column 1 tWCS Din tHPC tCAS tRCD tRP tWCH tDH Din 1 tCP tRSH tCAS tASC tCAH Column 2 tWCS tDS tWCH tDH Din 2 tCP tCAS tASC tCRP tCAH Column N tWCS tDS tWCH tDH Din N High-Z* * t WCS t WCS (min) 25 HM5116405 Series, HM5117405 Series EDO Page Mode Delayed Write Cycle*18 t RASP t RP tT t CP t CSH t RCD t CRP t CP t HPC t CAS t CAS t RSH t CAS t RAD t ASR t ASC t RAH Address t ASC t CAH Row t ASC t CAH Column 1 t CAH Column 2 t CWL Column N t CWL t CWL t RWL t RCS t RCS t RCS t WP t WP t WP t DZC t DS t DZC t DS t DZC t DS t DH t DH Din 1 Din t DZO t DH Din 2 t DZO t OED Din N t DZO t OED t OEH t CLZ t OEH t CLZ t OEZ t OED t OEH t CLZ t OEZ t OEZ High-Z Dout Invalid Dout 26 Invalid Dout Invalid Dout HM5116405 Series, HM5117405 Series EDO Page Mode Read-Modify-Write Cycle*18 t RASP t RP tT t HPRWC t CP t RCD t RSH t CP t CAS t CAS t CRP t CAS t RAD t ASR Address t ASC t RAH Row t ASC t CAH t CAH Column 1 Column 2 t RWD t CWL Column N t CPW t AWD t CWL t RCS t WP t RCS t WP t WP t DZC t DS t DH Din 1 t OED t OED t OEH t OEZ t OEH t OHO t OHO t OEA t CAC t AA t CPA t CLZ t OED t DZO t OEA t CAC t RAC Din N t OEH t OHO t AA t DH Din 2 t DZO t OEA t CAC t RWL t CWD t DZC t DS t DH t DZO t CWL t AWD t CWD t DZC t DS Din t CPW t AWD t CWD t RCS t ASC t CAH t AA t CPA t OEZ t CLZ t OEZ t CLZ High-Z Dout Dout 1 Dout 2 Dout N 27 HM5116405 Series, HM5117405 Series EDO Page Mode Mix Cycle (1) t RP t RASP tT t CAS t CRP t CP t CP t CP t CAS tCAS tCAS t CSH tRSH t RCD t WCS tWCH tCPW tAWD t ASC tRAH tASR Address Row tCAH Column 1 t CAL t DS Din tASC t CAH tASC t CAH Column 2 Column 3 t CAL tWP tASC t RAL t CAH Column 4 t CAL t DH Din 1 t RRH t RCH tRCS t RCS High-Z tRDD tCDD t CAL t DH t DS Din 3 tOED tCPA tCPA tAA tOEA tCPA tAA 28 t OEZ tCAC t OHO tCAC Dout tWED t DOH Dout 2 Dout 3 tOFR tWEZ tAA tOEZ tCAC tOHO tOEA tOFF tOH Dout 4 HM5116405 Series, HM5117405 Series EDO Page Mode Mix Cycle (2) t RNCD t RP t RASP tT t CSH t CAS t RCD t CAS tCAS tCAS t RCHR t RCS t RCH tWCS t WCH t ASC tRAH Address Row tCAH Column 1 t ASC t CAH t ASC t CAH Column 2 Column 3 t CAL tRSH t RCS t RCS t CAL t RRH t RCH tWP tCPW tASR t CRP t CP t CP t RAL t CAH tASC Column 4 t CAL t CAL t DS t DS High-Z Din t DH tRDD tCDD t DH Din 2 Din 3 tOED tOED tCOP tWED tCOL t OEA tAA tOEA tCAC tOEZ tCPA tAA tCAC tRAC tOEZ t OHO t OHO Dout Dout 1 tOFR tWEZ tCPA Dout 3 tAA tCAC tOEZ tOEA tOFF tOH tOHO Dout 4 29 HM5116405 Series, HM5117405 Series Test Mode Cycle *19 Set Cycle** Test Mode Cycle *,** Reset Cycle Normal Mode RAS CAS WE * CBR or RAS-only refresh ** Address, Din, OE: H or L 30 HM5116405 Series, HM5117405 Series Test Mode Set Cycle t RC t RP t RPC t RAS t CSR t RP t CHR t RPC t CRP tT t CP t WTS t WTH t CP Address t OFR t OFF Dout High-Z 31 HM5116405 Series, HM5117405 Series Package Dimensions HM5116405S/LS Series HM5117405S/LS Series (CP-26/24DB) Unit: mm 14 8.51 0.13 26 16.90 17.27 Max 21 19 13 0.43 0.41 0.10 0.08 1.27 2.54 Dimension including the plating thickness Base material dimension 32 2.65 0.80 +0.25 –0.17 1.30 Max 0.12 0.26 6 8 0.74 3.50 1 + 0.19 6.79 – 0.18 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) CP-26/24DB Conforms Conforms 0.8 g HM5116405 Series, HM5117405 Series HM5116405TS/LTS Series HM5117405TS/LTS Series (TTP-26/24DA) Unit: mm 14 7.62 26 17.14 17.54 Max 21 19 0.42 0.40 0.08 0.06 6 8 1.27 13 0.80 0.21 M 9.22 1.15 Max 0.20 Dimension including the plating thickness Base material dimension 0.05 0.04 0.05 0.13 0.10 0.145 0.125 1.20 Max 0 –5 2.54 0.50 Hitachi Code JEDEC EIAJ Weight (reference value) 0.10 0.68 1 TTP-26/24DA Conforms — 0.30 g 33 HM5116405 Series, HM5117405 Series When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi’s permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user’s unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. Hitachi, Ltd. Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi Semiconductor (America) Inc. 2000 Sierra Point Parkway Brisbane, CA. 94005-1897 USA Tel: 800-285-1601 Fax:303-297-0447 Hitachi Europe GmbH Continental Europe Dornacher Straße 3 D-85622 Feldkirchen München Tel: 089-9 91 80-0 Fax: 089-9 29 30-00 Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 01628-585000 Fax: 01628-585160 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071 Copyright © Hitachi, Ltd., 1997. All rights reserved. Printed in Japan. 34 HM5116405 Series, HM5117405 Series Revision Record Rev. Date Contents of Modification Drawn by Approved by 1.0 Oct. 14, 1996 Initial issue Y. Kasama M. Mishima 2.0 Nov. 8, 1996 Addition of HM5116405-5 Series Y. Kasama Y. Matsuno Y. Kasama Y. Matsuno Addition of HM5117405-5 Series Power dissipation (active) 550/495 mW(max) to 495/440/385 mW (max) (HM5116405 Series) 605/550 mW(max) to 550/495/440 mW (max) (HM5117405 Series) DC Characteristics (HM5116405 Series) I CC7 max: 110/100 mA to 80/70/65 mA DC Characteristics (HM5117405 Series) I CC1 I CC3 I CC6 I CC7 max: max: max: max: 110/100 mA to 100/90/80 mA 110/100 mA to 100/90/80 mA 110/100 mA to 100/90/80 mA 110/100 mA to 90/80/75 mA AC Characteristics t RCD min: 20/20 ns to 11/14/14 ns t RAD min: 15/15 ns to 9/12/12 ns t RSH min: 15/18 ns to 10/13/13 ns t RRH min: 0/0 ns to 5/5/5 ns t RWC min: 149/175 ns to 111/135/161 ns t RWD min: 82/95 ns to 67/79/92 ns t CWD min: 37/43 ns to 30/34/40 ns t AWD min: 52/60 ns to 42/49/57 ns t RPC min: 0/0 ns to 5/5/5 ns t HPRWC min: 79/90 ns to 57/68/79 ns Timing Waveforms Addition of t RNCD timing to EDO page mode mix cycle (2) 3.0 Feb. 27, 1997 AC Characteristics t RRH min: 5/5/5 ns to 0/0/0 ns 4.0 Nov. 1997 Change of Subtitle 35