HM5112805FTD-5, HM5113805FTD-5 128M EDO DRAM (16-Mword × 8-bit) 8k refresh/4k refresh E0174H10 (Ver. 1.0) (Previous ADE-203-1052B (Z)) Jul. 16, 2001 Description The HM5112805F Series, HM5113805F Series are 128M-bit dynamic RAMs organized as 16,777,216word × 8-bit. They have realized high performance and low power by employing CMOS process technology. HM5112805F Series, HM5113805F Series offer Extended Data Out (EDO) Page Mode as a high speed access mode. They are packaged in 32-pin plastic TSOPII. Features • Single 3.3 V supply: 3.3 V ± 0.15 V • Access time: 50 ns (max) • Power dissipation Active: 759 mW (max) (HM5112805F Series) 897 mW (max) (HM5113805F Series) Standby : 3.5 mW (max) (CMOS interface) • EDO page mode capability • Refresh cycles RAS-only refresh 8192 cycles/64 ms (HM5112805F) 4096 cycles/64 ms (HM5113805F) CBR/Hidden refresh 4096 cycles/64 ms (HM5112805F, HM5113805F) • 3 variations of refresh RAS-only refresh CAS-before-RAS refresh Hidden refresh Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd. HM5112805FTD-5, HM5113805FTD-5 Ordering Information Type No. Access time Package HM5112805FTD-5 50 ns 400-mil 32-pin plastic TSOP II (TTP-32DF) HM5113805FTD-5 50 ns Data Sheet E0174H10 2 HM5112805FTD-5, HM5113805FTD-5 Pin Arrangement (HM5112805F Series) 32-pin TSOP VCC 1 32 VSS I/O0 2 31 I/O7 I/O1 3 30 I/O6 I/O2 4 29 I/O5 I/O3 5 28 I/O4 NC 6 27 VSS VCC 7 26 CAS WE 8 25 OE RAS 9 24 A12 A0 10 23 A11 A1 11 22 A10 A2 12 21 A9 A3 13 20 A8 A4 14 19 A7 A5 15 18 A6 VCC 16 17 VSS (Top view) Pin Description Pin name Function A0 to A12 Address input — Row/Refresh address A0 to A12 — Column address A0 to A10 I/O0 to I/O7 Data input/output RAS Row address strobe CAS Column address strobe WE Write enable OE Output enable VCC Power supply VSS Ground NC No connection Data Sheet E0174H10 3 HM5112805FTD-5, HM5113805FTD-5 Pin Arrangement (HM5113805F Series) 32-pin TSOP VCC 1 32 VSS I/O0 2 31 I/O7 I/O1 3 30 I/O6 I/O2 4 29 I/O5 I/O3 5 28 I/O4 NC 6 27 VSS VCC 7 26 CAS WE 8 25 OE RAS 9 24 NC A0 10 23 A11 A1 11 22 A10 A2 12 21 A9 A3 13 20 A8 A4 14 19 A7 A5 15 18 A6 VCC 16 17 VSS (Top view) Pin Description Pin name Function A0 to A11 Address input — Row/Refresh address A0 to A11 — Column address A0 to A11 I/O0 to I/O7 Data input/output RAS Row address strobe CAS Column address strobe WE Write enable OE Output enable VCC Power supply VSS Ground NC No connection Data Sheet E0174H10 4 HM5112805FTD-5, HM5113805FTD-5 Block Diagram (HM5112805F Series) A0 A1 to Upper pellet Column decoder • • • Column address buffers 16M array A10 Row decoder 16M array Row address buffers I/O buffers 16M array I/O1 I/O3 I/O4 I/O6 16M array A11 A12 Timing and control RAS CAS WE OE Lower pellet Timing and control Column decoder Column address buffers Row address buffers Row decoder • • • 16M array 16M array I/O buffers 16M array I/O0 I/O2 I/O5 I/O7 16M array Data Sheet E0174H10 5 HM5112805FTD-5, HM5113805FTD-5 Block Diagram (HM5113805F Series) A0 to A10 • • • Column address buffers 16M array 16M array Row decoder A1 Upper pellet Column decoder Row address buffers I/O buffers 16M array I/O1 I/O3 I/O4 I/O6 16M array A11 Timing and control RAS CAS WE OE Lower pellet Timing and control Column decoder Column address buffers Row address buffers Row decoder • • • 16M array 16M array I/O buffers 16M array 16M array Data Sheet E0174H10 6 I/O0 I/O2 I/O5 I/O7 HM5112805FTD-5, HM5113805FTD-5 Operation Table RAS CAS WE OE I/O 0 to I/O 7 Operation H × × × High-Z Standby L L H L L L Dout Read cycle L* 2 × Din Early write cycle 2 H Din Delayed write cycle L L L* L L H to L L to H Dout/Din Read-modify-write cycle L H × × High-Z RAS-only refresh cycle H to L L H × High-Z CAS-before-RAS refresh cycle L L H H High-Z Read cycle (Output disabled) Notes: 1. H: VIH (inactive), L: VIL (active), ×: VIH or VIL 2. t WCS ≥ 0 ns: Early write cycle t WCS < 0 ns: Delayed write cycle Absolute Maximum Ratings Parameter Symbol Value Unit Terminal voltage on any pin relative to V SS VT –0.5 to VCC + 0.5 (≤ 4.6 V (max)) V Power supply voltage relative to V SS VCC –0.5 to +4.6 V Short circuit output current Iout 50 mA Power dissipation PT 1.0 W Storage temperature Tstg –55 to +125 °C DC Operating Conditions Parameter Symbol Min Typ Max Unit Notes Supply voltage VCC 3.15 3.3 3.45 V 1, 2 VSS 0 0 0 V 2 Input high voltage VIH 2.0 — VCC + 0.3 V 1 Input low voltage VIL –0.3 — 0.8 V 1 Ambient temperature range Ta 0 — 70 ˚C Notes: 1. All voltage referred to VSS . 2. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level. Data Sheet E0174H10 7 HM5112805FTD-5, HM5113805FTD-5 DC Characteristics (HM5112805F Series) HM5112805F -5 Parameter Symbol Min Max Unit Test conditions I CC1 — 220 mA t RC = min I CC2 — 4 mA TTL interface RAS, CAS = VIH Dout = High-Z — 1 mA CMOS interface RAS, CAS ≥ VCC – 0.2 V Dout = High-Z I CC3 — 220 mA t RC = min I CC5 — 10 mA RAS = VIH, CAS = VIL Dout = enable CAS-before-RAS refresh current I CC6 — 220 mA t RC = min I CC7 — 220 mA RAS = VIL , CAS cycle, t HPC = tHPC min Input leakage current I LI –5 5 µA 0 V ≤ Vin ≤ VCC + 0.3 V Output leakage current I LO –5 5 µA 0 V ≤ Vout ≤ VCC Dout = disable Output high voltage VOH 2.4 VCC V High Iout = –2 mA Output low voltage VOL 0 0.4 V Low Iout = 2 mA 1, Operating current* * 2 Standby current RAS-only refresh current*2 1 Standby current* 1, EDO page mode current* * 3 Notes: 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Measured with one sequential address change per EDO cycle, tHPC . Data Sheet E0174H10 8 HM5112805FTD-5, HM5113805FTD-5 DC Characteristics (HM5113805F Series) HM5113805F -5 Parameter Symbol Min Max Unit Test conditions I CC1 — 260 mA t RC = min I CC2 — 4 mA TTL interface RAS, CAS = VIH Dout = High-Z — 1 mA CMOS interface RAS, CAS ≥ VCC – 0.2 V Dout = High-Z I CC3 — 260 mA t RC = min I CC5 — 10 mA RAS = VIH, CAS = VIL Dout = enable CAS-before-RAS refresh current I CC6 — 260 mA t RC = min I CC7 — 220 mA RAS = VIL , CAS cycle, t HPC = tHPC min Input leakage current I LI –5 5 µA 0 V ≤ Vin ≤ VCC + 0.3 V Output leakage current I LO –5 5 µA 0 V ≤ Vout ≤ VCC Dout = disable Output high voltage VOH 2.4 VCC V High Iout = –2 mA Output low voltage VOL 0 0.4 V Low Iout = 2 mA 1, Operating current* * 2 Standby current RAS-only refresh current*2 1 Standby current* 1, EDO page mode current* * 3 Notes: 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Measured with one sequential address change per EDO cycle, tHPC . Capacitance (Ta = 25˚C, VCC = 3.3 V ± 0.15 V) Parameter Symbol Typ Max Unit Notes Input capacitance (Address) CI1 — 7 pF 1 Input capacitance (Clocks) CI2 — 7 pF 1 Output capacitance (Data-in, Data-out) CI/O — 8 pF 1, 2 Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. RAS and CAS = VIH to disable Dout. Data Sheet E0174H10 9 HM5112805FTD-5, HM5113805FTD-5 AC Characteristics (Ta = 0 to +70˚C, VCC = 3.3 V ± 0.15 V, VSS = 0 V) *1, *2, *19 Test Conditions • • • • • Input rise and fall time: 2 ns Input pulse levels: V IL = 0 V, V IH = 3.0 V Input timing reference levels: 0.8 V, 2.0 V Output timing reference levels: 0.8 V, 2.0 V Output load: 1 TTL gate + C L (100 pF) (Including scope and jig) Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters) HM5112805F/HM5113805F -5 Parameter Symbol Min Max Unit Random read or write cycle time t RC 84 — ns RAS precharge time t RP 30 — ns CAS precharge time t CP 8 — ns RAS pulse width t RAS 50 10000 ns CAS pulse width t CAS 8 10000 ns Row address setup time t ASR 0 — ns Row address hold time t RAH 8 — ns Column address setup time t ASC 0 — ns Column address hold time t CAH 8 — ns RAS to CAS delay time t RCD 12 37 ns 3 RAS to column address delay time t RAD 10 25 ns 4 RAS hold time t RSH 13 — ns CAS hold time t CSH 38 — ns CAS to RAS precharge time t CRP 5 — ns OE to Din delay time t OED 13 — ns 5 OE delay time from Din t DZO 0 — ns 6 CAS delay time from Din t DZC 0 — ns 6 Transition time (rise and fall) tT 2 50 ns 7 Data Sheet E0174H10 10 Notes HM5112805FTD-5, HM5113805FTD-5 Read Cycle HM5112805F/HM5113805F -5 Parameter Symbol Min Max Unit Notes Access time from RAS t RAC — 50 ns 8, 9 Access time from CAS t CAC — 13 ns 9, 10, 17 Access time from address t AA — 25 ns 9, 11, 17 Access time from OE t OEA — 13 ns 9 Read command setup time t RCS 0 — ns Read command hold time to CAS t RCH 0 — ns Read command hold time from RAS t RCHR 50 — ns Read command hold time to RAS t RRH 0 — ns Column address to RAS lead time t RAL 25 — ns Column address to CAS lead time t CAL 15 — ns CAS to output in low-Z t CLZ 0 — ns Output data hold time t OH 3 — ns Output data hold time from OE t OHO 3 — ns Output buffer turn-off time t OFF — 13 ns 13, 21 Output buffer turn-off to OE t OEZ — 13 ns 13 CAS to Din delay time t CDD 13 — ns 5 Output data hold time from RAS t OHR 3 — ns 21 Output buffer turn-off to RAS t OFR — 13 ns 13, 21 Output buffer turn-off to WE t WEZ — 13 ns 13 WE to Din delay time t WED 13 — ns RAS to Din delay time t RDD 13 — ns 12 12 21 Data Sheet E0174H10 11 HM5112805FTD-5, HM5113805FTD-5 Write Cycle HM5112805F/HM5113805F -5 Parameter Symbol Min Max Unit Notes Write command setup time t WCS 0 — ns 14 Write command hold time t WCH 8 — ns Write command pulse width t WP 8 — ns Write command to RAS lead time t RWL 13 — ns Write command to CAS lead time t CWL 8 — ns Data-in setup time t DS 0 — ns 15 Data-in hold time t DH 8 — ns 15 Notes Read-Modify-Write Cycle HM5112805F/HM5113805F -5 Parameter Symbol Min Max Unit Read-modify-write cycle time t RWC 116 — ns RAS to WE delay time t RWD 67 — ns 14 CAS to WE delay time t CWD 30 — ns 14 Column address to WE delay time t AWD 42 — ns 14 OE hold time from WE t OEH 13 — ns Refresh Cycle HM5112805F/HM5113805F -5 Parameter Symbol Min Max Unit CAS setup time (CBR refresh cycle) t CSR 5 — ns CAS hold time (CBR refresh cycle) t CHR 8 — ns WE setup time (CBR refresh cycle) t WRP 0 — ns WE hold time (CBR refresh cycle) t WRH 8 — ns RAS precharge to CAS hold time t RPC 5 — ns Data Sheet E0174H10 12 Notes HM5112805FTD-5, HM5113805FTD-5 EDO Page Mode Cycle HM5112805F/HM5113805F -5 Parameter Symbol Min Max Unit Notes EDO page mode cycle time t HPC 20 — ns 20 EDO page mode RAS pulse width t RASP — 100000 ns 16 Access time from CAS precharge t CPA — 28 ns 9, 17 RAS hold time from CAS precharge t CPRH 28 — ns Output data hold time from CAS low t DOH 3 — ns CAS hold time referred OE t COL 8 — ns CAS to OE setup time t COP 5 — ns Read command hold time from CAS precharge t RCHC 28 — ns Write pulse width during CAS precharge t WPE 8 — ns OE precharge time 8 — ns t OEP 9, 22 EDO Page Mode Read-Modify-Write Cycle HM5112805F/HM5113805F -5 Parameter Symbol Min Max Unit EDO page mode read-modify-write cycle time t HPRWC 57 — ns WE delay time from CAS precharge t CPW 45 — ns Notes 14 Refresh(HM5112805F Series) Parameter Symbol Max Unit Notes Refresh period t REF 64 ms 8192 cycles Parameter Symbol Max Unit Notes Refresh period t REF 64 ms 4096 cycles Refresh(HM5113805F Series) Data Sheet E0174H10 13 HM5112805FTD-5, HM5113805FTD-5 Notes: 1. AC measurements assume t T = 2 ns. 2. An initial pause of 200 µs is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh). 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if t RCD is greater than the specified tRCD (max) limit, than the access time is controlled exclusively by tCAC . 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 5. Either t OED or tCDD must be satisfied. 6. Either t DZO or tDZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and VIL (max). 8. Assumes that t RCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF. 10. Assumes that t RCD ≥ tRCD (max) and tRCD + tCAC (max) ≥ tRAD + tAA (max). 11. Assumes that t RAD ≥ tRAD (max) and tRCD + tCAC (max) ≤ tRAD + tAA (max). 12. Either t RCH or tRRH must be satisfied for a read cycles. 13. t OFF (max), tOEZ (max), tWEZ (max) and tOFR (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t WCS , t RWD, t CWD, t AWD and t CPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t WCS ≥ tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD ≥ tRWD (min), tCWD ≥ tCWD (min), and tAWD ≥ tAWD (min), or tCWD ≥ tCWD (min), tAWD ≥ tAWD (min) and tCPW ≥ t CPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. t DS and t DH are referred to CAS leading edge in early write cycles and to WE leading edge in delayed write or read-modify-write cycles. 16. t RASP defines RAS pulse width in EDO page mode cycles. 17. Access time is determined by the longest among tAA, t CAC and t CPA. 18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 19. When output buffers are enabled once, sustain the low impedance state until valid data is obtained. When output buffer is turned on and off within a very short time, generally it causes large V CC/V SS line noise, which causes to degrade V IH min/VIL max level. 20. t HPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode read cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO page mode mix cycle (1), (2)), minimum value of CAS cycle (tCAS + tCP + 2 tT) becomes greater than the specified t HPC (min) value. The value of CAS cycle time of mixed EDO page mode is shown in EDO page mode mix cycle (1) and (2). 21. Data output turns off and becomes high impedance from later rising edge of RAS and CAS. Hold time and turn off time are specified by the timing specifications of later rising edge of RAS and CAS between t OHR and t OH and between tOFR and t OFF. Data Sheet E0174H10 14 HM5112805FTD-5, HM5113805FTD-5 22. t DOH defines the time at which the output level go cross. V OL = 0.8 V, VOH = 2.0 V of output timing reference level. 23. XXX: H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or VIL. Data Sheet E0174H10 15 HM5112805FTD-5, HM5113805FTD-5 Timing Waveforms*23 Read Cycle tRC tRAS tRP RAS tCSH tT CAS Address tRSH tCAS tRAD tASR tCRP tRCD tRAH tRAL tCAL tASC tCAH Column Row tRRH tRCHR tRCS tRCH WE tDZC tCDD tWED tRDD High-Z Din tDZO tOEA tOED OE tOEZ tOHO tOFF tOH tOFR tOHR tCAC tAA tRAC tCLZ tWEZ Dout Dout Data Sheet E0174H10 16 HM5112805FTD-5, HM5113805FTD-5 Early Write Cycle tRC tRAS tRP RAS tCSH tCRP tRCD tRSH tCAS tT CAS tASR Address tRAH Row tASC tCAH Column tWCS tWCH WE tDS Din tDH Din High-Z* Dout * t WCS t WCS (min) Data Sheet E0174H10 17 HM5112805FTD-5, HM5113805FTD-5 Delayed Write Cycle*18 tRC tRAS tRP RAS tCSH tCRP tRCD tRSH tCAS tT CAS tASR Address tRAH tASC Row tCAH Column tCWL tRWL tWP tRCS WE tDS tDZC High-Z Din , Din tDH tOED tDZO tOEH tOEP OE tOEZ tCLZ High-Z Dout Invalid Dout Data Sheet E0174H10 18 HM5112805FTD-5, HM5113805FTD-5 Read-Modify-Write Cycle*18 tRWC tRAS tRP RAS tT tRCD CAS tCRP tRAD tASR Address tCAS tASC tRAH Row tCAH Column tCWL tCWD tRCS tRWL tWP tAWD tRWD WE tDZC tDS High-Z Din , Din tDH tOED tDZO tOEH tOEA tOEP OE tCAC tAA tOEZ tRAC tOHO Dout Dout High-Z tCLZ Data Sheet E0174H10 19 HM5112805FTD-5, HM5113805FTD-5 RAS-Only Refresh Cycle tRC tRAS tRP RAS tT tRPC tCRP CAS tASR tRAH Row Address tOFR tOFF High-Z !" Dout Data Sheet E0174H10 20 tCRP HM5112805FTD-5, HM5113805FTD-5 CAS-Before-RAS Refresh Cycle tRC tRP tRC tRP tRAS tRAS tRP RAS tT tRPC tCP tRPC tCSR tCHR tWRP tWRH tCP tCRP tCSR tCHR CAS tWRP tWRH WE Address tOFR tOFF High-Z Dout Data Sheet E0174H10 21 HM5112805FTD-5, HM5113805FTD-5 Hidden Refresh Cycle tRC tRAS tRP tRC tRAS tRC tRP tRAS tRP RAS tT tRSH tCHR tCRP tRCD CAS tRAD tASR Address tRAH tRAL tASC Row tCAH Column tRRH tRCS tRCH WE tWED tDZC tCDD tRDD High-Z Din tDZO tOED tOEA OE tCAC tAA tRAC tOFF tCLZ Dout Dout Data Sheet E0174H10 22 tOH tOFR tOHR tOEZ tWEZ tOHO HM5112805FTD-5, HM5113805FTD-5 EDO Page Mode Read Cycle (1) t RP t HPC t RASP RAS tT t CSH t CP t HPC t CAS CAS t HPC t CPRH t CP t t CRP RSH t CAS t RCHR t RCS t CP tCAS tCAS t RCHC t RCH t RCS t RRH t RCH WE tASR Address tRAH tASC Row tCAH Column 1 t WPE t ASC t CAH t ASC t CAH Column 2 Column 3 t CAL t CAL t RAL t CAH tASC t WED Column 4 t CAL t CAL tRDD tCDD tDZC High-Z Din tCOL tDZO tCOP t OEP tOED tOEP OE tAA tCAC tCPA tAA tCAC tOEZ tOHO tAA tOEZ tCAC tAA tOFR tOHR tOEZ tCPA tCPA tOEA tWEZ tOEA tRAC Dout tDOH Dout 1 Dout 2 Dout 2 tOHO Dout 3 tCAC tOHO tOFF tOH tOEA Dout 4 Data Sheet E0174H10 23 HM5112805FTD-5, HM5113805FTD-5 EDO Page Mode Read Cycle (2) t RP t RASP RAS tT t CSH t CP t HPC t CAS CAS tHPC t CP t HPC t CP t CAS t CAS t CRP tRSH tCAS t RCHC t RRH t RCH t RCS WE tASR Address tRAH tASC Row tCAH Column 1 t ASC t CAH t ASC t CAH Column 2 t CAL t RAL t CAH tASC Column 3 t CAL t WED Column 4 t CAL tRDD t CAL tDZC tCDD High-Z Din tCOL tDZO tCOP t OEP tOED tOEP OE tOEA tCPA tAA tCAC tCPA tAA tCAC tOEZ tAA tCAC tAA tOFR tOHR tOEZ tCPA tDOH tRAC Dout tOHO tOEA tDOH tOHO Dout 1 Dout 2 Data Sheet E0174H10 24 tOEZ Dout 2 Dout 3 tCAC tOHO tOFF tOH tOEA Dout 4 HM5112805FTD-5, HM5113805FTD-5 EDO Page Mode Early Write Cycle tRP tRASP RAS tT tCSH tHPC tCAS tRCD tCP tRSH tCAS tCP tCAS tCRP CAS tASR Address Row tRAH tASC tCAH Column 1 tWCS tWCH tASC tCAH Column 2 tWCS tWCH tASC tCAH Column N tWCS tWCH WE tDS Din Dout tDH Din 1 tDS tDH Din 2 tDS tDH Din N High-Z* * t WCS t WCS (min) Data Sheet E0174H10 25 HM5112805FTD-5, HM5113805FTD-5 EDO Page Mode Delayed Write Cycle*18 tRASP tRP RAS tT tCP tRCD tCRP tCP tCSH tHPC tCAS tCAS tRSH tCAS CAS tRAD tASR tASC tCAH tASC tCAH Column 1 Column 2 tRAH Address Row tASC tCAH tCWL Column N tCWL tCWL tRWL tRCS tRCS tRCS WE tWP tDZC tDS tWP tDZC tDS tWP tDZC tDS tDH tDH Din 1 Din tDZO tOED tDH Din 2 tDZO tOED tOEP tOEH tDZO tOED tOEP tOEH tOEP tOEH Din N OE tCLZ tCLZ tOEZ tCLZ tOEZ tOEZ Dout Invalid Dout Invalid Dout Data Sheet E0174H10 26 Invalid Dout High-Z HM5112805FTD-5, HM5113805FTD-5 EDO Page Mode Read-Modify-Write Cycle*18 t RASP t RP RAS tT t HPRWC t CP t RCD t RSH t CP t CAS t CAS t CRP t CAS CAS t ASR Address t RAD t ASC t RAH t ASC t CAH t CAH Column 1 Row t ASC t CAH Column 2 t RWD t CWL t AWD t CPW t CWL t CPW t AWD t RCS t CWD Column N t CWL t AWD t RCS t CWD t RWL t CWD WE t RCS t WP t t DZC DS t WP t t DZC DS t WP t t DZC DS t DH t DH Din 1 Din t DZO t OED t OEP t OEH t DH Din 2 t OED t DZO t OEP t OEH Din N t OED t DZO t OEP t OEH OE t OHO t OHO t OHO t OEA t CAC t OEA t CAC t AA t OEA t CAC t AA t CPA t RAC t OEZ t CLZ t AA t CPA t OEZ t CLZ t OEZ t CLZ High-Z Dout Dout 1 Dout 2 Dout N Data Sheet E0174H10 27 HM5112805FTD-5, HM5113805FTD-5 EDO Page Mode Mix Cycle (1)*20 t RP t RASP RAS tT t CAS CAS t CRP t CP t CP t CP t CAS tCAS t CSH tCAS tCWL tRSH t RCD t WCS t WCH tCPW tAWD WE t ASC tRAH tASR Address Row tCAH Column 1 t RRH t RCH t RCS t RCS t ASC t CAH tASC t CAH Column 2 Column 3 tWP tASC t RAL t CAH Column 4 t CAL t DS Din Din 1 tRDD tCDD t CAL t DH t DH t DS High-Z Din 3 tOED tOEP tWED OE tCPA tAA tCAC Dout t DOH Dout 2 Data Sheet E0174H10 28 tOFR tWEZ tCPA tCPA tAA tOEA t OEZ tCAC t OHO Dout 3 tAA tOEZ tCAC tOHO tOEA tOFF tOH Dout 4 HM5112805FTD-5, HM5113805FTD-5 EDO Page Mode Mix Cycle (2) *20 t RP t RASP RAS tT t CSH t CAS CAS t RCD t CAS tCAS t RCHR t RCS t RCH tWCS t WCH Address tCAS tCWL Row tCAH Column 1 t ASC t CAH t ASC t CAH Column 2 Column 3 t RRH t RCH tWP tCPW t ASC tRAH tRSH t RCS t RCS WE tASR t CRP t CP t CP t CP t RAL t CAH tASC Column 4 t CAL t CAL t DS t DS High-Z Din t DH tRDD tCDD t DH Din 2 Din 3 t OEP t OEP tOED tOED tCOP tWED tCOL OE t OEA tAA tOEA tCAC tOEZ tCPA tAA tCAC tRAC tOEZ t OHO t OHO Dout Dout 1 tOFR tWEZ tCPA Dout 3 tAA tCAC tOEZ tOEA tOFF tOH tOHO Dout 4 Data Sheet E0174H10 29 HM5112805FTD-5, HM5113805FTD-5 Package Dimensions HM5112805FTD Series HM5113805FTD Series (TTP-32DF) As of January, 2001 Unit: mm 20.95 21.35 Max 17 10.16 32 1.27 0.21 M 0.80 11.76 ± 0.20 *0.12 ± 0.05 0.10 ± 0.04 1.20 Max 1.15 Max 0.10 *Dimension including the plating thickness Base material dimension Data Sheet E0174H10 30 0° – 5° 0.50 ± 0.10 Hitachi Code JEDEC EIAJ Mass (reference value) TTP-32DF — — 0.54 g 0.45 *0.42 ± 0.08 0.40 ± 0.06 16 0.05 ± 0.05 1 HM5112805FTD-5, HM5113805FTD-5 Cautions 1. Elpida Memory, Inc. neither warrants nor grants licenses of any rights of Elpida Memory, Inc.’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Elpida Memory, Inc. bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, contact Elpida Memory, Inc. before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Elpida Memory, Inc. particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. product does not cause bodily injury, fire or other consequential damage due to operation of the Elpida Memory, Inc. product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Elpida Memory, Inc.. 7. Contact Elpida Memory, Inc. for any questions regarding this document or Elpida Memory, Inc. semiconductor products. Data Sheet E0174H10 31