TECHNICAL DATA KK74LV174 Hex D-type flip-flop with reset; positive edge-trigger The 74LV174 is a low–voltage Si–gate CMOS device and is pin and function compatible with the 74HC/HCT174. The 74LV174 has six edge–triggered D–type flip–flops with individual D inputs and Q outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) all flip–flops simultaneously. The register is fully edge–triggered. The state of each D input, one set–up time prior to the LOW–to–HIGH clock transition, is transferred to the corresponding output of the flip–flop. A LOW level on the MR input forces all outputs LOW, independently of clock or data inputs. The device is useful for applications requiring true outputs only and clock and master reset inputs that are common to all storage elements. • Output voltage levels are compatible with input levels of CMOS, NMOS and TTL ICS • Supply voltage range: 1.2 to 5.5 V • Low input current: 1.0 µА; 0.1 µА at Т = 25 °С • Output current: 6 mA at Vcc = 3.0 V; 12 mA at Vcc = 4.5 V • High Noise Immunity Characteristic of CMOS Devices ORDERING INFORMATION KK74LV174N Plastic KK74LV174D SOIC TA = -40° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM MR 1 16 V CC Q0 2 15 Q5 D0 3 14 D5 D1 4 13 D4 Q1 5 12 Q4 D2 6 11 D3 Q2 7 10 Q3 GND 8 9 CP FUNCTION TABLE Inputs CP MR PIN 16=VCC PIN 08 = GND Outputs MR CP Dn Qn L X X L H H H H L L X no change X no change H L H H= high level L = low level X = don’t care 1 KK74LV174 MAXIMUM RATINGS* Symbol VCC Parameter Value Unit DC supply voltage -0.5 to +5.0 V 1 Input diode current ±20 mA 2 Output diode current ±50 mA Output source or sink current ±25 mA ICC VCC current ±50 mA IGND GND current ±50 mA IIK * IOK * IO * 3 PD Tstg TL Power dissipation per package: * Plastic DIP SO 4 mW 750 500 Storage Temperature -65 to +150 °C 260 °C Lead Temperature, 1.5 mm (Plastic DIP Package), 0.3 mm (SO Package) from Case for 4 Seconds * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. *1 VI < -0.5 V or VI > VCC + 0.5 V *2 VO < -0.5 V or VO > VCC + 0.5 V *3 -0.5 V < VO < VCC + 0.5 V *4 Derating - Plastic DIP: - 12 mW/°C from 70° to 125°C SO Package: : - 8 mW/°C from 70° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit 1.2 5.5 V VCC DC Supply Voltage VIN DC Input Voltage 0 VCC V DC Output Voltage 0 VCC V -40 +125 °C 0 0 0 0 500 200 100 50 ns/V VOUT TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Figure 1) 1.0 В ≤VCC <2.0 В 2.0 В ≤VCC <2.7 В 2.7 В ≤VCC <3.6 В 3.6 В ≤VCC ≤5.5 В This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2 KK74LV174 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Symbol Parameter Test VCC conditions V Guaranteed Limit -40°C to 25°C 85°C Unit 125°C min max min max min max VIH HIGH level input voltage 1.2 2.0 2.7 3.0 3.6 4.5 5.5 0.9 1.4 2.0 2.0 2.0 3.15 3.85 - 0.9 1.4 2.0 2.0 2.0 3.15 3.85 - 0.9 1.4 2.0 2.0 2.0 3.15 3.85 - V VIL LOW level input voltage 1.2 2.0 2.7 3.0 3.6 4.5 5.5 - 0.3 0.6 0.8 0.8 0.8 1.35 1.65 - 0.3 0.6 0.8 0.8 0.8 1.35 1.65 - 0.3 0.6 0.8 0.8 0.8 1.35 1.65 V VOH HIGH level output voltage VI = VIH or VIL IO = -100 µА 1.2 2.0 2.7 3.0 3.6 4.5 5.5 1.05 1.85 2.55 2.85 3.45 4.35 5.35 - 1.0 1.8 2.5 2.8 3.4 4.3 5.3 - 1.0 1.8 2.5 2.8 3.4 4.3 5.3 - V VI = VIH or VIL IO = -6 mА 3.0 2.48 - 2.34 - 2.20 - V VI = VIH or VIL IO = -12 mА 4.5 3.70 - 3.60 - 3.50 - V VI = VIH or VIL IO = 100 µА 1.2 2.0 2.7 3.0 3.6 4.5 5.5 - 0.15 0.15 0.15 0.15 0.15 0.15 0.15 - 0.2 0.2 0.2 0.2 0.2 0.2 0.2 - 0.2 0.2 0.2 0.2 0.2 0.2 0.2 V VI = VIH or VIL IO = 6 mА 3.0 - 0.33 - 0.40 - 0.50 V VI = VIH or VIL IO = 12 mА 4.5 - 0.40 - 0.55 - 0.65 V Input current VI = VCC or 0 V 5.5 - ±0.1 - ±1.0 - ±1.0 µА ICC Supply current VI =VCC or 0 V IO = 0 µА 5.5 - 8.0 - 80 - 160 µА ICC1 Additional quiescent supply current per input VI =VCC – 0.6 V 2.7 3.6 - 0.2 0.2 - 0.5 0.5 - 0.85 0.85 mA VOL II LOW level output voltage 3 KK74LV174 AC ELECTRICAL CHARACTERISTICS (CL=50 pF, RL = 1 kΩ, tr=tf=2.5 ns) Symbol Parameter tPHL, tPLH Propagation delay CP to Qn Test VCC conditions V Guaranteed Limit -40°C to 25°C 85°C 125°C min max min max min max Unit VI = 0 V or VCC Figure 1, 4 1.2 2.0 2.7 3.0 4.5 - 200 34 24 20 17 - 230 43 31 25 21 - 260 53 39 31 26 ns tPHL Propagation delay MR to Qn VI = 0 V or VCC Figure 2, 4 1.2 2.0 2.7 3.0 4.5 - 160 34 24 20 17 - 190 43 31 25 21 - 220 53 39 31 26 ns tW Clock pulse width HIGH or LOW VI = 0 V or VCC Figure 1, 4 1.2 2.0 2.7 3.0 4.5 100 28 21 17 14 - 140 34 25 20 17 - 180 41 30 24 20 - ns tW Master reset pulse width LOW VI = 0 V or VCC Figure 1, 4 1.2 2.0 2.7 3.0 4.5 100 28 21 17 14 - 140 34 25 20 17 - 180 41 30 24 20 - ns tREM Removal time MR to CP VI = 0 V or VCC Figure 3, 4 1.2 2.0 2.7 3.0 4.5 40 19 13 11 9 - 60 22 16 13 11 - 80 26 19 15 13 - ns tSU Set-up time Dn to CP VI = 0 В or VCC Рисунок 3, 4 1.2 2.0 2.7 3.0 4.5 50 5 5 5 5 - 50 5 5 5 5 - 50 5 5 5 5 - ns th Hold time Dn to CP VI = 0 В or VCC Рисунок 2, 4 1.2 2.0 2.7 3.0 4.5 50 5 5 5 5 - 50 5 5 5 5 - 50 5 5 5 5 - ns CI Input capacitance ТA = 25°C 5.0 - 7.0 - - - - pF CPD Power dissipation VI = 0 V or VCC capacitance (per flip-flop) T = 25°C A 5.5 - 34 - - - - pF fmax Maximum clock pulse frequency 1.2 2.0 2.7 3.0 4.5 - 2.0 16 22 27 32 - 1.0 14 19 24 27 - 1.0 12 16 20 24 MHz VI = 0 В or VCC Рисунок 1 4 KK74LV174 tw tr CP 10% VM tf V1 90% (1) (2) MR GND (2) V1 (1) VM GND t PHL tw 1/fmax Q tPLH Q VM VM VOH (1) VOL t PHL VOH (1) t rec VOL CP Figure 1. Switching Waveforms (2) V1 (1) VM GND Figure 2. Switching Waveforms TEST POINT VALID DATA VM GND t su CP (2) V1 (1) th VM (1) (2) V1 DEVICE UNDER TEST OUTPUT RL * CL GND * Includes all probe and jig capacitance Figure 3. Switching Waveforms Figure 4. Test Circuit Note: (1) VM = 1.5 V at VCC = 2.7 V VM = 0.5 ⋅VCC at VCC =1.2 V, 2.0 V, 3.0 V, 4.5 V (2) V1 = VCC at VCC =1.2 V, 2.0 V, 2.7 V, 4.5 V V1 = 2.7 V at VCC = 3.0 V 5 KK74LV174 N SUFFIX PLASTIC DIP (MS - 001BB) A Dimension, mm 9 16 B 1 8 Symbol MIN MAX A 18.67 19.69 B 6.1 7.11 5.33 C F L C -T- SEATING PLANE N G K D M H J 0.25 (0.010) M T NOTES: 1. Dimensions “A”, “B” do not include mold flash or protrusions. Maximum mold flash or protrusions 0.25 mm (0.010) per side. D 0.36 0.56 F 1.14 1.78 G 2.54 H 7.62 J 0° 10° K 2.92 3.81 L 7.62 8.26 M 0.2 0.36 N 0.38 D SUFFIX SOIC (MS - 012AC) Dimension, mm A 16 9 H B 1 G P 8 R x 45 C -TK D SEATING PLANE J 0.25 (0.010) M T C M F M Symbol MIN MAX A 9.8 10 B 3.8 4 C 1.35 1.75 D 0.33 0.51 F 0.4 1.27 G 1.27 H 5.72 J 0° 8° K 0.1 0.25 1. Dimensions A and B do not include mold flash or protrusion. M 0.19 0.25 2. Maximum mold flash or protrusion 0.15 mm (0.006) per side for A; for B ‑ 0.25 mm (0.010) per side. P 5.8 6.2 R 0.25 0.5 NOTES: 6