ML14469 Addressable Asynchronous Receiver/Transmitter CMOS Legacy Device: Motorola MC14469 The ML14469 receives one or two 11–bit words in a serial data stream. One of the incoming words contains the address and when the address matches, the ML14469 then transmits information in two 11–bit word data streams. Each of the transmitted words contains eight data bits, an even parity bit, and start and stop bits. The received word contains seven address bits with the address of the ML14469 set on seven pins. Therefore, 27 or 128 units can be interconnected in simplex or full–duplex data transmission. In addition to the address received, seven command bits may be received for general–purpose data or control use. The ML14469 finds application in transmitting data from remote analog–to–digital converters, remote MPUs, or remote digital transducers to the master computer or MPU. • • • • • • • • • P DIP 16 = QP PLASTIC DIP CASE 711 40 1 44 PLCC 44 = -4P PLCC PACKAGE CASE 777 1 CROSS REFERENCE/ORDERING INFORMATION PACKAGE MOTOROLA LANSDALE P DIP 40 MC14469P ML14469QP PLCC 44 MC14469FN ML14469-4P Supply Voltage Range: 4.5 V to 18 V Low Quiescent Current: 75 µA Maximum @ 5 V, 25°C Guaranteed Data Rates to 4800 Baud @ 5 V, to 9600 Baud @ 12 V Receive — Serial to Parallel Transmit — Parallel to Parallel Transmit and Receive Simultaneously in Full Duplex Crystal or Resonator Operation for On–Chip Oscillator See Application Note AN806A Chip Complexity: 1200 FETs or 300 Equivalent Gates Operating Temperature Range TA = –40° to +85°C Note: Lansdale lead free (Pb) product, as it becomes available, will be identified by a part number prefix change from ML to MLE. PIN ASSIGNMENTS Page 1 of 10 A6 10 31 ID0 ID1 ID2 11 12 13 30 29 28 ID3 ID4 ID5 ID6 14 15 16 17 27 26 25 24 ID7 RI VSS 18 19 20 23 22 21 C6 CS VAP SEND S0 S1 S2 S3 S4 S5 C3 32 C1 C2 9 S6 S7 C4 C5 C6 CS VAP NC SEND S0 S1 S2 S3 S5 S4 A5 C4 C5 C0 35 34 33 S6 6 7 8 6 5 4 3 2 1 44 43 42 41 40 7 39 8 38 9 37 10 36 11 35 12 34 13 33 14 32 15 31 16 30 17 29 18 19 20 21 22 23 24 25 26 27 28 S7 A2 A3 A4 A2 A3 A4 A5 A6 NC ID0 ID1 ID2 ID3 ID4 NC VDD 38 37 36 NC TRO 39 3 4 5 OSC1 2 RESET OSC2 OSC2 RESET A0 A1 VDD C0 C1 C2 C3 ID7 RI VSS 40 ID6 1 ID5 OSC1 A1 PLCC A0 P DIP NC = NO CONNECTION TRO www.lansdale.com Issue 0 ML14469 LANSDALE Semiconductor, Inc. BLOCK DIAGRAM RECEIVE (A0 – A6) ADDRESS (C0 – C6) COMMAND DATA 7 7 ADDRESS CONTROL AND DATA COMPARATOR COMMAND LATCHES CLOCK COMPARE RECEIVE DATA (RI) STROBE 7 STATIC SHIFT REGISTER RVAL CLOCK RECEIVE DATA STROBE COMMAND STROBE (CS) TIMING AND CONTROL AND PARITY CHECK RECEIVE DATA STROBE ENABLE SEND ENABLE LATCH (SEL) VALID ADDRESS PULSE (VAP) TRANSMIT (S0 – S7) STATUS (ID0 – ID7) INPUT DATA 8 STATUS LATCHES 8 STATUS STROBE 8 CLOCK STATIC SHIFT REGISTER LOAD SELECT 2 SEND CONTROL AND PARITY GENERATOR SEND ENABLE DATA RATE CLOCK OUTPUT LOGIC TRANSMIT DATA (TRO) 4 STATUS STROBE RVAL CLOCKS OSC1 OSC2 CLOCK OSCILLATOR CLOCK GENERATOR DATA RATE CLOCK RECEIVE DATA STROBE RECEIVE DATA STROBE ENABLE Page 2 of 10 www.lansdale.com Issue 0 ML14469 LANSDALE Semiconductor, Inc. MAXIMUM RATINGS (Voltages referenced to VSS) Rating DC Supply Voltage Input Voltage, All Inputs DC Current Drain per Pin Operating Temperature Range Storage Temperature Range Symbol Value Unit VDD – 0.5 to + 18 V Vin – 0.5 to VDD + 0.5 V I 10 mA TA – 40 to + 85 °C Tstg – 65 to + 150 °C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). ELECTRICAL CHARACTERISTICS (Voltages referenced to VSS) – 40°C Characteristic “0” Level Vin = 0 or VDD “1” Level Input Voltage (Except OSC1) VO = 4.5 or 0.5 V VO = 9.0 or 1.0 V VO = 13.5 or 1.5 V VO = 0.5 or 4.5 V VO = 1.0 or 9.0 V VO = 1.5 or 13.5 V Output Drive Current (Except OSC2) VOH = 2.5 V VOH = 4.6 V VOH = 9.5 V VOH = 13.5 V VOL = 0.4 V VOL = 0.5 V VOL = 1.5 V Output Drive Current (OSC2 Only) VOH = 2.5 V VOH = 4.6 V VOH = 9.5 V VOH = 13.5 V VOL = 0.4 V VOL = 0.5 V VOL = 1.5 V OSC Frequency* Input Current Pull–Up Current (A0 – A6, ID0 – ID7) 85°C VDD Min Max Min Max Min Max 5.0 10 15 — — — 0.05 0.05 0.05 — — — 0.05 0.05 0.05 — — — 0.05 0.05 0.05 5.0 10 15 4.95 9.95 14.95 — — — 4.95 9.95 14.95 — — — 4.95 9.95 14.95 — — — 5.0 10 15 — — — 1.5 3.0 4.0 — — — 1.5 3.0 4.0 — — — 1.5 3.0 4.0 5.0 10 15 3.5 7.0 11 — — — 3.5 7.0 11 — — — 3.5 7.0 11 — — — 5.0 5.0 10 15 – 1.0 – 0.2 – 0.5 – 1.4 — — — — – 0.8 – 0.16 – 0.4 – 1.2 — — — — – 0.6 – 0.12 – 0.3 – 1.0 — — — — 5.0 10 15 0.52 1.3 3.6 — — — 0.44 1.1 3.0 — — — 0.36 0.9 2.4 — — — 5.0 5.0 10 15 – 0.19 – 0.04 – 0.09 – 0.29 — — — — – 0.16 – 0.035 – 0.08 – 0.27 — — — — – 0.13 – 0.03 – 0.06 – 0.2 — — — — IOL 5.0 10 15 0.1 0.17 0.5 — — — 0.085 0.14 0.42 — — — 0.07 0.1 0.3 — — — mA fOSC 4.5 12 0 0 400 800 0 0 365 730 0 0 310 620 kHz Iin 15 — ± 0.3 — ± 0.3 — ± 1.0 µA IUP 15 12 120 10 100 8.0 85 µA Symbol Output Voltage Vin = VDD or 0 25°C VOL V VOH VIL VIH IOH IOL IOH mA mA Source Sink V mA Source Sink V V “0” Level “1” Level Unit Input Capacitance (Vin = 0) Cin — — — — 7.5 — — pF Quiescent Current (Per Package) IDD 5.0 10 15 — — — 75 150 300 — — — 75 150 300 — — — 565 1125 2250 µA Supply Voltage VDD — + 4.5 + 18 + 4.5 + 18 + 4.5 + 18 V * 310 kHz at 85°C guarantees 4800 baud; 620 kHz at 85°C guarantees 9600 baud. Page 3 of 10 www.lansdale.com Issue 0 ML14469 LANSDALE Semiconductor, Inc. RECEIVE DATA (RI) COMMAND ADDRESS ST ML14469 PIN DESIGNATION MC6850 PIN DESIGNATION P A0 A1 A2 A3 A4 A5 A6 ST SP ADDRESS IDENTIFIER (HIGH LOGIC LEVEL) P C0 C1 C2 C3 C4 C5 C6 SP COMMAND IDENTIFIER (LOW LOGIC LEVEL) D0 D1 D2 D3 D4 D5 D6 D0 D1 D2 D3 D4 D5 D6 TRANSMIT DATA (TRO) INPUT DATA STATUS ST ML14469 PIN DESIGNATION MC6850 PIN DESIGNATION P SP ST P ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 S0 S1 S2 S3 S4 S5 S6 S7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 ST = START BIT P = PARITY BIT SP = STOP BIT SP ID0 to ID7 = ML14469 IDENTIFICATION CODE S0 to S7 = ML14469 STATUS CODE A0 to A6 = ADDRESS BITS C0 to C6 = COMMAND BITS D0 to D7 = ACIA BUS BITS Figure 1. Data Format and Corresponding Data Position and Pins for MC14469 and MC6850 M S COMMAND B S P S 0 1 2 3 4 5 6 S 0 1 2 3 4 5 6 7 P T X X X X X X X T X X X X X X X ADDRESS M S B 7 S P P RECEIVER INPUT (RI) VALID ADDRESS PULSE (VAP) INTERNAL VALID ADDRESS LATCH (VAL) INTERNAL SEND ENABLE LATCH (SEL) COMMAND STROBE OUTPUT (CS) SEND INPUT (SEND) TRANSMIT OUT (TRO) M S S B S X X X X X X X X P P S X X X X X X X T 0 1 2 3 4 5 6 7 ID M S S B X P P T 0 1 2 3 4 5 6 7 STATUS Figure 2. Typical Receive/Send Cycle Page 4 of 10 www.lansdale.com Issue 0 ML14469 LANSDALE Semiconductor, Inc. PIN DESCRIPTIONS inversion if it is to drive another ML14469. A0 – A6 Address Inputs These inputs are the address setting pins which contain the address match for the received signal. Pins A0 – A6 have on–chip pull–up resistors. C0 – C6 Command Word These pins are the readout of the general–purpose command word which is the second word of the received signal. CS Command Strobe This is the output for the command strobe signifying a valid set of command data (C0 – C6). The pulse width is one oscillator cycle. For example, when a 307.2 kHz ceramic resonator is used, the pulse width is approximately 3 µs. ID0 – ID7 Input Data Pins These pins contain the input data for the first eight bits of data to be transmitted. Pins ID0 – ID7 have on–chip pull–up resistors. OSC1, OSC2 Oscillator Input and Oscillator Output These pins are the oscillator input and output (see Figure3). RESET Reset When this pin is pulled low for a minimum of 700 ns, the circuit is reset and ready for operation. RI Receive Input This is the receive input pin. S0 – S7 Second or Status Input Data These pins contain the input data for the second eight bits of data to be transmitted. SEND Send This pin accepts the send command after receipt of an address. TRO Transmit Register Output Signal This pin transmits the outgoing signal. Note that it is inverted from the incoming signal. It must go through one stage of Page 5 of 10 VAP Valid Address Pulse This is the output for the valid address pulse upon receipt of a matched incoming address. VDD Positive Power Supply This pin is the package positive power supply connection. This pin may range from + 4.5 V to + 18 V with respect toVSS. VSS Negative Power Supply This pin is the negative power supply connection. Normally this pin is system ground. OPERATING CHARACTERISTICS The receipt of a start bit on the receive input (RI) line causes the receive clock to start at a frequency equal to that of the oscillator divided by 64. All received data is strobed in at the center of a receive clock period. The start bit is followed by eight data bits. Seven of the bits are compared against states of the address of the particular circuit (A0 –A6). Address is latched 31 clock cycles after the end of the start bit of the incoming address. The eighth bit signifies an address word “1” or a command word “0”. Next, a parity bit is received and checked by the internal logic for even parity. Finally a stop bit is received. At the completion of the cycle if the address matches, a valid address pulse (VAP) occurs. Immediately following the address word, a command word is received. It also contains a start bit, eight data bits, even parity bit, and a stop bit. The eight data bits are composed of a seven–bit command, and a “0” which indicates a command word. At the end of the command word a command strobe pulse (CS) occurs. A positive transition on the send input initiates the transmit sequence. Send must occur within seven bit times of CS. Again the transmitted data is made up of two eleven–bit words, i.e., address and command words. The data portion of the first word is made up from input data inputs (ID0 –ID7), and the data for the second word from second input data (S0 – S7) inputs. The data on inputs ID0 – ID7 is latched one clock before the falling edge of the start bit. The data on inputs S0 – S7 is latched on the rising edge of the start bit. The transmitted signal is the inversion of the received signal, which allows the use of an inverting amplifier to drive the lines. TRO begins either 1/2 or 1–1/2 bit times after send, depending where send occurs. The oscillator can be crystal controlled or ceramic resonator controlled for required accuracy. OSC1 can be driven from an external oscillator (see Figure 3). www.lansdale.com Issue 0 ML14469 LANSDALE Semiconductor, Inc. ML14469 INTERNAL OSCILLATOR VDATA OSC1 OSC2 15 MΩ 1.0 kΩ DATA LINE X1 C1 GROUND LINE C2 NOTE: For externally generated clock, drive OSC1, float OSC2. X1 = Ceramic Resonator: 307.2 kHz ± 1 kHz for 4800 baud rate. C1 and C2 are sized per the ceramic resonator supplier’s recommendation. RI TRO VDD 1.0 µF Ceramic Resonator Suppliers:* 1. Morgan Matroc, Inc., Bedford, OH, 216/232–8600 2. Radio Materials Co., Attica, IN, 317/762–2491 * Lansdale cannot recommend one supplier over another and in no way suggests that this is a complete listing of ceramic resonator suppliers. Figure 3. Oscillator Circuit ML14469 VSS Figure 4. Rectified Power from Data Lines Circuit C0 C1 CHANNEL SELECT C2 CS SEND ML14469 SELECT CHANNEL, START CONVERSION END CONVERSION ANALOG INPUTS S0 S1 S2 S3 S4 DIGITAL OUTPUTS S5 S6 S7 8–CHANNEL A/D CONVERTER ASSEMBLY Figure 5. A–D Converter Interface Page 6 of 10 www.lansdale.com Issue 0 ML14469 LANSDALE Semiconductor, Inc. V+ 1k 10 k TRO RI 10 k 10 k TRO RI VDD ID7 VSS RI VDD TRO VSS ID7 S7 S7 MC6850 ACIA OR UART MASTER STATION 10 k ML14469 0 A0,ID0 A1,ID1 A2,ID2 A3,ID3 A4,ID4 CS A5,ID5 SEND A6,ID6 ADDRESS 0000000 REMOTE ML14469 STATIONS VSS ID7 S7 ML14469 1 A1,ID1 A2,ID2 A3,ID3 A4,ID4 A5,ID5 A6,ID6 ADDRESS 0000001 RI VDD TRO TRO VSS ML14469 127 ADDRESS 1111111 CS SEND CS SEND NOTE: For simplex operation the ID7 must be tied high, S7 must be tied low, and the 7–bit ID must be the same as the 7–bit address (or set to some unused address) to prevent erroneous responses. Figure 6. Single Line, Simplex Data Transmission V+ VDD 1k 1k 10 k TRO RI 10 k TRO VSS MC6850 ACIA OR UART MASTER STATION 10 k RI VDD ADDRESS 0000000 A0 A1 A2 A3 A4 A5 A6 RI VDD TRO VSS ML14469 0 TRO VSS ML14469 1 ADDRESS 0000001 VAP SEND 10 k A1 A2 A3 A4 A5 A6 RI VDD ADDRESS 1111111 VAP SEND TRO VSS ML14469 127 VAP SEND REMOTE ML14469 STATIONS Figure 7. Double Line, Full Duplex Data Transmission Page 7 of 10 www.lansdale.com Issue 0 ML14469 LANSDALE Semiconductor, Inc. RESET CLEAR COMMAND LATCH RESET SEL RESET RESET VAL INITIALIZE TRANSMITTER INITIALIZE RECEIVER Y Y MSB = 1? VAL SET? N Y SEL SET? COMMAND VALID? N N N VAL SET? N Y N SEND =1? Y N SEL SET? N Y RESET VAL AND SEL Y LATCH COMMAND ADDRESS VALID? N ISSUE CS Y SET VAL PREVIOUS TRANSMISSION COMPLETE? Y LATCH STATUS ISSUE VAP TRANSMIT ID SET SEL N TRANSMIT STATUS 8 BIT TIMES? Y RESET SEL Figure 8. Flow Chart of ML14469 Operation Page 8 of 10 www.lansdale.com Issue 0 ML14469 LANSDALE Semiconductor, Inc. OUTLINE DIMENSIONS PLCC 44 = -4P (ML14469-4P) PLCC PACKAGE CASE 777–02 –N– Y BRK 0.007(0.180) M T B D L–M 0.007(0.180) M T U N S L–M S S N S Z –M– –L– V 44 W 1 X D G1 0.010 (0.25) VIEW D–D A 0.007(0.180) M T L–M S N S R 0.007(0.180) M T L–M S N S S T 0.007(0.180) M T H L–M S L–M S N S N N S S Z J C K1 E 0.004 (0.10) –T– SEATING G G1 0.010 (0.25) S K PLANE T L–M S N S F VIEW S 0.007(0.180) M T L–M S VIEW S NOTES: 1. DATUMS –L–, –M–, AND –N– ARE DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM –T–, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.25) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). Page 9 of 10 DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.685 0.695 0.685 0.695 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 ––– 0.025 ––– 0.650 0.656 0.650 0.656 0.042 0.048 0.042 0.048 0.042 0.056 ––– 0.020 2 10 0.610 0.630 0.040 ––– www.lansdale.com MILLIMETERS MIN MAX 17.40 17.65 17.40 17.65 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 ––– 0.64 ––– 16.51 16.66 16.51 16.66 1.07 1.21 1.07 1.21 1.07 1.42 ––– 0.50 2 10 15.50 16.00 1.02 ––– Issue 0 ML14469 LANSDALE Semiconductor, Inc. OUTLINE DIMENSIONS P DIP 40 = QP (ML14469QP) PLASTIC DIP CASE 711–03 40 NOTES: 1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 21 B 1 20 L A C N J H G F D K M SEATING PLANE DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 51.69 52.45 13.72 14.22 3.94 5.08 0.36 0.56 1.02 1.52 2.54 BSC 1.65 2.16 0.20 0.38 2.92 3.43 15.24 BSC 0 15 0.51 1.02 INCHES MIN MAX 2.035 2.065 0.540 0.560 0.155 0.200 0.014 0.022 0.040 0.060 0.100 BSC 0.065 0.085 0.008 0.015 0.115 0.135 0.600 BSC 0 15 0.020 0.040 Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. “Typical” parameters which may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by the customer’s technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc. Page 10 of 10 www.lansdale.com Issue 0