SM6453AB
3-wire Serial Data Volume Control for Headphone Amplifier IC
OVERVIEW
The SM6453AB is a stereo headphone amplifier IC with built-in electronic volume controlled by 3-wire serial
data. Two switchable input systems are supported. It features bass boost function, automatic gain control
(AGC) function, power-down function, and beep sound input/output function, making it ideal for use in portable electronic products.
■
■
DVDD1
DVDD2
DVSS
LRMXO
AGCTC
BSTC
BSTN
21
6
20
7
19
8
18
9
17
10 11 12 13 14 15 16
PACKAGE DIMENSIONS
(Unit: mm)
ORDERING INFORMATION
(Top view)
(Bottom view)
6.20 ± 0.1
0.50
5.00 ± 0.05
3.22TYP
1.00
32-pin QFN
32
SM6453AB
.7
0
Package
C0
Device
5.20 ± 0.1
6.00 ± 0.05
0.60 ± 0.10
■
22
5
0.60 ± 0.10
1
0.50
1.00
0.05
0.22 ± 0.05
0.05 M
0.22 ± 0.05
■
■
23
4
BSTO
BEEPLO
LOUT
AVSS2
AVDD2
AVDD3
AVSS3
ROUT
BEEPRO
2.68TYP
■
3
0.90 ± 0.05
■
24
0.005MIN
0.02TYP
0.04MAX
■
32 31 30 29 28 27 26
25
2
AVDD1
LIN1
LIN2
AVSS1
RIN1
RIN2
VBIAS
■
1
.2
■
MLEN
MCK
MDT
RSTN
MUTEN
PDN
BEEPI
VREF1
VREF2
C0
■
(Top view)
−
■
2 stereo system inputs, selectable 1 output system
Headphone amplifier function
• +12dB to -68dB output voltage gain range
(GCNT)
• +12dB headphone amplifier gain (GHPA)
Attenuation function
• 1.0dB step width, 81 steps, 0 to –80dB range
(GEVR)
Mute function
Bass boost function (2 boost characteristics controlled by external RC network)
Auto gain control function (AGC)
Beep sound input/output circuit
26mW+26mW maximum output power
(1kHz, THD + N = 10%, 16Ω load, 2.0V supply
voltage)
Power-down function
1.8 to 3.6V operating supply voltage range
Low current consumption
(2.3mA total, 2.4V supply voltage)
Silicon-gate CMOS process
32-pin QFN package
3
■
PINOUT
0
FEATURES
NIPPON PRECISION CIRCUITS INC.—1
SM6453AB
PIN DESCRIPTION
Number
Name
I/O1
1
MLEN
Ip
Microcontroller latch enable input
2
MCK
Ip
Microcontroller clock input
3
MDT
Ip
Microcontroller data input
4
RSTN
Ip
System reset (LOW-level reset)
5
MUTEN
I
Mute input (LOW-level mute)
6
PDN
I
Power-down mode select (LOW-level power-down)
7
BEEPI
I
Beep signal input
8
VREF1
O
Reference voltage 1
9
VREF2
O
Reference voltage 2
10
AVDD1
−
EVR-stage analog VDD
11
LIN1
I
Left-channel analog input 1
12
LIN2
I
Left-channel analog input 2
13
AVSS1
−
EVR-stage analog VSS
14
RIN1
I
Right-channel analog input 1
15
RIN2
I
Right-channel analog input 2
16
VBIAS
O
EVR-stage bias voltage
17
BEEPRO
O
Right-channel beep signal output
18
ROUT
O
Right-channel output
19
AVSS3
−
Headphone amplifier right-channel analog VSS
20
AVDD3
−
Headphone amplifier right-channel analog VDD
21
AVDD2
−
Headphone amplifier left-channel analog VDD
22
AVSS2
−
Headphone amplifier left-channel analog VSS
23
LOUT
O
Left-channel output
24
BEEPLO
O
Left-channel beep signal output
25
BSTO
O
Bass boost auxiliary output
26
BSTN
I
Bass boost auxiliary input
27
BSTC
O
Bass boost capacitor connection
28
AGCTC
O
AGC time constant set capacitor connection
29
LRMXO
O
Left and right-channel mixer detector output
30
DVSS
−
Digital VSS
31
DVDD2
−
Digital VDD2
32
DVDD1
−
Digital VDD1
Description
VDD
VDD2
VDD1
VDD2
1. Ip = input with pull-up resistance
VDD1, VDD2, VSS definitions
VDD1 = DVDD2 = AVDD1 = AVDD2 = AVDD3
VDD2 = DVDD1
VSS = DVSS = AVSS1 = AVSS2 = AVSS3
NIPPON PRECISION CIRCUITS INC.—2
SM6453AB
32
MLEN
31
30
29
28
BSTN
BSTC
AGCTC
LRMXO
DVSS
DVDD2
DVDD1
BLOCK DIAGRAM
27
26
25
1
BSTO
MDT
RSTN
3
Level Shifter
MCK
Microcontroller
Interface
BST
2
24
AGC
+12dB
23
HPA
22
4
BEEPLO
LOUT
AVSS2
EVR(0 to -80dB)
MUTEN
PDN
5
21
EVR
AMP
+12dB
6
HPA
20
AVDD2
AVDD3
EVR(0 to -80dB)
8
VREF2
17
Selector
13
14
15
AVSS3
ROUT
BEEPRO
16
VBIAS
12
RIN2
11
RIN1
10
AVSS1
9
18
BEEP
VREF1
LIN2
VREF2
19
EVR
AMP
LIN1
VREF1
7
AVDD1
BEEPI
NIPPON PRECISION CIRCUITS INC.—3
SM6453AB
SPECIFICATIONS
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
VDD1, VDD2
− 0.3 to 4.6
V
Digital system input voltage1
VIND
VSS − 0.3 to VDD2 + 0.3
V
Analog system input voltage2
VINA
VSS − 0.3 to VDD1 + 0.3
V
Storage temperature
TSTG
− 55 to 125
°C
Output current
IO
100
mA
Power dissipation3
PD
370
mW
Supply voltage
1. Digital system inputs: MLEN, MDT, MCK, RSTN, MUTEN, PDN, BEEPI
2. Analog system inputs: LIN1, LIN2, RIN1, RIN2, BSTN
3. NPC specified value θJa = 107.6°C/W
PD = {(TJMAX – Ta)/θJa} (TJMAX = 125°C, Ta = 85°C)
Recommended Operating Conditions
VSS = DVSS = AVSS1 = AVSS2 = AVSS3 = 0V, VDD1 = DVDD2 = AVDD1 = AVDD2 = AVDD3,
VDD2 = DVDD1
Parameter
Symbol
Conditions
Unit
Supply voltage 1
VDD1
1.8 to 3.6
V
Supply voltage 2
VDD2
1.8 to 3.6
V
DVDD2-AVDD1,
DVDD2-AVDD2,
DVDD2-AVDD3,
AVDD1-AVDD2,
AVDD1-AVDD3,
AVDD2-AVDD3
± 0.1
V
Ta
− 40 to 85
°C
Supply voltage difference
Operating temperature
NIPPON PRECISION CIRCUITS INC.—4
SM6453AB
DC Characteristics
AVSS1 = AVSS2 = AVSS3 = DVSS = 0V, AVDD1 = AVDD2 = AVDD3 = DVDD2 = 1.8 to 3.6V,
DVDD1 = 1.8 to 3.6V, Ta = – 40 to 85°C unless otherwise noted.
Rating
Parameter
Pins
Symbol
DVDD1
DVDD2
Input voltage 1
typ
max
(Note 1)
–
0.03
0.06
mA
IDDD1S
(Note 2)
–
0.2
1.0
µA
IDDD2A
(Note 1)
–
0.05
0.3
mA
IDDD2S
(Note 2)
–
0.2
1.0
µA
IDDAA
(Note 1)
–
2.3
3.6
mA
IDDAS
(Note 2)
–
13.0
25.0
µA
IDDAM1
(Note 3)
–
1.7
3.1
mA
IDDAM2
(Note 4)
–
0.5
–
mA
IDDAT
(Note 5)
–
7.0
10.0
mA
H-level
VIH1
0.8×DVDD1
–
–
V
L-level
VIL1
–
–
0.2×DVDD1
V
H-level
VIH2
1.2
–
–
V
L-level
VIL2
–
–
0.4
V
(*1)
Input voltage 2
Unit
min
IDDD1A
Current consumption
AVDD1
+
AVDD2
+
AVDD3
Condition
(*2)
Input current 1
(*1)
IIL1
VIN = 0V
–
25
90
µA
Input current 2
(*3)
IIH1
VIN = VDD1
–
280
900
µA
Input leakage current 1
(*1)
IIH2
VIN = VDD1
–
–
1.0
µA
Input leakage current 2
(*2)
IIL2
VIN = 0V
–
–
1.0
µA
Input leakage current 3
(*2)
IIH3
VIN = VDD1
–
–
1.0
µA
Input leakage current 4
(*3)
IIL3
VIN = 0V
–
–
1.0
µA
(Note 1) MUTEN = HIGH, PDN = HIGH, 600Ω resistor connected between VREF1 and all analog inputs (LIN1, LIN2, RIN1, RIN2), GEVR = 0dB,
Microcontroller clock frequency = 4MHz, data transfer from microcontroller.
(Note 2) MUTEN = LOW, PDN = LOW, 600Ω resistor connected between VREF1 and all analog inputs (LIN1, LIN2, RIN1, RIN2), GEVR = 0dB, data
transfer from microcontroller stopped, Pins (*1) = VDD2.
(Note 3) MUTEN = LOW, PDN = HIGH, 600Ω resistor connected between VREF1 and all analog inputs (LIN1, LIN2, RIN1, RIN2), GEVR = 0dB, data
transfer from microcontroller stopped, Pins (*1) = VDD2. Other than idling current of final stage of headphone amplifiers.
(Note 4) MUTEN = HIGH, PDN = HIGH, 600Ω resistor connected between VREF1 and all analog inputs (LIN1, LIN2, RIN1, RIN2), GEVR = 0dB, data
transfer from microcontroller stopped, Pins (*1) = VDD2. Idling current of final stage of headphone amplifiers only.
(Note 5) MUTEN = HIGH, PDN = HIGH, reference voltage see "Measurement circuit", All analog inputs (LIN1, LIN2, RIN1, RIN2) connected reference
input voltage, Bass boost = OFF, AGC = OFF, Frequency = 1kHz, PO = 0.5mW + 0.5mW
Pin types
Pin types
Name
(*1)
MLEN, MDT, MCK, RSTN
(*2)
MUTEN, PDN
(*3)
BEEPI
NIPPON PRECISION CIRCUITS INC.—5
SM6453AB
AC Characteristics
AVDD1 = AVDD2 = AVDD3 = DVDD1 = DVDD2 = 1.8 to 3.6V, AVSS1 = AVSS2 = AVSS3 = DVSS = 0V,
Ta = – 40 to 85°C unless otherwise noted.
Serial inputs (MDT, MCK, MLEN)
Rating
Parameter
Symbol
Unit
min
typ
max
MCK, MLEN rise time
tr
–
–
100
ns
MCK, MLEN fall time
tf
–
–
100
ns
MDT setup time
tMDS
50
–
–
ns
MDT hold time
tMDH
50
–
–
ns
Setup time
tMCS
50
–
–
ns
Hold time
tMCH
50
–
–
ns
LOW-level pulsewidth
tMEWL
50
–
–
ns
HIGH-level pulsewidth
tMEWH
50
–
–
ns
MLEN
0.5V DD2
MDT
tMDS
tMDH
MCK
0.5V DD2
tMCS
tMCH
MLEN
0.5V DD2
tMEWL
tMEWH
tf
tr
0.9VDD2
MLEN
MCK
0.9VDD2
0.1VDD2
0.1VDD2
Reset input (RSTN)
Rating
Parameter
RSTN LOW-level pulsewidth
Symbol
tRSTN
Unit
min
typ
max
100
–
–
ns
NIPPON PRECISION CIRCUITS INC.—6
SM6453AB
AC Analog Characteristics
VDD1 = VDD2 = 2.0V, analog input amplitude = 0.025Vrms, input frequency = 1kHz, Ta = 25°C, Measurement
circuit, PDN = HIGH, MUTEN = HIGH, MDT D0 to D12 = LOW, unless otherwise noted.
Analog input characteristics (LIN1, RIN1, LIN2, RIN2)
Parameter
Symbol
Reference input amplitude
VAI
Input resistance
RIN
Input clipping voltage
VCLP
Condition
GEVR = 0dB, PO = 0.5mW + 0.5mW
GEVR = 0dB, PO = 26mW + 26mW
Rating
Unit
min
typ
max
0.015
0.025
0.035
Vrms
18
23
–
kΩ
0.17
0.21
–
Vrms
Analog output characteristics (LOUT, ROUT)
Parameter
Residual noise voltage
Total harmonic distortion + noise
Symbol
VNS
THD + N
Condition
Rating
min
typ
max
Unit
GEVR = 0dB, A-WTD
–
26
38
µVrms
PO = 0.5mW + 0.5mW
–
0.3
1.0
%
Reference output power
POREF
0.4
0.5
0.6
mW
Reference output voltage
VOREF
0.08
0.09
0.098
Vrms
Maximum output power
POMAX
GEVR = 0dB, THD + N = 10%
22
26
–
mW
Maximum output voltage
VOMAX
GEVR = 0dB, THD + N = 10%
0.516
0.645
–
Vrms
BBST1
(Note 1)
+ 5.2
+ 7.2
+ 9.2
dBr
BBST2
(Note 2)
+ 12.0
+ 14.0
+ 16.0
dBr
AGC detection level
VAGC
0.5VDD1 reference voltage output
+ 0.30
+ 0.48
+ 0.66
V
Step width
GSTEP
0.1
1.0
1.6
dB
Bass boost response
Attenuation error (1kHz)
Absolute attenuation (1kHz)
Mute factor (1kHz)
Channel crosstalk
Power supply ripple rejection ratio
(Note 1)
(Note 2)
(Note 3)
(Note 4)
(Note 5)
(Note 6)
(Note 7)
(Note 8)
(Note 9)
GERR1
GEVR = 0dB to – 60dB
− 2.8
– 0.8
1.2
dB
GERR2
GEVR = – 61dB to – 72dB
– 2.0
0
2.0
dB
GERR3
GEVR = – 73dB to – 80dB
– 1.2
0.8
2.8
dB
GO1
GO = + 12dB (GEVR = 0dB)
+ 9.2
+ 11.2
+ 13.2
dB
GO2
GO = – 8dB (GEVR = – 20dB)
– 10.6
– 8.6
– 6.6
dB
GO3
GO = – 28dB (GEVR = – 40dB)
– 30.6
− 28.6
– 26.6
dB
GO4
GO = – 48dB (GEVR = – 60dB)
– 50.4
− 48.4
– 46.4
dB
GO5
GO = – 68dB (GEVR = – 80dB)
– 70.5
− 66.0
– 61.5
dB
GMUTE
(Note 3)
– 100.0
− 120.0
–
dB
CT1
(Note 4)
− 69.0
− 75.0
–
dB
CT2
(Note 5)
− 29.0
− 35.0
–
dB
CT3
(Note 6)
− 30.0
− 36.0
–
dB
PSRR1
(Note 7)
83.0
93.0
–
dB
PSRR2
(Note 8)
45.0
55.0
–
dB
PSRR3
(Note 9)
34.0
44.0
–
dB
Microcontroller data bit D9 = HIGH, D10 = LOW, D11 = LOW, 55Hz frequency, VOREF output
Microcontroller data bit D9 = HIGH, D10 = HIGH, D11 = LOW, 55Hz frequency, VOREF output
GEVR = 0dB, MDT D0 to D7 are muted, MUTEN = HIGH, VOREF output
Microcontroller data bit D9 = LOW, D11 = LOW, GEVR = 0dB, cross-channel leakage signal with VOREF output and standard voltage input on one
channel only
Microcontroller data bit D9 = HIGH, D10 = LOW, D11 = LOW, GEVR = 0dB, cross-channel leakage signal with VOREF output and standard voltage
input on one channel only, Frequency = 10kHz
Microcontroller data bit D9 = HIGH, D10 = HIGH, D11 = LOW, GEVR = 0dB, cross-channel leakage signal with VOREF output and standard voltage input on one channel only, Frequency = 10kHz
PDN = LOW, MUTEN = HIGH, MDT = muted, ripple frequency = 100Hz and ripple amplitude = 0.1Vrms on AVDD1/AVDD2/AVDD3
PDN = HIGH, MUTEN = LOW, MDT = muted, ripple frequency = 100Hz and ripple amplitude = 0.1Vrms on AVDD1/AVDD2/AVDD3
PDN = HIGH, MUTEN = HIGH, MDT D0 to D12 = LOW, ripple frequency = 100Hz and ripple amplitude = 0.1Vrms on AVDD1/AVDD2/AVDD3
NIPPON PRECISION CIRCUITS INC.—7
SM6453AB
Analog output characteristics (BEEPLO, BEEPRO)
Rating
Parameter
Symbol
BEEP output voltage
Condition
Unit
2VP-O amplitude, 50% duty,
400Hz rectangular wave
VBO
min
typ
max
− 55
− 49.3
− 44
dBv
Reference voltage characteristics (VREF1, VREF2, VBIAS)
Rating
Parameter
Symbol
Condition
Unit
min
typ
max
Reference voltage output 1
VREF1
0.45VDD1
0.5VDD1
0.55VDD1
V
Reference voltage output 2
VREF2
–
VDD1 − 0.815
–
V
Bias voltage output
VBIAS
0.45VDD1
0.5VDD1
0.55VDD1
V
Measurement circuit
*1
*4
0.1µF
33µF
+
0.01µF
*3
VDD1
VREF1
VDD1
VREF1
VREF1
VDD1
820kΩ *2
VDD2
2200pF
32
31
30
DVDD1 DVDD2
2
3
6
MCK
BEEPLO
MDT
LOUT
RSTN
MUTEN
PDN
25
24
23
220µF
AVDD2
AVDD3
22
AVSS3
ROUT
VREF1
VDD1
20
VDD1
19
18
BEEPRO
VREF2
LIN1
LIN2
11
12
AVSS1
13
10µF
RIN1
RIN2
VBIAS
14
15
16
4.7Ω
+
220µF
9
10
220µF
21
220µF
BEEPI
AVDD1
4.7Ω
0.47µF
AVSS2
0.47µF
8
16Ω
+
+
7
BSTO
16Ω
17
+
1µF
1µF
1µF
10µF
1µF
+
+
VDD2
5
26
BSTN
MLEN
+
VDD2
4
27
BSTC
NPC
SM6453
VDD2
28
+
1
29
LRMXO AGCTC
DVSS
100µF
10µF
VDD1
*1 to *4: AGC time constant setting components. Measured with *4 open circuit.
NIPPON PRECISION CIRCUITS INC.—8
SM6453AB
FUNCTIONAL DESCRIPTION
Microcontroller Interface
The SM6453AB uses a serial microcontroller interface comprising MDT (data), MCK (clock), MLEN (latch
enable).
Data format
The data transfer format is shown in figure 1.
MDT
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
MCK
MLEN
Figure 1. Microcontroller data input timing
The internal shift register shifts data on the rising edge of MCK, and the data is loaded and updated on the rising edge of MLEN (dotted lines also indicate valid data timing).
Each cycle is completed by 16 or more MCK input cycles, even if there are unused data bits.
NIPPON PRECISION CIRCUITS INC.—9
SM6453AB
Microcontroller data description
Definition: “L” = VIL1 level, “H” = VIH1 level
D7
Input select
Don't care
D8
Bass boost
mode select
Bass boost
ON/OFF
D15 D14 D13 D12 D11 D10 D9
AGC ON/OFF
MDT
D6
D5
D4
D3
D2
D1
D0
EVR gain setting
GEVR: 0dB to -80dB, MUTE
Figure 2. Microcontroller data description
■
D15 to D12: Not used (don’t care) bits. Can be either “L” or “H”.
■
D11: AGC bit. OFF when “L”, and ON when “H”. AGC = OFF when system reset (see “Automatic gain
control function”).
■
D11
AGC function
LOW
OFF
HIGH
ON
D10, D9: Bass boost control bits. Bass boost = OFF and bass boost mode = BB1 when system reset (see
“Bass boost function”).
D9
D10
Bass boost
characteristics
LOW
LOW
OFF
HIGH
LOW
BB1
HIGH
BB2
HIGH
■
D8: Input select bit. LIN1 and RIN1 when “L”, and LIN2 and RIN2 when “H”. LIN1 and RIN1 input when
system reset.
D8
Selected inputs
LOW
LIN1, RIN1
HIGH
LIN2, RIN2
Input
Input Selector Block
Output
D8=L/D8=H
LIN1
RIN1
Input
Selector
LIN1/LIN2
RIN1/RIN2
To EVR Block
LIN2
RIN2
NIPPON PRECISION CIRCUITS INC.—10
SM6453AB
D7 to D0: EVR gain control bits. MUTE when system reset.
LIN1
LIN2
Input
Selector Block
EVR Block
0dB
Gain (GEVR) :
0 to −80dB variable,
MUTE
RIN1
RIN2
Headphone
Amplifier Block
Gain (GHPA) :
+12dB fixed, MUTE
LOUT
Gain: GEVR + GHPA = GO
GO: +12dB to −68dB, MUTE
ROUT
MCK
MLEN
Microcontroller
Interface
MDT
■
Figure 3. Electronic volume gain (GEVR) setting and output voltage gain (GO)
EVR gain
(GEVR)
LOUT, ROUT gain
(GO)
D7
D6
D5
D4
D3
D2
D1
D0
HEX
0dB
+ 12dB
L
L
L
L
L
L
L
L
00
– 1dB
+ 11dB
L
L
L
L
L
L
L
H
01
– 2dB
+ 10dB
L
L
L
L
L
L
H
L
02
:
:
:
:
:
:
:
:
:
:
:
− 15dB
− 3dB
L
L
L
L
H
H
H
H
0F
− 16dB
− 4dB
L
L
L
H
L
L
L
L
10
− 17dB
− 5dB
L
L
L
H
L
L
L
H
11
:
:
:
:
:
:
:
:
:
:
:
− 63dB
− 51dB
L
L
H
H
H
H
H
H
3F
− 64dB
− 52dB
L
H
L
L
L
L
L
L
40
− 65dB
− 53dB
L
H
L
L
L
L
L
H
41
:
:
:
:
:
:
:
:
:
:
:
− 79dB
− 67dB
L
H
L
L
H
H
H
H
4F
− 80dB
− 68dB
L
H
L
H
L
L
L
L
50
MUTE
MUTE
L
H
L
H
L
L
L
H
51
MUTE
MUTE
L
H
L
H
L
L
H
L
52
:
:
:
:
:
:
:
:
:
:
:
MUTE
MUTE
H
H
H
H
H
H
H
L
FE
MUTE
MUTE
H
H
H
H
H
H
H
H
FF
NIPPON PRECISION CIRCUITS INC.—11
SM6453AB
System Reset Function (RSTN)
The system is reset using a LOW-level pulse on RSTN. After the system is reset, AGC is OFF, bass boost mode
is BB1, input selector is LIN1/RIN1, and LOUT/ROUT output voltage gain is muted.
AGC
Bass boost mode
Bass boost function
Input Select
EVR gain (GEVR)
Output gain (GO)
OFF
BB1
OFF
LIN1, RIN1
MUTE
MUTE
Bass Boost Function with Automatic Gain Control (AGC)
Equivalent circuit
240kΩ
VREF1
40kΩ
(Equivalent input
resistance:23kΩ)
C2
Lch 2
VREF1
VREF1
LOUT
VREF1
VREF1
16Ω
Headphone
Amp
0.47µF
ROUT
C1
BSTC
COUT
220µF
60kΩ
4.7Ω
(Equivalent input
resistance:23kΩ)
*2
CINL2
1µF
Bass
Boost
Amp
32kΩ
40kΩ
VREF1
LIN2
*1
LRMXO
AGCTC
*1
33µF
VDD
AGC Amp
AGC Block
VREF1
*1
LIN1
2kΩ
R1L
EVR
Block
RIN
820kΩ
Lch 1
240kΩ
60kΩ
*1
CINL1
1µF
R3 *4
R2
*2
2200pF
BSTN
VREF1
0.1µF
RIN2
Input Selector
Rch 2
10kΩ
*2
CINR2
1µF
0.01µF
RIN1
Headphone
Amp
COUT
220µF
BSTO
Rch 1
*3
R1R
EVR
Block
RIN
4.7Ω
R1
*2
CINR1
1µF
32kΩ
60kΩ
16Ω
Bass Boost Block
0.47µF
ROUT
ROUT
60kΩ
VREF1 VREF1
*1: From “Measurement circuit”. Adjustment AGC detection level and time constant.
*2: CINR1 = CINL1, CINR2 = CINL2 → CIN
*3: RIN1 = LIN1 → R1 = (R1R/2 + R1L/2) = 20kΩ
*4: BB1 → R3 = 15kΩ, BB2 → R3 = 60kΩ
NIPPON PRECISION CIRCUITS INC.—12
SM6453AB
Bass boost function (BSTO, BSTN, BSTC)
The bass boost characteristic (BB1, BB2) is selected using bit D10. The left-channel and right-channel bass
components are mixed and amplified, and then added to the headphone driver amplifier. A capacitor (0.1µF std)
connected between BSTC and VREF1 forms a lowpass filter through which the signal from the EVR block
passes, boosting the bass component, which is then added to the original signal.
Bass boost examples
IC internal components are RIN = 23kΩ, R1 = 20kΩ, R2 = 10kΩ, R3 = 15kΩ (BB1) or 60kΩ (BB2). The bass
boost characteristic also depends on the external resistor and capacitor components connected between BSTO
and BSTN, as indicated below.
■
Example 1
C1 = 0.1µF, C2 = 2200pF, CIN = 1µF, COUT = 220µF, ROUT = 16Ω (Measurement circuit)
15
BB2
10
[dBr]
5
BB1
0
BB OFF
-5
-10
-15
■
10
100
1000
Frequency [Hz]
10000
Example 2
C1 = 0.1µF, C2 = 0.01µF, CIN = 1µF, COUT = 220µF, ROUT = 16Ω
15
BB2
10
[dBr]
5
BB1
0
BB OFF
-5
-10
-15
10
100
1000
Frequency [Hz]
10000
NIPPON PRECISION CIRCUITS INC.—13
SM6453AB
■
Example 3
C1 = 0.1µF, C2 = 0.047µF, CIN = 1µF, COUT = 220µF, ROUT = 16Ω
15
BB2
10
BB1
[dBr]
5
0
BB OFF
-5
-10
-15
■
10
100
1000
Frequency [Hz]
10000
Example 4
C1 = 0.22µF, C2 = 6800pF, CIN = 0.47µF, COUT = 47µF, ROUT = 16Ω, 2700Ω resistor connected between
BSTN and VREF1
Note that when the output coupling capacitance COUT is small, the bass signal component margin available
before reaching the bass output saturation level is considerably reduced.
15
[dBr]
10
5
0
–5
–10
–15
–20
–25
–30
–35
10
BB2
BB1
BB OFF
100
1000
10000
Frequency [Hz]
Automatic gain control (AGC) function
The AGC function is selected using bit D11. When bass boost is on, whenever the magnitude of either the positive or negative output voltage peak value of LOUT or ROUT exceeds VREF1 + 0.48V (typ), half-wave rectification starts. The resulting detected and smoothed DC potential is compared with the VREF1 potential, and
the comparator output signal is used to control the reduction in bass boost gain, thereby increasing the headphone amplifier output bass clip margin.
NIPPON PRECISION CIRCUITS INC.—14
SM6453AB
Power-down Function (PDN)
The power-down function is selected when PDN goes LOW. This reduces the power consumption, while
LOUT and ROUT become high impedance. A pull-down resistor connected to PDN is recommended.
Mute Function
Mute function (MUTEN)
The mute function is selected when MUTEN goes LOW. At initial startup, it is recommended that a delay of
2.5 seconds (typ) occur before MUTEN goes HIGH to prevent pop-noise output on LOUT and ROUT that can
occur when muting is released and after power-down is released (see mute release timing in figures 4 and 5).
Note that when muting using the MUTEN pin, outputs LOUT and ROUT do not become high impedance. A
pull-down resistor connected to MUTEN is recommended.
Reset
2.5 [sec]
RSTN
PDN
MUTEN
MDT
LOUT/ROUT
Current consumption
MUTE OFF
High Impedance
Medium Impedance
High Impedance
Power Down
MUTE
Low Impedance
(Power ON)
MUTE ON
MUTE OFF
Figure 4. Initial startup recommended mute release timing example 1
2.5 [sec]
Reset
RSTN
PDN
MUTEN
MDT
LOUT/ROUT
Current consumption
MUTE OFF
High Impedance
Medium Impedance
Power Down
MUTE
Low Impedance
(Power ON)
MUTE ON
MUTE OFF
Figure 5. Initial startup recommended mute release timing example 2
Mute function (Microcontroller Data)
Mute is ON when Microcontroller Data D0 to D7 = LOW. Output impedance is HIGH when Microcontroller
Data D0 to D7 = LOW, Mute function.
Beep Signal Input/Output (BEEPI, BEEPLO, BEEPRO)
The beep signal is a constant-current output signal on BEEPLO and BEEPRO in response to an input signal on
BBEPI. The beep signal input/output circuit should be used when MUTEN is HIGH, when muting using the
attenuation data bits D0 to D7, and during power-down.
NIPPON PRECISION CIRCUITS INC.—15
SM6453AB
TYPICAL RESPONSE
VDD1 = VDD2 = 2.0V, analog input amplitude = 0.025Vrms, input frequency = 1kHz, Ta = 25°C, Measurement
circuit, PDN = HIGH, MUTEN = HIGH, MDT D0 to D12 = LOW, unless otherwise noted
10
10
9
0.5mW+0.5mW (16Ω)
7
THD+N [%]
supply current [mA]
8
6
5
4
1
0.5mW+0.5mW (16Ω)
3
No signal (16Ω)
2
1
10mW+10mW (16Ω)
0
1.5
2.0
2.5
3.0
supply voltage:VDD1 [V]
3.5
0.1
1.5
4.0
Figure 6. Current consumption vs. Supply voltage
2.5
3.0
supply voltage:VDD1 [V]
3.5
4.0
Figure 7. THD+N vs. Supply voltage
100
10
10
THD+N [%]
100
THD+N [%]
2.0
1
1
0.1
0.001
0.01
0.1
1
output power [mW]
10
0.1
0.001
100
0.01
0.1
1
input level [V]
Figure 8. THD+N vs. Output power
Figure 9. THD+N vs. Input voltage
100
100
90
80
output power [mW]
output power [mW]
10
1
0.1
0.01
70
60
50
40
30
20
0.001
10
0.0001
0.001
0.01
0.1
input level [V]
Figure 10. THD+N vs. Input voltage
1
0
1.5
2.0
2.5
3.0
supply voltage:VDD1 [V]
3.5
4.0
Figure 11. Maximum output power vs. Supply
voltage
NIPPON PRECISION CIRCUITS INC.—16
SM6453AB
100
30
cross talk:CT1, CT2, CT3 [dB]
GEVR = 0dB
noise level:VNS [µV]
25
GEVR = –12dB
20
15
10
5
0
1.5
2.0
2.5
3.0
supply voltage:VDD1 [V]
3.5
60
50
40
BB2:CT3
30
BB1:CT2
20
10
2.0
2.5
3.0
supply voltage:VDD1 [V]
3.5
4.0
12
GEVR = 0dB (GO = +12dB)
2
GEVR = –20dB (GO = –8dB)
–8
GEVR = –40dB (GO = –28dB)
GEVR = –60dB (GO = –48dB)
GEVR = –80dB (GO = –68dB)
–18
–28
–38
–48
–58
MUTE
–68
2.0
2.5
3.0
supply voltage:VDD1 [V]
3.5
0
4.0
Figure 14. Absolute gain vs. Supply voltage
–10
–20
–30
–40
GEVR [dB]
–50
–60
–70
–80
Figure 15. Output voltage gain vs. EVR gain setting
15
2.0
BB2
14
1.5
13
1.0
12
0.5
[dBr]
gain error:GERR [dB]
BB OFF:CT1
70
Figure 13. Channel separation vs. Supply voltage
GO [dB]
Absolute gain [dB]
30
20
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
1.5
80
0
1.5
4.0
Figure 12. Noise level vs. Supply voltage
90
0.0
11
10
9
–0.5
8
–1.0
BB1
7
–0.5
6
–2.0
0
–10
–20
–30
–40
GEVR [dB]
–50
Figure 16. Gain error
–60
–70
–80
5
1.5
2.0
2.5
3.0
supply voltage:VDD1 [V]
3.5
4.0
Figure 17. Bass boost gain vs. Supply voltage
NIPPON PRECISION CIRCUITS INC.—17
SM6453AB
0.70
+20
BB2
+10
0.65
AGC voltage:VAGC [V]
+15
BB1
dBr
+5
+0
BB OFF
–5
–10
0.60
0.55
0.50
0.45
0.40
–15
20
50
100
200
500
1k
2k
5k
10k
0.35
1.5
20k
2.0
2.5
3.0
supply voltage:VDD1 [V]
Hz
Figure 18. Frequency response vs. Bass boost
3.5
4.0
Figure 19. AGC level vs. Supply voltage
–40
0
VDD1 = 1.8V
BEEP out level:VBO [dBv]
BEEP out level:VBO [dBv]
VDD1 = 3.6V
–50
–10
–20
–30
–40
BEEPI = 2.0VP-0
–50
–60
1.5
2.0
2.5
3.0
supply voltage:VDD1 [V]
3.5
Figure 20. Beep sound output level vs. Supply
voltage
4.0
–60
–70
–80
–90
–100
–110
0
0.5
1.0
1.5
2.0
2.5
BEEPI level [VP-O]
3.0
3.5
4.0
Figure 21. Beep sound output level vs. Beep input
level
NIPPON PRECISION CIRCUITS INC.—18
SM6453AB
NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to
improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for
the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits
are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision
Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification.
The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or
malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter,
including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or
indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies.
NIPPON PRECISION CIRCUITS INC.
4-3, Fukuzumi 2-chome, Koto-ku,
Tokyo 135-8430, Japan
Telephone: +81-3-3642-6661
Facsimile: +81-3-3642-6698
http://www.npc.co.jp/
Email: [email protected]
NC0024AE
2002.04
NIPPON PRECISION CIRCUITS INC.—19