TI SN74ACT00-Q1

SCLS517 − AUGUST 2003
D Qualification in Accordance With
D PACKAGE
(TOP VIEW)
AEC-Q100†
D Qualified for Automotive Applications
D Customer-Specific Configuration Control
D
D
D
D
D
1A
1B
1Y
2A
2B
2Y
GND
Can Be Supported Along With
Major-Change Approval
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
4.5-V to 5.5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Max tpd of 8 ns at 5 V
Inputs Are TTL-Voltage Compatible
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
4B
4A
4Y
3B
3A
3Y
† Contact factory for details. Q100 qualification data available on
request.
description/ordering information
The SN74ACT00 contains four independent 2-input NAND gates. Each gate performs the Boolean function of
Y = A S B or Y = A + B in positive logic.
ORDERING INFORMATION
TA
ORDERABLE
PART NUMBER
PACKAGE‡
TOP-SIDE
MARKING
−40°C to 105°C
SOIC − D
Tape and reel
SN74ACT00TDRQ1
ACT00TQ1
‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
FUNCTION TABLE
(each gate)
INPUTS
A
B
OUTPUT
Y
H
H
L
L
X
H
X
L
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2003, Texas Instruments Incorporated
!"# $"%&! '#(
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#- && $##(
POST OFFICE BOX 655303
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1
SCLS517 − AUGUST 2003
logic diagram, each gate (positive logic)
A
Y
B
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA
Package thermal impedance, θJA (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN
MAX
4.5
5.5
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
Input voltage
0
VO
IOH
Output voltage
0
IOL
∆t/∆v
High-level input voltage
2
UNIT
V
V
0.8
V
VCC
VCC
V
High-level output current
−24
mA
Low-level output current
24
mA
8
ns/V
Input transition rise or fall rate
V
TA
Operating free-air temperature
−40
105
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2
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SCLS517 − AUGUST 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
IOH = −50 µA
A
VOH
IOH = −24 mA
IOL = 50 µA
A
VOL
IOL = 24 mA
II
ICC
VI = VCC or GND
VI = VCC or GND,
∆ICC†
One input at 3.4 V,
Other inputs at GND or VCC
IO = 0
MIN
TA = 25°C
TYP
MAX
MIN
4.5 V
4.4
4.49
4.4
5.5 V
5.4
5.49
5.4
4.5 V
3.86
5.5 V
4.86
MAX
UNIT
V
3.7
4.7
4.5 V
0.001
0.1
0.1
5.5 V
0.001
0.1
0.1
4.5 V
0.36
0.5
5.5 V
0.36
0.5
5.5 V
±0.1
±1
µA
5.5 V
2
40
µA
1.6
mA
5.5 V
0.6
Ci
VI = VCC or GND
5V
2.6
† This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.
V
pF
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
tPLH
tPHL
FROM
(INPUT)
TO
(OUTPUT)
A or B
Y
MIN
TA = 25°C
TYP
MAX
MIN
MAX
1.5
5.5
9
1
9.5
1.5
4
7
1
8
UNIT
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
CL = 50 pF,
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
f = 1 MHz
TYP
UNIT
40
pF
3
SCLS517 − AUGUST 2003
PARAMETER MEASUREMENT INFORMATION
TEST
3V
S1
tPLH/tPHL
1.5 V
Input
Open
1.5 V
0V
tPHL
tPLH
2 × VCC
From Output
Under Test
CL = 50 pF
(see Note A)
500 Ω
S1
Open
In-Phase
Output
50% VCC
tPLH
tPHL
500 Ω
Out-of-Phase
Output
LOAD CIRCUIT
VOH
50% VCC
VOL
50% VCC
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
4
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• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
18-May-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
SN74ACT00TDRQ1
NRND
SOIC
D
Pins Package Eco Plan (2)
Qty
14
2500
TBD
Lead/Ball Finish
Call TI
MSL Peak Temp (3)
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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