TI 74ACT11810

SCAS211 − MARCH 1990 − REVISED APRIL 1993
•
•
•
•
•
•
D OR N PACKAGE
(TOP VIEW)
Inputs Are TTL-Voltage Compatible
Flow-Through Architecture to Optimize
PCB Layout
Center-Pin VCC and GND Configurations to
Minimize High-Speed Switching Noise
EPICt (Enhanced-Performance Implanted
CMOS) 1-mm Process
500-mA Typical Latch-Up Immunity at
125°C
Package Options Include Plastic SmallOutline Packages and Standard Plastic
300-mil DIPs
1A
1Y
2Y
GND
GND
3Y
4Y
4B
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
1B
2A
2B
VCC
VCC
3A
3B
4A
description
This device contains four independent Exclusive-NOR gates. They perform the Boolean functions Y = A⊕B =
(A + B) • (A + B) in positive logic.
A common application is a true/complement element. If one of the inputs is high, the other input will be
reproduced in true form at the output. If one of the inputs is low, the signal on the other input will be reproduced
inverted at the output.
The 74ACT11810 is characterized for operation from − 40°C to 85°C.
FUNCTION TABLE
INPUTS
A
B
OUTPUT
Y
L
L
H
L
H
L
H
L
L
H
H
H
EPIC is a trademark of Texas Instruments Incorporated.
Copyright  1993, Texas Instruments Incorporated
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1
SCAS211 − MARCH 1990 − REVISED APRIL 1993
logic symbol†
1
1A
logic diagram (positive logic)
=1
16
1B
15
2A
14
2B
11
3A
10
3B
9
4A
3
6
7
8
4B
2
1A
1Y
1B
2A
2Y
2B
3A
3Y
3B
4A
4Y
4B
11
16
15
14
11
10
9
8
2
3
6
7
1Y
2Y
3Y
4Y
† This symbol is in accordance with ANSI/IEEE Std 91-1984
andIEC Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 100 mA
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
} Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
recommended operating conditions
2
MIN
MAX
4.5
5.5
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
Input voltage
0
VO
IOH
Output voltage
0
High-level input voltage
2
UNIT
V
V
0.8
V
VCC
VCC
V
High-level output current
−24
mA
IOL
Dt/Dv
Low-level output current
24
mA
0
10
ns/V
TA
Operating free-air temperature
− 40
85
°C
Input transition rise or fall rate
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
V
SCAS211 − MARCH 1990 − REVISED APRIL 1993
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
4.5 V
4.4
4.4
5.5 V
5.4
5.4
4.5 V
3.94
3.8
IOH = − 24 mA
5.5 V
4.94
4.8
IOH = − 75 mA†
5.5 V
IOH = − 50 mA
A
VOH
II
ICC
DICC‡
IOL = 24 mA
IOL = 75 mA†
VI = VCC or GND
VI = VCC or GND,
MIN
MAX
V
0.1
0.1
5.5 V
0.1
0.1
4.5 V
0.36
0.44
5.5 V
0.36
0.44
5.5 V
IO = 0
One input at 3.4 V,
Other inputs at GND or VCC
UNIT
3.85
4.5 V
IOL = 50 mA
A
VOL
TA = 25°C
TYP
MAX
VCC
V
1.65
5.5 V
± 0.1
±1
mA
5.5 V
4
4
mA
5.5 V
0.9
1
mA
Ci
VI = VCC or GND
5V
3.5
† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
‡ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
pF
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A or B
(other input low)
Y
tPLH
tPHL
A or B
(other input high)
Y
MIN
TA = 25°C
TYP
MAX
MIN
MAX
1.9
4.8
7.2
1.9
8.3
1.9
4.9
7.1
1.9
8.3
1.9
4.8
7.2
1.9
8.3
1.9
4.9
7.1
1.9
8.3
UNIT
ns
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
CL = 50 pF,
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
f = 1 MHz
TYP
UNIT
26
pF
3
SCAS211 − MARCH 1990 − REVISED APRIL 1993
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
500 Ω
LOAD CIRCUIT
3V
Input
(see Note B)
50% VCC
50% VCC
0
tPHL
tPLH
In-Phase
Output
50% VCC
VOH
50% VCC
VOL
tPLH
tPHL
Out-of-Phase
Output
50% VCC
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
4
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jun-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
74ACT11810D
OBSOLETE
SOIC
D
16
TBD
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74ACT11810DR
OBSOLETE
SOIC
D
16
TBD
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74ACT11810DR
OBSOLETE
SOIC
D
16
TBD
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74ACT11810N
OBSOLETE
PDIP
N
16
TBD
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74ACT11810N
OBSOLETE
PDIP
N
16
TBD
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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