DS7800/DS8800 Dual Voltage Level Translator General Description Features The DS7800/DS8800 are dual voltage translators designed for interfacing between conventional TTL or LS voltage levels and those levels associated with high impedance junction or MOS REF-type devices. The design allows the user a wide latitude in his selection of power supply voltages, thus providing custom control of the output swing. The translator is especially useful in analog switching; and since low power dissipation occurs in the ‘‘off’’ state, minimum system power is required. Y Y Y Y Y 31 volt (max) output swing 1 mW power dissipation in normal state Standard 5V power supply Temperature range: b 55§ C to a 125§ C DS7800 DS8800 0§ C to a 70§ C Compatible with all MOS devices Schematic and Connection Diagrams Metal Can Package TL/F/5827 – 2 Top View Order Number DS7800H or DS8800H See NS Package Number H10C TL/F/5827 – 1 Typical Applications Bipolar to MOS Interfacing 4-Channel Analog Switch TL/F/5827 – 4 TL/F/5827 – 3 *Analog signals within the range of a 8V to b 8V. C1995 National Semiconductor Corporation TL/F/5827 RRD-B30M105/Printed in U. S. A. DS7800/DS8800 Dual Voltage Level Translator June 1986 Absolute Maximum Ratings (Note 1) Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. VCC Supply Voltage Supply Voltage, VCC DS7800 DS8800 Temperature (TA) DS7800 DS8800 7.0V V2 Supply Voltage b 30V V3 Supply Voltage 30V V3 – V2 Voltage Differential 40V Input Voltage 5.5V Storage Temperature Min Max Units 4.5 4.75 5.5 5.25 V V b 55 a 125 a 70 §C §C 0 b 65§ C to a 150§ C Lead Temperature (Soldering, 4 seconds) 260§ C Maximum Power Dissipation* at 25§ C Metal Can (TO-5) Package 690 mW *Derate metal can package 4.6 mW/§ C above 25§ C. Electrical Characteristics (Notes 2 and 3) Symbol Parameter Conditions VIH Logical ‘‘1’’ Input Voltage VCC e Min VIL Logical ‘‘0’’ Input Voltage VCC e Min IIH Logical ‘‘1’’ Input Current VCC e Max Min Max Units 0.8 V 2.0 V VIN e 2.4V 5 mA VIN e 5.5V 1 mA b 0.4 mA IIL Logical ‘‘0’’ Input Current VCC e Max, VIN e 0.4V IOL Output Sink Current VCC e Min, VIN e 2V, DS7800 1.6 V3 Open DS8800 2.3 IOH Typ (Note 6) b 0.2 Output Leakage Voltage VCC e Max, VIN e 0.8V (Notes 4 and 7) RO Output Collector Resistor TA e 25§ C VOL Logical ‘‘0’’ Output Voltage VCC e Min, VIN e 2.0V (Note 7) ICC(MAX) Power Supply Current Output ‘‘ON’’ Per Gate VCC e Max, VIN e 4.5V (Note 5) ICC(MIN) Power Supply Current Output ‘‘OFF’’ Per Gate VCC e Max, VIN e 0V (Note 5) 11.5 mA mA 16.0 10 mA 20.0 kX V2 a 2.0 V 0.85 1.6 mA 0.22 0.41 mA Switching Characteristics TA e 25§ C, nominal power supplies unless otherwise noted Parameter Conditions Min Typ Max Units tpd0 Symbol Transition Time to Logical ‘‘0’’ Output TA e 25§ C, C e 15 pF (Note 8) 25 70 125 ns tpd1 Transition Time to Logical ‘‘1’’ Output TA e 25§ C, C e 15 pF (Note 9) 25 62 125 ns Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation. Note 2: Unless otherwise specified min/max limits apply across the b 55§ C to a 125§ C temperature range for the DS7800 and across the 0§ C to a 70§ C range for the DS8800. Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown as max or min on absolute value basis. Note 4: Current measured is drawn from V3 supply. Note 5: Current measured is drawn from VCC supply. Note 6: All typical values are measured at TA e 25§ C with VCC e 5.0V, V2 e b 22V, V3 e a 8V. Note 7: Specification applies for all allowable values of V2 and V3. Note 8: Measured from 1.5V on input to 50% level on output. Note 9: Measured from 1.5V on input to logic ‘‘0’’ voltage, plus 1V. 2 Since this current is relatively constant, the collector of Q2 acts as a constant current source for the output stage. Logic inversion is performed since logical ‘‘1’’ input voltages cause current to be supplied to Q2 and Q3. And when Q3 turns on the output voltage drops to the logical ‘‘0’’ level. The reason for the PNP current source, Q2, is so that the output stage can be driven from a high impedance. This allows voltage V2 to be adjusted in accordance with the application. Negative voltages to b25V can be applied to V2. Since the output will neither source nor sink large amounts of current, the output voltage range is almost exclusively dependent upon the values selected for V2 and V3. Maximum leakage current through the output transistor Q3 is specified at 10 mA under worst-case voltage between V2 and V3. This will result in a logical ‘‘1’’ output voltage which is 0.2V below V3. Likewise the clamping action of diodes D4, D5, and D6, prevents the logical ‘‘0’’ output voltage from falling lower than 2V above V2, thus establishing the ouput voltage swing at typically 2 volts less than the voltage separation between V2 and V3. Theory of Operation The two input diodes perform the AND function on TTL input voltage levels. When at least one input voltage is a logical ‘‘0’’, current from VCC (nominally 5.0V) passes through R1 and out the input(s) which is at the low voltage. Other than small leakage currents, this current drawn from VCC through the 20 kX resistor is the only source of power dissipation in the logical ‘‘1’’ output state. When both inputs are at logical ‘‘1’’ levels, current passes through R1 and diverts to transistor Q1, turning it on and thus pulling current through R2. Current is then supplied to the PNP transistor, Q2. The voltage losses caused by current through Q1, D3, and Q2 necessitate that node P reach a voltage sufficient to overcome these losses before current begins to flow. To achieve this voltage at node P, the inputs must be raised to a voltage level which is one diode potential lower than node P. Since these levels are exactly the same as those experienced with conventional TTL, the interfacing with these types of circuits is achieved. Transistor Q2 provides ‘‘constant current switching’’ to the output due to the common base connection of Q2. When at least one input is at the logical ‘‘0’’ level, no current is delivered to Q2; so that its collector supplies essentially zero current to the output stage. But when both inputs are raised to a logical ‘‘1’’ level current is supplied to Q2. Selecting Power Supply Voltage The graph shows the boundary conditions which must be used for proper operation of the unit. The range of operation for power supply V2 is shown on the X axis. It must be between b25V and b8V. The allowable range for power supply V3 is governed by supply V2. With a value chosen for V2, V3 may be selected as any value along a vertical line passing through the V2 value and terminated by the boundaries of the operating region. A voltage difference between power supplies of at least 5V should be maintained for adequate signal swing. TL/F/5827 – 5 Switching Time Waveforms TL/F/5827 – 6 3 Physical Dimensions inches (millimeters) Metal Can Package (H) Order Number DS7800H or DS8800H NS Package Number H10C LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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