ADC0841 8-Bit µP Compatible A/D Converter General Description The ADC0841 is a CMOS 8-bit successive approximation A/D converter. Differential inputs provide low frequency input common mode rejection and allow offsetting the analog range of the converter. In addition, the reference input can be adjusted enabling the conversion of reduced analog ranges with 8-bit resolution. The A/D is designed to operate with the control bus of a variety of microprocessors. TRI-STATE ® output latches that directly drive the data bus permit the A/D to be configured as a memory location or I/O device to the microprocessor with no interface logic necessary. Features n n n n n n Operates ratiometrically or with 5 VDC voltage reference No zero or full-scale adjust required Internal clock 0V to 5V input range with single 5V power supply 0.3" standard width 20-pin package 20 Pin Molded Chip Carrier Package Key Specifications n n n n n Resolution: 8 Bits Total Unadjusted Error: ± 1⁄2 LSB and ± 1 LSB Single Supply: 5 VDC Low Power: 15 mW Conversion Time: 40 µs n Easy interface to all microprocessors Block and Connection Diagrams DS008557-1 Dual-In-Line Package (N) Molded Chip Carrier Package (V) DS008557-2 (N.C.-No Connection) DS008557-3 Top View Top View TRI-STATE ® is a registered trademark of National Semiconductor Corporation. NSC800™ is a trademark of National Semiconductor Corporation. © 1999 National Semiconductor Corporation DS008557 www.national.com ADC0841 8-Bit µP Compatible A/D Converter May 1998 Absolute Maximum Ratings (Notes 1, 2) Lead Temp. (Soldering, 10 seconds) Dual-In-Line Package (Plastic) Molded Chip Carrier Package Vapor Phase (60 seconds) Infrared (15 seconds) ESD Susceptibility (Note 10) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) Voltage Logic Control Inputs At Other Inputs and Outputs Input Current Per Pin (Note 3) Input Current Per Package (Note 3) Storage Temperature Package Dissipation at TA = 25˚C 6.5V Operating Conditions −0.3V to VCC+0.3V −0.3V to VCC+0.3V ± 5 mA ± 20 mA −65˚C to +150˚C 875 mW 260˚C 215˚C 220˚C 800V (Notes 1, 2) Supply Voltage (VCC) Temperature Range ADC0841BCN, ADC0841CCN ADC0841BCV, ADC0841CCV 4.5 VDC to 6.0 VDC TMIN≤TA≤TMAX 0˚C≤TA≤70˚C −40˚C≤TA≤85˚C Electrical Characteristics The following specifications apply for VCC = 5 VDC unless otherwise specified. Boldface limits apply from TMIN to TMAX; all other limits TA = Tj = 25˚C. ADC0841BCN, ADC0841CCN ADC0841BCV, ADC0841CCV Parameter Conditions Typ Tested Design (Note 6) Limit Limit Units (Note 7) (Note 8) ± 1⁄2 ±1 ± 1⁄2 ±1 LSB 2.4 1.2 1.1 kΩ 2.4 5.4 5.9 kΩ (Note 5) VCC+0.05 VCC+0.05 V (Note 5) GND−0.05 GND−0.05 V ± 1⁄4 ± 1⁄8 ± 1⁄4 ± 1⁄8 LSB CONVERTER AND MULTIPLEXER CHARACTERISTICS Maximum Total VREF = 5.00 VDC Unadjusted Error (Note 4) ADC0841BCN, BCV ADC0841CCN, CCV Minimum Reference LSB Input Resistance Maximum Reference Input Resistance Maximum Common-Mode Input Voltage Minimum Common-Mode Input Voltage DC Common-Mode Error Differential Mode Power Supply Sensitivity VCC = 5V ± 5% ± 1/16 ± 1/16 LSB Electrical Characteristics The following specifications apply for VCC = 5 VDC unless otherwise specified. Boldface limits apply from TMIN to TMAX; all other limits TA = Tj = 25˚C. ADC0841BCN, ADC0841CCN ADC0841BCV, ADC0841CCV Symbol Parameter Conditions Typ Tested Design (Note 6) Limit Limit Units (Note 7) (Note 8) VCC = 5.25V 2.0 2.0 V VCC = 4.75V 0.8 0.8 V 1 µA DIGITAL AND DC CHARACTERISTICS VIN(1) Logical “1” Input Voltage (Min) VIN(0) Logical “0” Input Voltage (Max) IIN(1) Logical “1” Input VIN = 5.0V 0.005 Current (Max) www.national.com 2 Electrical Characteristics (Continued) The following specifications apply for VCC = 5 VDC unless otherwise specified. Boldface limits apply from TMIN to TMAX; all other limits TA = Tj = 25˚C. ADC0841BCN, ADC0841CCN ADC0841BCV, ADC0841CCV Symbol Parameter Conditions Typ Tested Design (Note 6) Limit Limit (Note 7) (Note 8) Units DIGITAL AND DC CHARACTERISTICS IIN(0) Logical “0” Input VIN = 0V −0.005 −1 µA V Current (Max) VOUT(1) Logical “1” VCC = 4.75V Output Voltage (Min) IOUT = −360 µA IOUT = −10 µA 2.8 2.4 4.6 4.5 V VCC = 4.75V IOUT = 1.6 mA 0.34 0.4 V VOUT(0) Logical “0” IOUT TRI-STATE Output VOUT = 0V −0.01 −0.3 −3 µA Current (Max) VOUT = 5V VOUT = 0V 0.01 0.3 3 µA −14 −7.5 −6.5 mA VOUT = VCC 16 9.0 8.0 mA CS = 1, VREF Open 1 2.3 2.5 mA Output Voltage (Max) ISOURCE Output Source Current (Min) ISINK Output Sink Current (Min) ICC Supply Current (Max) AC Characteristics The following specifications apply for VCC = 5VDC, tr = tf = 10 ns unless otherwise specified. Boldface limits apply from TMIN to TMAX; all other limits TA = TJ = 25˚C. Tested Symbol Parameter tC Maximum Conversion Time (See Graph) tW(WR) Minimum WR Pulse Width tACC Maximum Access Time (Delay from Falling Edge of RD to Output Data Valid) t1H, t0H tWI, tRI Conditions (Note 9) CL = 100 pF Limit Limit (Note 6) (Note 7) (Note 8) 60 Units 30 40 50 150 ns 145 225 ns 125 Edge of RD to Hi-Z State) (Note 9) CL = 10 pF, RL = 10k, tr = 20 ns (Note 9) Maximum Delay from Falling Edge of WR or RD to (Note 9) 200 TRI-STATE Control (Maximum Delay from Rising Design Typ 200 400 µs ns ns Reset of INTR CIN Capacitance of Logic Inputs 5 pF COUT Capacitance of Logic Outputs 5 pF Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions. Note 2: All voltages are measured with respect to the ground pins. Note 3: During over-voltage conditions (VIN < 0V and VIN > VCC) the maximum input current at any one pin is ± 5 mA. If the current is limited to ± 5 mA at all the pins no more than four pins can be in this condition in order to meet the Input Current Per Package ( ± 20 mA) specification. Note 4: Total unadjusted error includes offset, full-scale, and linearity. Note 5: For VIN (−) ≥ VIN (+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input, which will forward-conduct for analog input voltages one diode drop below ground or one diode drop greater than VCC supply. Be careful during testing at low VCC levels (4.5V), as high level analog inputs (5V) can cause this input diode to conduct, especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows 50 mV forward bias of either diode. This means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV, the output code will be correct. To achieve an absolute 0 VDC to 5 VDC input voltage range will therefore require a minimum supply voltage of 4.950 VDC over temperature variations, initial tolerance and loading. Note 6: Typicals are at 25˚C and represent most likely parametric norm. Note 7: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 8: Design limits are guaranteed but not 100% production tested. These limits are not used to calculate outgoing quality levels. Note 9: The temperature coefficient is 0.3%/˚C. Note 10: Human body model, 100 pF discharged through 1.5 kΩ resistor. 3 www.national.com Timing Diagram DS008557-9 Note 11: Read strobe must occur at least 600 ns after the assertion of interrupt to guarantee reset of INTR. Typical Performance Characteristics Logic Input Threshold Voltage vs Supply Voltage Output Current vs Temperature DS008557-24 DS008557-23 Linearity Error vs VREF Power Supply Current vs Temperature Conversion Time vs VSUPPLY DS008557-25 Conversion Time vs Temperature DS008557-27 DS008557-26 DS008557-28 www.national.com 4 Typical Performance Characteristics (Continued) Unadjusted Offset Error vs VREF Voltage DS008557-22 TRI-STATE Test Circuits and Waveforms t1H, CL = 10 pF t1H DS008557-6 DS008557-5 tr = 20 ns t0H, CL = 10 pF t0H DS008557-8 DS008557-7 tr = 20 ns 5 www.national.com Functional Block Diagram DS008557-10 www.national.com 6 where fCM is the frequency of the common-mode signal, Vpeak is its peak voltage value and tC is the conversion time. Functional Description A conversion is initiated via the CS and WR lines. If the data from a previous conversion is not read, the INTR line will be low. The falling edge of WR will reset the INTR line high and ready the A/D for a conversion cycle. The rising edge of WR starts a conversion. After the conversion cycle (tC ≤ 60 µsec), which is set by the internal clock frequency, the digital data is transferred to the output latch and the INTR is asserted low. Taking CS and RD low resets INTR output high and transfers the conversion result on the output data lines (DB0–DB7). For a 60 Hz common-mode signal to generate a 1⁄4 LSB error (≈ 5 mV) with the converter running at 40 µS, its peak value would have to be 5.43V. This large common-mode signal is much greater than that generally found in a well designed data acquisition system. 2.2 Input Current Due to the sampling nature of the analog inputs, short duration spikes of current enter the “+” input and exit the “−” input at the clock edges during the actual conversion. These currents decay rapidly and do not cause errors as the internal comparator is strobed at the end of a clock period. Bypass capacitors at the inputs will average these currents and cause an effective DC current to flow through the output resistance of the analog signal source. Bypass capacitors should not be used if the source resistance is greater than 1 kΩ. An op amp RC active low pass filter can provide both impedance buffering and noise filtering should a high impedance signal source be required. Applications Information 1.0 REFERENCE CONSIDERATIONS The voltage applied to the reference input of this converter defines the voltage span of the analog input (the difference between VIN(MAX) and VIN(MIN)) over which the 256 possible output codes apply. The device can be used in either ratiometric applications or in systems requiring absolute accuracy. The reference pin must be connected to a voltage source capable of driving the minimum reference input resistance of 1.1 kΩ. This pin is the top of a resistor divider string used for the successive approximation conversion. In a ratiometric system (Figure 1a), the analog input voltage is proportional to the voltage used for the A/D reference. This voltage is typically the system power supply, so the VREF pin can be tied to VCC. This technique relaxes the stability requirements of the system reference as the analog input and A/D reference move together maintaining the same output code for a given input condition. For absolute accuracy (Figure 1b), where the analog input varies between very specific voltage limits, the reference pin can be biased with a time and temperature stable voltage source. The LM385 and LM336 reference diodes are good low current devices to use with this converter. The maximum value of the reference is limited to the VCC supply voltage. The minimum value, however, can be quite small (see Typical Performance Characteristics) to allow direct conversions of transducer outputs providing less than a 5V output span. Particular care must be taken with regard to noise pickup, circuit layout and system error voltage sources when operating with a reduced span due to the increased sensitivity of the converter (1 LSB equals VREF/256). 3.0 OPTIONAL ADJUSTMENTS 3.1 Zero Error The zero of the A/D does not require adjustment. If the minimum analog input voltage value, VIN(MIN), is not ground, a zero offset can be done. The converter can be made to output 0000 0000 digital code for this minimum input voltage by biasing the VIN (−) input at this VIN(MIN) value. The zero error of the A/D converter relates to the location of the first riser of the transfer function and can be measured by grounding the V− input and applying a small magnitude positive voltage to the V+ input. Zero error is the difference between actual DC input voltage which is necessary to just cause an output digital code transition from 0000 0000 to 0000 0001 and the ideal 1⁄2 LSB value (1⁄2 LSB = 9.8 mV for VREF = 5.000 VDC). 3.2 Full-Scale The full-scale adjustment can be made by applying a differential input voltage which is 1 1⁄2 LSB down from the desired analog full-scale voltage range and then adjusting the magnitude of the VREF input for a digital output code changing from 1111 1110 to 1111 1111. 2.0 THE ANALOG INPUTS 3.3 Adjusting for an Arbitrary Analog Input Voltage Range If the analog zero voltage of the A/D is shifted away from ground (for example, to accommodate an analog input signal which does not go to ground), this new zero reference should be properly adjusted first. A voltage which equals this desired zero reference plus 1⁄2 LSB (where the LSB is calculated for the desired analog span, 1 LSB = analog span/256) is applied to the “+” input (VIN(+)) and the zero reference voltage at the “−” input (VIN(−)) should then be adjusted to just obtain the 00HEX to 01HEX code transition. 2.1 Analog Differential Voltage Inputs and Common-Mode Rejection The differential inputs of this converter actually reduce the effects of common-mode input noise, a signal common to both selected “+” and “−” inputs for a conversion (60 Hz is most typical). The time interval between sampling the “+” input and then the “−” input is 1⁄2 of a clock period. The change in the common-mode voltage during this short time interval can cause conversion errors. For a sinusoidal common-mode signal this error is: 7 www.national.com Applications Information (Continued) DS008557-11 DS008557-12 a) Ratiometric b) Absolute with a Reduced Span FIGURE 1. Referencing Examples The VREF (or VCC) voltage is then adjusted to provide a code change from FEHEX to FFHEX. This completes the adjustment procedure. For an example see the Zero-Shift and Span Adjust circuit below. The full-scale adjustment should be made [with the proper VIN (−) voltage applied] by forcing a voltage to the VIN(+) input which is given by: where VMAX = the high end of the analog input range and VMIN = the low end (the offset zero) of the analog range. (Both are ground referenced.) Zero Shift and Span Adjust (2V≤VIN≤5V) DS008557-13 www.national.com 8 Applications Information (Continued) Span Adjust 0V≤VIN≤3V DS008557-14 Protecting the Input High Accuracy Comparator DS008557-16 DS008557-15 DO = all 1s if VIN(+) > VIN(−) DO = all 0s if VIN(+) < VIN(−) Diodes are 1N914 9 www.national.com Applications Information (Continued) Continuous Conversion DS008557-19 Operating with Automotive Ratiometric Transducers DS008557-17 *VIN(−) = 0.15 VCC 15% of VCC≤VXDR≤85% of VCC SAMPLE PROGRAM FOR ADC0841 — INS8039 INTERFACE CONVERTING TWO RATIOMETRIC, DIFFERENTIAL SIGNALS 0000 04 10 BEGIN: ORG 0H JMP BEGIN ORG 10H ;MAIN PROGRAM MOV R1,#0FFH ;LOAD R1 WITH A UNUSED ADDR ;START PROGRAM AT ADDR 10 0010 B9 FF 0012 B8 20 MOV R0,#20H 0014 89 FF ORL P1,#0FFH ;SET PORT 1 OUTPUTS HIGH 0016 23 00 MOV A,00H ;LOAD THE ACC WITH 00 0018 14 50 CALL CONV ;CALL THE CONVERSION SUBROUTINE ;LOCATION ;CONTINUE MAIN PROGRAM www.national.com 10 ;A/D DATA ADDRESS Applications Information (Continued) ;CONVERSION SUBROUTINE ;ENTRY: ACC — A/D MUX DATA ;EXIT: ACC — CONVERTED DATA CONV: ORG 50H ANL P1,#0FEH MOVX @ R1,A ;START CONVERSION IN A,P1 LOOP ;INPUT INTR STATE ;IF INTR = 1 GOTO LOOP A,@R1 ;IF INTR = 0 INPUT A/D DATA 0050 99 FE 0052 91 0053 09 0054 32 53 JB1 0056 81 MOVX 0057 89 01 ORL P1,&01H ;CLEAR THE A/D CHIP SELECT 0059 A0 MOV @ R0,A ;STORE THE A/D DATA 005A 83 RET LOOP: ;CHIP SELECT THE A/D ;RETURN TO MAIN PROGRAM ADC0841_INS8039 Interface DS008557-20 11 www.national.com Applications Information (Continued) I/O Interface to NSC800™ DS008557-21 SAMPLE PROGRAM FOR ADC0841 — NSC800 INTERFACE 0010 NCONV EQU 16 ;TWICE THE NUMBER OF REQUIRED 000F DEL EQU 15 ;DELAY 60 µsec CONVERSION 001F CS EQU 1FH ;THE BOARD ADDRESS 3C00 ADDTA EQU 003CH ;CONVERSIONS ;START OF RAM FOR A/D ;DATA 0000' 00 DTA: DB 08H 0001' 0E 1F START: LD C,CS 0003' 06 16 LD B,NCONV 0005' 21 0000' LD HL,DTA 0008' 11 003C LD DE,ADDTA 000B' ED A3 000D' EB EX DE,HL 000E' 3E 0F LD A,DEL 0010' 3D DEC A ;WAIT 60 µsec FOR THE 0011' C2 0013' JP NZ,WAIT ;CONVERSION TO FINISH 0014' ED A2 INI STCONV: OUTI ;DATA ;START A CONVERSION ;HL = RAM ADDRESS FOR THE ;A/D DATA WAIT: ;STORE THE A/D’S DATA ;THE REQUIRED CONVERSIONS COMPLETED? 0016' EB EX DE,HL 0017' C2 000E' JP NZ,STCONV ;IF NOT GOTO STCONV END Note 12: A conversion is started, then a 60 µs wait for the A/D to complete a conversion and the data is stored at address ADDTA for the first conversion, ADDTA + 1 for the second conversion, etc. for a total of 8 conversions. www.national.com 12 Ordering Information Temperature Total Unadjusted Error Package ± 1⁄2 LSB ± 1 LSB Outline 0˚C to +70˚C ADC0841BCN ADC0841CCN N20A Molded Dip −40˚C to +85˚C ADC0841BCV ADC0841CCV V20A Molded Chip Carrier Range 13 www.national.com 14 Physical Dimensions inches (millimeters) unless otherwise noted Molded Dual-In-Line Package (N) Order Number ADC0841BCN or ADC0841CCN NS Package Number N20A Molded Chip Carrier Package (V) Order Number ADC0841BCV or ADC0841CCV NS Package Number V20A 15 www.national.com ADC0841 8-Bit µP Compatible A/D Converter LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component is any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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