LP3952 6-Channel Color LED Driver with Audio Synchronization General Description Features LP3952 is a color LED driver for battery powered handheld devices. It drives any color LEDs including RGB LEDs, indicator LEDs and keypad backlight LEDs. The boost DC-DC converter drives high current loads with high efficiency. The stand-alone command based RGB controller is feature rich and easy to configure. Different lighting patterns and blinking sequences can be programmed to driver registers. Built-in audio synchronization feature allows user to synchronize the color LEDs to audio signal. LED lighting can be controlled either by audio signal amplitude or frequency. There are many controls available for audio synchronization to get desired lighting effect, including gain, speed, and different filter settings. The flexible I2C interface allows easy control of LP3952. LED outputs can be also controlled with external PWM signal. Small micro SMDxt package together with minimum number of external components is a best fit for handheld devices. ■ Constant current and PWM controlled color LED drivers ■ Maximum current 40mA / output in constant current mode, ■ ■ ■ ■ ■ ■ ■ supports also switch mode control with 50 mA maximum current / output Complete audio synchronization for color/RGB LEDs with amplitude, frequency and speed optimization Command based lighting pattern generator for RGB LEDs Programmable ON/OFF blinking sequences for RGB1 outputs High efficiency Boost DC-DC converter with programmable VOUTand fSW I2C compatible interface Possibility for external PWM dimming control Small package – 36-bump micro SMDxt, 3.0 x 3.0 x 0.65 mm Applications ■ Cellular Phones ■ PDAs, MP3 players Typical Applications 30023871 © 2007 National Semiconductor Corporation 300238 www.national.com LP3952 6-Channel Color LED Driver with Audio Synchronization July 2007 LP3952 Connection Diagrams and Package Mark Information CONNECTION DIAGRAMS 36-bump Micro SMDxt Package, 3.0 x 3.0 x 0.65 mm, 0.5 mm pitch NS Package Number RLA36AAA 30023872 30023873 PACKAGE MARK 30023874 Ordering Information www.national.com Order Number Package Marking Supplied As Spec/Flow LP3952RL D62B TNR 250 NoPb LP3952RLX D62B TNR 1000 NoPb 2 LP3952 Pin Descriptions Pin # Name Type 6F SW Output Description 6E FB Input 6D GND Ground Ground 6C R1 Output Red LED 1 Output 6B G1 Output Green LED 1 Output 6A B1 Output Blue LED 1 Output Boost Converter Power Switch Boost Converter Feedback 5F GND_SW Ground Power Switch Ground 5E GND Ground Ground 5D VDDIO Power Supply Voltage for Logic Input/Output Buffers and Drivers 5C SDA Logic Input/Output 5B IRGB Input 5A GND_RGB Ground Ground for RGB Currents 4F GND Ground Ground 4E GND Ground Ground 4D PWM Logic Input External PWM Control for LEDs. Connect to GND if not used. 4C ADDR_SEL Logic Input Address Select (I2C) 4B NRST Logic Input Reset Pin Serial Data In/Out (I2C) Bias Current Set Resistor for RGB Drivers 4A R2 Output Red LED 2 Output 3F GND Ground Ground 3E GND Ground Ground 3D VDD1 Power Supply Voltage 3C GND Ground Ground 3B SCL Logic Input Clock (I2C) 3A G2 Output Green LED 2 Output 2F GND Ground Ground Ground 2E GND Ground 2D ASE Input Audio Synchronization Input 2C IRT Input Oscillator Frequency Resistor 2B GNDT Ground Ground 2A B2 Output Blue LED 2 Output 1F GND Ground Ground 1E GND Ground Ground 1D GNDA Ground Ground for Analog Circuitry 1C VREF Output Reference Voltage 1B VDDA Power Internal LDO Output 1A VDD2 Power Supply Voltage 3 www.national.com LP3952 Operating Ratings Absolute Maximum Ratings (Notes 1, 2) (Notes 1, 2) V (SW, FB, R1-2, G1-2, B1-2) 0 to 6.0V VDD1,2 with external LDO 2.7 to 5.5V VDD1,2 with internal LDO 3.0 to 5.5V VDDA 2.7 to 2.9V VDDIO 1.65V to VDD1 Voltage on ASE 0.1V to VDDA –0.1V Recommended Load Current 0 to 300 mA Junction Temperature (TJ) Range -30°C to +125°C Ambient Temperature (TA) Range -30°C to +85°C (Note 8) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. V (SW, FB, R1-2, G1-2, B1-2) (Notes 3, 4) VDD1, VDD2, VDDIO, VDDA Voltage on ASE, IRT, IRGB, VREF Voltage on Logic Pins V(all other pins): Voltage to GND I (VREF) I(R1, G1, B1, R2, G2, B2) Continuous Power Dissipation (Note 5) Junction Temperature (TJ-MAX) Storage Temperature Range Maximum Lead Temperature (Soldering) (Note 6) ESD Rating (Note 7) Human Body Model: www.national.com -0.3V to +7.2V -0.3V to +6.0V -0.3V to VDD1+0.3V with 6.0V max -0.3V to VDDIO +0.3V with 6.0V max -0.3V to 6.0V Thermal Properties 10 μA 100 mA Internally Limited Junction-to-Ambient Thermal Resistance(θJA), RLA36AAA Package (Note 9) 150°C -65°C to +150°C 260°C 2 kV 4 60°C/W (Notes 2, 10) Limits in standard typeface are for TJ = 25°C. Limits in boldface type apply over the operating ambient temperature range (-30°C < TA < +85°C). Unless otherwise noted, specifications apply to the LP3952 Block Diagram with: VDD1 = VDD2 = 3.6V, VDDIO = 2.8V, CVDD = CVDDIO = 100 nF, COUT = CIN = 10 μF, CVDDA = 1 μF, CREF = 100 nF, L1 = 4.7 μH, RRGB = 5.6 kΩ and RRT = 82 kΩ (Note 11). Symbol IVDD Parameter Standby supply current (VDD1 + VDD2) Condition Min NSTBY (bit) = L, NRST (pin) = H SCL=H, SDA = H Typ Max Units 1 8 μA 450 μA 1 mA No-boost supply current NSTBY (bit) = H, (VDD1 + VDD2) EN_BOOST(bit) = L SCL = H, SDA = H Audio sync and LEDs OFF IVDD IVDDIO IEXT_LDO VDDA No-load supply current (VDD1 + VDD2) NSTBY (bit) = H, EN_BOOST (bit) = H SCL = H, SDA = H Audio sync and LEDs OFF Autoload OFF RGB drivers (VDD1 + VDD2) CC mode at R1, G1, B1 and R2, G2, B2 set to 15 mA SW mode 150 150 μA Audio synchronization (VDD1 + VDD2) Audio sync ON VDD1,2 = 2.8V 390 μA VDD1,2 = 3.6V 700 VDDIO Standby Supply current NSTBY (bit)=L SCL = H, SDA = H External LDO output current (VDD1, VDD2, VDDA) 7V tolerant application only IBOOST = 300 mA Output voltage of internal (Note 12) LDO for analog parts 2.72 -3 2.80 1 μA 6.5 mA 2.88 +3 V % Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics tables. Note 2: All voltages are with respect to the potential at the GND pins. Note 3: Battery/Charger voltage should be above 6V no more than 10% of the operational lifetime. Note 4: Voltage tolerance of LP3952 above 6.0V relies on fact that VDD1 and VDD2 (2.8V) are available (ON) at all conditions. If VDD1 and VDD2 are not available (ON) at all conditions, National Semiconductor does not guarantee any parameters or reliability for this device. Note 5: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ=160°C (typ.) and disengages at TJ=140°C (typ.). Note 6: For detailed soldering specifications and information, please refer to National Semiconductor Application Note AN1412 : Micro SMDxt Wafer Level Chip Scale Package Note 7: The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. Note 8: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX). Note 9: Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design. Note 10: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm. Note 11: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics. Note 12: VDDA output is not recommended for external use. 5 www.national.com LP3952 Electrical Characteristics LP3952 Block Diagram 30023878 www.national.com 6 RESET: In the RESET mode all the internal registers are reset to the default values and the chip goes to STANDBY mode after reset. NSTBY control bit is low after reset by default. Reset is active always if NRST input pin is low or internal Power On Reset is active. LP3952 can be also reset by writing any data to Reset Register in address 60H. Power On Reset (POR) will activate during the chip startup or when the supply voltage VDD2 falls below 1.5V. Once VDD2 rises above 1.5V, POR will inactivate and the chip will continue to the STANDBY mode. STANDBY: The STANDBY mode is entered if the register bit NSTBY is LOW. This is the low power consumption mode, when all circuit functions are disabled. Registers can be written in this mode and the control bits are effective immediately after power up. STARTUP: When NSTBY bit is written high, the INTERNAL STARTUP SEQUENCE powers up all the needed internal blocks (Vref, Bias, Oscillator etc..). To ensure the correct oscillator initialization, a 10 ms delay is generated by the internal state-machine. If the chip temperature rises too high, the Thermal Shutdown (TSD) disables the chip operation and STARTUP mode is entered until no thermal shutdown event is present. BOOST STARTUP: Soft start for boost output is generated in the BOOST STARTUP mode. The boost output is raised in PFM mode during the 10 ms delay generated by the state-machine. The Boost startup is entered from Internal Startup Sequence if EN_BOOST is HIGH or from Normal mode when EN_BOOST is written HIGH. During the 10 ms Boost Startup time all LED outputs are switched off to ensure smooth start-up. NORMAL: During NORMAL mode the user controls the chip using the Control Registers. The registers can be written in any sequence and any number of bits can be altered in a register in one write 30023807 7 www.national.com LP3952 Modes of Operation LP3952 Magnetic Boost DC/DC Converter The LP3952 Boost DC/DC Converter generates a 4.0 – 5.3V voltage for the LEDs from single Li-Ion battery (3V…4.5V). The output voltage is controlled with an 8-bit register in 9 steps. The converter is a magnetic switching PWM mode DC/ DC converter with a current limit. The converter has three options for switching frequency, 1 MHz, 1.67 MHz and 2 MHz (default), when timing resistor RT is 82 kΩ. Timing resistor defines the internal oscillator frequency and thus directly affects boost frequency and all circuit's internally generated timing (RGB patterns). The LP3952 Boost Converter uses pulse-skipping elimination to stabilize the noise spectrum. Even with light load or no load a minimum length current pulse is fed to the inductor. An active load is used to remove the excess charge from the output capacitor at very light loads. At very light load and when input and output voltages are very close to each other, the pulse skipping is not completely eliminated. Output voltage should be at least 0.5V higher than input voltage to avoid pulse skipping. Reducing the switching frequency will also reduce the required voltage difference. Active load can be disabled with the en_autoload bit. Disabling will increase the efficiency at light loads, but the downside is that pulse skipping will occur. The Boost Converter should be stopped when there is no load to minimise the current consumption. The topology of the magnetic boost converter is called CPM control, current programmed mode, where the inductor current is measured and controlled with the feedback. The user can program the output voltage of the boost converter. The output voltage control changes the resistor divider in the feedback loop. The following figure shows the boost topology with the protection circuitry. Four different protection schemes are implemented: 1. 2. 3. 4. Over voltage protection, limits the maximum output voltage — Keeps the output below breakdown voltage. — Prevents boost operation if battery voltage is much higher than desired output. Over current protection, limits the maximum inductor current — Voltage over switching NMOS is monitored; too high voltages turn the switch off. Feedback break protection. Prevents uncontrolled operation if FB pin gets disconnected. Duty cycle limiting, done with digital control. 30023808 Boost Converter Topology www.national.com 8 LP3952 Magnetic Boost DC/DC Converter Electrical Characteristics Symbol Parameter Conditions Min Typ Max 3.0V ≤ VIN VOUT = 5V 0 3.0V ≤ VIN VOUT = 4V 0 400 Output Voltage Accuracy (FB Pin) 3.0V ≤ VIN ≤ VOUT - 0.5 VOUT = 5.0V −5 +5 Output Voltage (FB Pin) 1 mA ≤ ILOAD ≤ 300 mA VIN > 5V + V(SCHOTTKY) VIN–V(SCHOTTKY) RDSON Switch ON Resistance VDD1,2 = 2.8V, ISW = 0.5A 0.4 fboost PWM Mode Switching Frequency RT = 82 kΩ freq_sel[2:0] = 1XX Frequency Accuracy 2.7 ≤ VDDA ≤ 2.9 −6 RT = 82 kΩ −9 ILOAD Load Current VOUT Units 300 mA V 0.8 2 tPULSE Switch Pulse Minimum Width no load tSTARTUP Startup Time Boost startup from STANDBY ISW_MAX SW Pin Current Limit Ω MHz ±3 +6 +9 25 % ns 10 700 550 % ms 800 900 950 mA Boost Output Voltage Control BOOST STANDBY MODE User can stop the Boost Converter operation by writing the Enables register bit EN_BOOST low. When EN_BOOST is written high, the converter starts for 10 ms in PFM mode and then goes to PWM mode. BOOST OUTPUT VOLTAGE CONTROL User can control the boost output voltage by boost output 8bit register. Boost Output [7:0] Register 0DH Boost Output Voltage (typical) Bin Hex 0000 0000 00 4.00 0000 0001 01 4.25 0000 0011 03 4.40 0000 0111 07 4.55 0000 1111 0F 4.70 0001 1111 1F 4.85 0011 1111 3F 5.00 Default 0111 1111 7F 5.15 1111 1111 FF 5.30 30023809 BOOST FREQUENCY CONTROL freq_sel[2:0] frequency 1XX 2.00 MHz 01X 1.67 MHz 001 1.00 MHz Register ‘boost freq’ (address 0EH). Register default value after reset is 07H. 9 www.national.com LP3952 Boost Converter Typical Performance Characteristics Vin = 3.6V, Vout = 5.0V if not otherwise stated Boost Converter Efficiency Boost Typical Waveforms at 100mA Load 30023811 30023810 Battery Current vs Voltage Battery Current vs Voltage 30023812 30023813 Boost Line Regulation Boost Startup with No Load 30023814 www.national.com 30023815 10 LP3952 Boost Load Transient, 50 mA–100 mA Boost Switching Frequency 30023816 30023817 Output Voltage vs Load Current Efficiency at Low Load vs Autoload 30023862 30023861 11 www.national.com LP3952 Functionality of Color LED Outputs (R1, G1, B1; R2, G2, B2) LP3952 has 2 sets of RGB/color LED outputs. Both sets have 3 outputs and the sets can be controlled in 4 different ways: CURRENT CONTROL OF COLOR LED OUTPUTS (R1, R2, G1, G2, B1, B2) Both RGB output sets can be separately controlled as constant current sinks or as switches. This is done using cc_rgb1/2 bits in the RGB control register. In constant current mode one or both RGB output sets are controlled with constant current sinks (no external ballast resistors required). The maximum output current for both drivers is set by one external resistor RRGB. User can decrease the maximum current for an individual LED driver by programming as shown later. The maximum current for all RGB drivers is set with RRGB. The equation for calculating the maximum current is 1. Command based pattern generator control (internal PWM) 2. Audio synchronization control 3. Programmable ON/OFF blinking sequences for RGB1 4. External PWM control By using command based pattern generator user can program any kind of color effect patterns. LED intensity, blinking cycles and slopes are independently controlled with 8 16-bit commands. Also real time commands are possible as well as loops and step by step control. If analog audio is available on system, the user can use audio synchronization for synchronizing LED blinking to the music. The different modes together with the various sub modes generate very colorful and interesting lighting effects. Direct ON/OFF control is mainly for switching on and off LEDs. External PWM control is for applications where external PWM signal is available and required to control the color LEDs. PWM signal can be connected to any color LED separately as shown later. IMAX = 100 × 1.23V / (RRGB + 50Ω) where IMAX - maximum RGB current in any RGB output in constant current mode 1.23V - reference voltage 100 - internal current mirror multiplier RRGB- resistor value in Ohms 50Ω - internal resistor in the IRGB input For example if 22mA is required for maximum RGB current RRGB equals to COLOR LED CONTROL MODE SELECTION The RGB_SEL[1:0] bits in the Enables register (08H) control the output modes for RGB1 (R1, G1, B1) and RGB2 (R2, G2, B2) outputs as seen in the following table. RGB_SEL [1:0] Audio sync Pattern generator Blinking control 00 - RGB1 & RGB2 - 01 - RGB2 RGB1 10 RGB2 RGB1 - 11 RGB1 & RGB2 - - RRGB=100×1.23V / IMAX–50Ω=123V / 0.022A–50Ω=5.54kΩ Each individual RGB output has a separate maximum current programming. The control bits are in registers RGB1 max current and RGB2 max current (12H and 13H) and programming is shown in table below. The default value after reset is 00b. RGB Control register (00H) has control bits for direct on/off control of all color LEDs. Note that the LEDs have to be turned on in order to control them with audio synchronization or pattern generator. The external PWM signal can control any LED depending on the control register setup. External PWM signal is connected to PWM pin. The controls are in the Ext. PWM Control register (address 07H): bit 5 PWM controls R1 output g1_pwm bit 4 PWM controls G1 output b1_pwm bit 3 PWM controls B1 output r2_pwm bit 2 PWM controls R2 output g2_pwm bit 1 PWM controls G2 output b2_pwm bit 0 PWM controls B2 output Note: Maximum external PWM frequency is 1kHz. If during the external PWM control the internal PWM is on, the result will be product of both functions. www.national.com Maximum current/output 00 0.25 × IMAX 01 0.50 × IMAX 10 0.75 × IMAX 11 1.00 × IMAX SWITCH MODE The switch mode is used if there is a need to connect parallel LEDs to output or if the RGB output current needs to be increased. Please note that the switch mode requires an external ballast resistors at each output to limit the LED current. The switch/current mode and on/off controls for RGB are in the RGB_ctrl register (00H). Ext. PWM Control (07H) r1_pwm IR1[1:0], IG1[1:0], IB1[1:0], IR2[1:0], IG2[1:0], IB2[1:0] 12 LP3952 RGB_ctrl register (00H) CC_RGB1 bit7 CC_RGB2 bit6 r1sw bit5 g1sw bit4 b1sw bit3 r2sw bit2 g2sw bit1 b2sw bit0 1 R1, G1 and B1 are switches → limit current with ballast resistor 0 R1, G1 and B1 are constant current sinks, current limited internally 1 R2, G2 and B2 are switches → limit current with ballast resistor 0 R2, G2 and B2 are constant current sinks, current limited internally 1 R1 is on 0 R1 is off 1 G1 is on 0 G1 is off 1 B1 is on 0 B1 is off 1 R2 is on 0 R2 is off 1 G2 is on 0 G2 is off 1 B2 is on 0 B2 is off 30023818 13 www.national.com LP3952 Command Based Pattern Generator for Color LEDs The LP3952 has an unique stand-alone command based pattern generator with 8 user controllable 16-bit commands. Since registers are 8-bit long one command requires 2 write cycles. Each command has intensity level for each LED, command execution time (CET) and transition time (TT) as seen in the following figures. 30023819 COMMAND REGISTER WITH 8 COMMANDS COMMAND 1 COMMAND 2 COMMAND 3 COMMAND 4 ADDRESS 50H R2 R1 R0 G2 G1 G0 CET3 CET2 ADDRESS 51H CET1 CET0 B2 B1 B0 TT2 TT1 TT0 CET2 ADDRESS 52H R2 R1 R0 G2 G1 G0 CET3 ADDRESS 53H CET1 CET0 B2 B1 B0 TT2 TT1 TT0 ADDRESS 54H R2 R1 R0 G2 G1 G0 CET3 CET2 ADDRESS 55H CET1 CET0 B2 B1 B0 TT2 TT1 TT0 ADDRESS 56H R2 R1 R0 G2 G1 G0 CET3 CET2 ADDRESS 57H CET1 CET0 B2 B1 B0 TT2 TT1 TT0 COMMAND 5 ADDRESS 58H R2 R1 R0 G2 G1 G0 CET3 CET2 ADDRESS 59H CET1 CET0 B2 B1 B0 TT2 TT1 TT0 COMMAND 6 ADDRESS 5AH R2 R1 R0 G2 G1 G0 CET3 CET2 ADDRESS 5BH CET1 CET0 B2 B1 B0 TT2 TT1 TT0 CET2 COMMAND 7 COMMAND 8 ADDRESS 5CH R2 R1 R0 G2 G1 G0 CET3 ADDRESS 5DH CET1 CET0 B2 B1 B0 TT2 TT1 TT0 ADDRESS 5EH R2 R1 R0 G2 G1 G0 CET3 CET2 ADDRESS 5FH CET1 CET0 B2 B1 B0 TT2 TT1 TT0 COLOR INTENSITY CONTROL Each color has 3-bit intensity level. Level control is logarithmic, 2 curves are selectable. The LOG bit in register 11H defines the curve used as seen in the following table. R[2:0], G[2:0], B[2:0] LOG=0 LOG=1 0 0 001 7 1 010 14 2 011 21 4 100 32 10 101 46 21 110 71 46 111 100 100 000 www.national.com CURRENT [% × IMAX(COLOR)] 30023820 14 CET [3:0] CET duration, ms 0000 197 0001 393 0010 590 0011 786 0100 983 0101 1180 0110 1376 0111 1573 1000 1769 1001 1966 1010 2163 1011 2359 1100 2556 1101 2753 CET [3:0] CET duration, ms 1110 2949 1111 3146 LP3952 COMMAND EXECUTION TIME (CET) AND TRANSITION TIME (TT) The command execution time CET is the duration of one single command. Command execution times are defined as follows, when RT=82kΩ: Transition time TT is duration of transition from the previous RGB value to programmed new value. Transition times are defined as follows: TT [2:0] Transition time, ms 000 0 001 55 010 110 011 221 100 442 101 885 110 1770 111 3539 The figure below shows an example of RGB CET and TT times. 30023821 The command execution time also may be less than the transition time – the figure below illuminates this case. 30023822 15 www.national.com LP3952 LOOP CONTROL Pattern generator commands can be looped using the LOOP bit (D1) in Pattern gen ctrl register (11H). If LOOP=1 the program will be looped from the command 8 register or if there is 0000 0000 and 0000 0000 in one command register. The loop will start from command 1 and continue until stopped by writing rgb_start=0 or loop=0. The example of loop is shown in following figure: 30023823 SINGLE PROGRAM If control bit LOOP=0 the program will start from Command 1 and run to either last command or to empty “0000 0000 / 0000 0000” command. 30023824 The LEDs maintain the brightness of the last command when the single program stops. Changes in command register will not be effective in this phase. The RGB_START bit has to be toggled off and on to make changes effective. START BIT Pattern_gen_ctrl register’s RGB_START bit will enable command execution starting from Command 1. Pattern gen ctrl register (11H) www.national.com rgb_start Bit 2 0 – Pattern generator disabled 1 – execution pattern starting from command 1 loop Bit 1 0 – pattern generator loop disabled (single pattern) 1 – pattern generator loop enabled (execute until stopped) log Bit 0 0 – color intensity mode 0 1 – color intensity mode 1 16 The color LEDs connected to RGB outputs can be synchronized to incoming audio with Audio Synchronization feature. Audio Sync has 2 modes. Amplitude mode synchronizes color LEDs based on input signal’s peak amplitude. In the amplitude mode the user can select between 3 different amplitude mapping modes and 4 different speed configurations. The frequency mode synchronizes the color LEDs based on bass, middle and treble amplitudes (= low pass, band pass and high pass filters). User can select between 2 different frequency responses and 4 different speed configurations for best audio-visual user experience. Programmable gain and AGC function are also available for adjustment of input signal amplitude to light response. The Audio Sync functionality is described more closely below. PWM signal with 3.3V amplitude. Active filters, such as a Sallen-Key filter, may also be applied. An active filter gives better stop-band attenuation and cut-off frequency can be higher than for a RC-filter. To make sure that the filter rolls off sufficiently quickly, connect your filter circuit to the audio input(s), turn on the audio synchronization feature, set manual gain to maximum, apply the PWM signal to the filter input and keep an eye on LEDs. If they are blinking without an audio signal (modulation), a sharper roll-off after the cut-off frequency, more stop-band attenuation, or smaller amplitude of the PWM signal is required. AUDIO SYNCHRONIZATION SIGNAL PATH LP3952 audio synchronization is mainly done digitally and it consists of the following signal path blocks: • Input Buffers • AD Converter • DC Remover • Automatic Gain Control (AGC) • Programmable Gain • 3 Band Digital Filter • Peak Detector • Look-up Tables (LUT) • Mode Selector • Integrators • PWM Generator • Output Drivers USING A DIGITAL PWM AUDIO SIGNAL AS AN AUDIO SYNCHRONIZATION SOURCE If the input signal is a PWM signal, use a first or second order low pass filter to convert the digital PWM audio signal into an analog waveform. There are two parameters that need to be known to get the filter to work successfully: frequency of the PWM signal and the voltage level of the PWM signal. Suggested cut-off frequency (-3 dB) should be around 2 kHz to 4 kHz and the stop-band attenuation at sampling frequency should be around -48 dB or better. Use a resistor divider to reduce the digital signal amplitude to meet the specification of the analog audio input. Because a low-order low-pass filter attenuates the high-frequency components from audio signal, MODE_CTRL=01b selection is recommended when frequency synchronization mode is enabled. Application example 5 shows an example of a second order RC-filter for 29 kHz 30023825 The digitized input signal has DC component that is removed by digital DC REMOVER (-3 dB @ 400 Hz). Since the light response of input audio signal is very much amplitude dependent the AGC adjusts the input signal to suitable range automatically. User can disable AGC and the gain can be set manually with PROGRAMMABLE GAIN. LP3952 has 2 audio synchronization modes: amplitude and frequency. For amplitude based synchronization the PEAK DETECTION method is used. For frequency based synchronization 3 BAND FILTER separates high pass, low pass and band bass signals. For both modes the predefined LUT is used to optimize the audio visual effect. MODE SELECTOR selects the synchronization mode. Different response times to music beat can be selected using INTEGRATOR speed variables. Finally PWM GENERATOR sets the driver FET duty cycles. scribed in the Audio Synch table. The buffer is rail-to-rail input operational amplifier connected as a voltage follower. DC level of the input signal is set by a simple resistor divider INPUT SIGNAL TYPE AND BUFFERING LP3952 supports single ended audio input as shown in the figure below. The electric parameters of the buffer are de- 30023826 17 www.national.com LP3952 Audio Synchronization LP3952 AUDIO SYNCHRONIZATION ELECTRICAL PARAMETERS Symbol Parameter Conditions ZIN Input Impedance of ASE AIN Audio Input Level Range (peak-to-peak) f3dB Gain = 21 dB Gain = 0 dB Crossover Frequencies (-3 dB) Narrow Frequency Response Wide Frequency Response Min Typical 250 500 Max kΩ V 0.1 VDDA-0.1 Low Pass Band Pass High Pass Low Pass Band Pass High Pass 0.5 1.0 and 1.5 2.0 1.0 2.0 and 3.0 4.0 CONTROL OF ADC AND AUDIO SYNCHRONIZATION The following table describes the controls required for audio synchronization. Audio_sync_CTRL1 (2AH) Input signal gain control. Range 0...21 dB, step 3 dB: GAIN_SEL[2:0] Bits 7-5 [000] = 0 dB (default) [001] = 3 dB [010] = 6 dB [011] = 9 dB [100] = 12 dB [101] = 15 dB [110] = 18 dB [111] = 21 dB Synchronization mode selector. SYNC_MODE Bit 4 SYNCMODE = 0 → Amplitude Mode (default) SYNCMODE = 1 → Frequency Mode EN_AGC EN_SYNC INPUT_SEL[1:0] Bit 3 Automatic Gain Control enable 1 = enabled 0 = disabled (Gain Select enabled) (default) Bit 2 Audio synchronization enable 1 = Enabled Note : If AGC is enabled, AGC gain starts from current GAIN_SEL gain value. 0 = Disabled (default) [00] = Single ended input signal, ASE. [01] = Not used Bits 1-0 [10] = Not used [11] = No input (default) Audio_sync_CTRL2 (2BH) EN_AVG Bit 4 0 – averaging disabled (not applicable in audio sync mode) 1 – averaging enabled (not applicable in audio sync mode) MODE_CTRL[1:0] Bits 3-2 See below: Mode control SPEED_CTRL[1:0] Sets the LEDs light response time to audio input. [00] = FASTEST (default) [01] = FAST Bits 1-0 [10] = MEDIUM [11] = SLOW (For SLOW setting in amplitude mode fMAX= 3.8 Hz, Frequency mode fMAX = 7.6 Hz) www.national.com Units 18 kHz Mode control has two setups based on audio synchronization mode select: the frequency mode and the amplitude mode. During the frequency mode user can select two filter options by MODE_CTRL as shown below. User can select the filters based on the music type and light effect requirements. In the first mode the frequency range extends to 8 kHz in the secont to 4 kHz. The lowpass filter is used for the red, the bandpass filter for the blue and the hipass filter for the green LED. Higher frequency mode MODE_CTRL = 00 and SYNC_MODE = 1 Lower frequency mode MODE_CTRL = 01 and SYNC_MODE = 1 30023827 30023828 MODE CONTROL IN AMPLITUDE MODE During the amplitude synchronization mode user can select between three different amplitude mappings by using MODE_CTRL select. These three mapping options give different light response. The modes are presented in the following graphs. Non-overlapping mode MODE_CTRL[1:0] = [01] Partly overlapping mode MODE_CTRL[1:0] = [00] 30023829 30023830 19 www.national.com LP3952 MODE CONTROL IN FREQUENCY MODE LP3952 Overlapping mode MODE_CTRL[1:0] = [10] Peak Input Signal Level Range vs Gain Setting 30023832 30023831 www.national.com 20 LP3952 has a possibility to drive indicator LEDs with RGB1 outputs with programmable blinking time. Blinking function is enabled with RGB_SEL[1:0] bits set as 01b in 0BH register. R1_CYCLE_EN, G1_CYCLE_EN and B1_CYCLE_EN bits in cycle registers (02H, 04H and 06H) enable/disable blinking function for corresponding output. When EN_BLINK bit is written high in register 11H, the blinking sequences for all outputs (which has CYCLE_EN bit enabled) starts simultaneously. EN_BLINK bit should be written high after selecting wanted blinking sequences and enabling CYCLE_EN bits, to synchronize outputs to get desired lighting effect. R1SW, G1SW and B1SW bits can be used to enable and disable outputs when wanted. RGB1 blinking sequence is set with R1, G1 and B1 blink registers (01H, 03H and 05H) by setting the appropriate OFF-ON times. Blinking cycle times are set with R1_CYCLE[2:0], G1_CYCLE[2:0] and B1_CYCLE[2:0] bits in R1, G1 and B1 CYCLE registers (02H, 04H and 06H). OFF/ON time is a percentage of the selected cycle time. Values for setting OFF/ON time can be seen in following table. R1, G1 and B1 Blink Registers (01H, 03H and 05H): Name Bit Description R1_ON[3:0], R1_OFF[3:0] G1_ON[3:0], G1_OFF[3:0] B1_ON[3:0], B1_OFF[3:0] 7-4, 3-0 RGB1 ON and OFF time Blinking ON/OFF cycle is defined so that there will be first OFF-period then ON-period after which follows an off-period for the remaining cycle time that can not be set. If OFF and ON times are together more than 100% the first OFF time will be as set and the ON time is cut to meet 100%. For example, Bits ON/OFF time 0000 0% 0001 1% 0010 2.5% 0011 5% 0100 7.5% 0101 10% 0110 15% 0111 20% 1000 30% 1001 40% 1010 50% 1011 60% 1100 70% 1101 80% 1110 90% 1111 100% if 50% OFF time is set and ON time is set greater than 50%, only 50% ON time is used, the exceeding ON time is ignored. If OFF and ON times are together less than 100% the remaining cycle time output is OFF. 21 www.national.com LP3952 RGB LED Blinking Control LP3952 30023870 Values for setting the blinking cycle for RGB1 can be seen in following table: R1, G1 and B1 Cycle Registers (02H, 04H and 06H): Name Bit Decription R1_CYCLE_EN G1_CYCLE_EN B1_CYCLE_EN 3 Blinking enable 0 = disabled 1 = enabled, output state is defined with blinking cycle R1_CYCLE[2:0] G1_CYCLE[2:0] B1_CYCLE[2:0] 2-0 RGB1 cycle time Bits Blinking cycle time Blinking frequency 000 0.1s 10 Hz 001 0.25s 4 Hz 010 0.5s 2 Hz 011 1s 1 Hz 100 2s 0.5 Hz 101 3s 0.33 Hz 110 4s 0.25 Hz 111 5s 0.2 Hz PATTERN_GEN_CTRL Register (11H): www.national.com Name Bit EN_BLINK 3 Description Blinking sequence start bit 0 = disabled 1 = enabled 22 LP3952 RGB Driver Electrical Characteristics (R1, G1, B1, R2, G2, B2 Outputs) Symbol Parameter ILEAKAGE R1, G1, B1, R2, G2, B2 pin leakage current Condition IRGB Maximum recommended sink current Min Typ Max Units 0.1 1 μA CC mode 40 mA SW mode 50 mA Accuracy @ 37mA RRGB=3.3 kΩ ±1%, CC mode Current mirror ratio CC mode ±5 % 1:100 RGB1 and RGB2 current mismatch IRGB=37mA, CC mode ±5 RSW Switch resistance SW mode 2.5 5 Ω fRGB RGB switching frequency Accuracy proportional to internal clock freq. 20 21.8 kHz 18.2 % Note: RGB current should be limited as follows: constant current mode – limit by external RRGB resistor; switch mode – limit by external ballast resistors Output Current vs Pin Voltage (Current Sink Mode) Pin Voltage vs Output Current (Switch Mode) 30023866 30023868 Output Current vs RRGB (Current Sink Mode) 30023867 23 www.national.com LP3952 7V Shielding To shield LP3952 from high input voltages 6…7.2V the use of external 2.8V LDO is required. This 2.8V voltage protects internally the device against high voltage condition. The recommended connection is as shown in the picture below. Internally both logic and analog circuitry works at 2.8V supply voltage. Both supply voltage pins should have separate filtering capacitors. 30023844 In cases where high voltage is not an issue the connection is as shown below 30023845 www.national.com 24 LP3952 Logic Interface Electrical Characteristics (1.65V ≤ VDDIO ≤ VDD1,2V) (Unless otherwise noted). Symbol Parameter Conditions Min Typ Max Units 0.2×VDDIO V 1.0 μA 400 kHz 0.5 V 1.0 μA LOGIC INPUTS ADDR_SEL, NRST, SCL, PWM, SDA VIL Input Low Level VIH Input High Level IL Logic Input Current fSCL Clock Frequency 0.8×VDDIO V −1.0 LOGIC OUTPUT SDA VOL Output Low Level ISDA = 3 mA IL Output Leakage Current VSDA = 2.8V 0.3 Note: Any unused digital input pin has to be connected to GND to avoid floating and extra current consumption. I2C Compatible Interface STOP condition is defined as the SDA transitioning from LOW to HIGH while SCL is HIGH. The I2C master always generates START and STOP bits. The I2C bus is considered to be busy after START condition and free after STOP condition. During data transmission, I2C master can generate repeated START conditions. First START and repeated START conditions are equivalent, function-wise. INTERFACE BUS OVERVIEW The I2C compatible synchronous serial interface provides access to the programmable functions and registers on the device. This protocol uses a two-wire interface for bi-directional communications between the devices connected to the bus. The two interface lines are the Serial Data Line (SDA), and the Serial Clock Line (SCL). These lines should be connected to a positive supply, via a pull-up resistor and remain HIGH even when the bus is idle. Every device on the bus is assigned a unique address and acts as either a Master or a Slave depending on whether it generates or receives the serial clock (SCL). DATA TRANSACTIONS One data bit is transferred during each clock pulse. Data is sampled during the high state of the serial clock (SCL). Consequently, throughout the clock’s high period, the data should remain stable. Any changes on the SDA line during the high state of the SCL and in the middle of a transaction, aborts the current transaction. New data should be sent during the low SCL state. This protocol permits a single data line to transfer both command/control information and data using the synchronous serial clock. 30023850 TRANSFERRING DATA Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first. Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the 9th clock pulse, signifying an acknowledge. A receiver which has been addressed must generate an acknowledge after each byte has been received. After the START condition, the I2C master sends a chip address. This address is seven bits long followed by an eighth bit which is a data direction bit (R/W). The LP3952 address is 54h or 55H as selected with ADDR_SEL pin. I2C address for LP3952 is 54H when ADDR_SEL=0 and 55H when ADDR_SEL=1. For the eighth bit, a “0” indicates a WRITE and a “1” indicates a READ. The second byte selects the register to which the data will be written. The third byte contains data to write to the selected register. I2C DATA VALIDITY The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of the data line can only be changed when CLK is LOW. 30023849 I2C Signals: Data Validity I2C START AND STOP CONDITIONS START and STOP bits classify the beginning and the end of the I2C session. START condition is defined as SDA signal transitioning from HIGH to LOW while SCL line is HIGH. 30023851 I2C Chip Address 25 www.national.com LP3952 Register changes take an effect at the SCL rising edge during the last ACK from slave. 30023852 w = write (SDA = “0”) r = read (SDA = “1”) ack = acknowledge (SDA pulled down by either master or slave) rs = repeated start id = 7-bit chip address, 54H (ADDR_SEL=0) or 55H (ADDR_SEL=1) for LP3952. I2C Write Cycle When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in the Read Cycle waveform. 30023853 I2C Read Cycle 30023854 I2C Timing Diagram www.national.com 26 LP3952 I2C Timing Parameters VDD1,2 = 3.0 to 4.5V, VDD_IO = 1.65V to VDD1,2 Symbol Parameter Limit Min Units Max μs 1 Hold Time (repeated) START Condition 0.6 2 Clock Low Time 1.3 μs 3 Clock High Time 600 ns 4 Setup Time for a Repeated START Condition 600 5 Data Hold Time (Output direction, delay generated by LP3952) 300 900 ns 5 Data Hold Time (Input direction, delay generated by the Master) 0 900 ns 6 Data Setup Time 7 Rise Time of SDA and SCL 20+0.1Cb 300 ns 8 Fall Time of SDA and SCL 15+0.1Cb 300 ns ns 100 ns 9 Set-up Time for STOP condition 600 ns 10 Bus Free Time between a STOP and a START Condition 1.3 μs Cb Capacitive Load for Each Bus Line 10 200 pF NOTE: Data guaranteed by design Autoincrement mode is available, with this mode it is possible to read or write bytes with autoincreasing addresses. LP3952 has empty spaces in address register map, and it is recommended to use autoincrement mode only for writing in pattern command registers. 27 www.national.com LP3952 Recommended External Components than the peak inductor current (ca. 1A). Average current rating of the schottky diode should be higher than maximum output current used. Schottky diodes with a low forward drop and fast switching speeds are ideal for increasing efficiency in portable applications. Choose a reverse breakdown of the schottky diode larger than the output voltage. Do not use ordinary rectifier diodes, since slow switching speeds and long recovery times cause the efficiency and the load regulation to suffer. OUTPUT CAPACITOR, COUT The output capacitor COUT directly affects the magnitude of the output ripple voltage. In general, the higher the value of COUT, the lower the output ripple magnitude. Multilayer ceramic capacitors with low ESR are the best choice. At the lighter loads, the low ESR ceramics offer a much lower Vout ripple that the higher ESR tantalums of the same value. At the higher loads, the ceramics offer a slightly lower Vout ripple magnitude than the tantalums of the same value. However, the dv/dt of the Vout ripple with the ceramics is much lower than the tantalums under all load conditions. Capacitor voltage rating must be sufficient, 10V or greater is recommended. Some ceramic capacitors, especially those in small packages, exhibit a strong capacitance reduction with the increased applied DC voltage, so called DC bias effect. The capacitance value can fall to below half of the nominal capacitance. Too low output capacitance will increase noise and it can make the boost converter unstable. Recommended maximum DC bias effect at 5V DC voltage is -50%. INDUCTOR, L1 The LP3952’s high switching frequency enables the use of the small surface mount inductor. A 4.7 μH shielded inductor is suggested for 2 MHz operation, 10 μH should be used at 1 MHz. The inductor should have a saturation current rating higher than the rms current it will experience during circuit operation. To get maximum (400 mA) current from the boost, an inductor with 1A saturation current is recommended. If output current is for example 200 mA then inductor with 600 mA saturation current can be used. Less than 300 mΩ ESR is suggested for high efficiency. Open core inductors cause flux linkage with circuit components and interfere with the normal operation of the circuit. This should be avoided. For high efficiency, choose an inductor with a high frequency core material such as ferrite to reduce the core losses. The inductor should be connected to the SW pin as close to the IC as possible. Examples of suitable inductor for 400 mA output current is TDK VLF4012AT-4R7M1R1, and for 200mA application VLF3010AT-4R7MR70 or Panasonic ELLVEG4R7N. INPUT CAPACITOR, CIN The input capacitor CIN directly affects the magnitude of the input ripple voltage and to a lesser degree the VOUT ripple. A higher value CIN will give a lower VIN ripple. Capacitor voltage rating must be sufficient, 10V or greater is recommended. OUTPUT DIODE, D1 A schottky diode should be used for the output diode. Peak repetitive current rating of the schottky diode should be larger LIST OF RECOMMENDED EXTERNAL COMPONENTS Symbol Value Unit CVDD1 Symbol explanation C between VDD1 and GND 100 nF Ceramic, X7R / X5R Type CVDD2 C between VDD2 and GND 100 nF Ceramic, X7R / X5R CVDDIO C between VDDIO and GND 100 nF Ceramic, X7R / X5R CVDDA C between VDDA and GND 1 μF Ceramic, X7R / X5R COUT C between FB and GND 10 μF Ceramic, X7R / X5R, 10V CIN C between battery voltage and GND 10 μF Ceramic, X7R / X5R L1 L between SW and VBAT at 2 MHz 4.7 μH Shielded, low ESR, Isat=1A for 400 mA output current, Isat=600 mA for 200 mA output current CVREF C between VREF and GND 100 nF Ceramic, X7R CVDDIO C between VDDIO and GND 100 nF Ceramic, X7R R between IRGB and GND 5.6 kΩ ±1% RRBG RRT R between IRT and GND 82 kΩ ±1% D1 Rectifying Diode (Vf @ maxload) 0.3 V Schottky diode CASE C between Audio input and ASE 100 nF LEDs www.national.com Ceramic, X7R / X5R User defined 28 LP3952 Application Examples EXAMPLE 1 30023876 There may be cases where the audio input signal going into the LP3952 is too weak for audio synchronization. This figure presents a single-supply inverting amplifier connected to the ASE input for audio signal amplification. The amplification is +20 dB, which is well enough for 20 mVp-p audio signal. Because the amplifier (LMV321) is operating in single supply voltage, a voltage divider using R3 and R4 is implemented to bias the amplifier so the input signal is within the input common-mode voltage range of the amplifier. The capacitor C1 is placed between the inverting input and resistor R1 to block the DC signal going into the audio signal source. The values of R1 and C1 affect the cutoff frequency, fc = 1/(2π*R1*C1), in this case it is around 160 Hz. As a result, the LMV321 output signal is centered around mid-supply, that is VDDA/2. The output can swing to both rails, maximizing the signal-to-noise ratio in a low voltage system 29 www.national.com LP3952 EXAMPLE 2 30023879 Here, a second order RC-filter is used on the ASE input to convert a PWM signal to an analog waveform. More application information is available in the document "LP3952 Evaluation Kit". www.national.com 30 B1 blink B1 cycle Ext. PWM control 05 06 07 0 0 0 b1_on[2] b1_on[3] 0 0 0 r1_pwm 0 b1_on[1] 0 g1_on[1] 0 0 g1_pwm 0 b1_on[0] 0 g1_on[0] 0 r1_on[0] ADC output Boost output Boost_frq 0C 0D 0E Pattern gen ctrl RGB1 max current 11 12 10 Enables 0B 0 0 0 1 0 0 0 0 en_ boost nstby ir1[1:0] 0 Do not use 1 0 Do not use G1 cycle 04 g1_on[2] g1_on[3] 0 0 r1_on[1] 0 g1sw Do not use G1 blink 03 r1_on[2] r1_on[3] 0 r1sw 0A R1 cycle 02 1 1 D4 Do not use R1 blink 01 cc_rgb2 cc_rgb1 D5 09 RGB Ctrl 00 D6 D7 08 REGISTER ADDR (HEX) 0 0 0 1 boost[7:0] 0 data[7:0] 0 ig1[1:0] 0 0 0 rgb_start 1 1 0 1 en_ autoload 0 r2_pwm 0 b1_pwm 0 b1_cycle[2] 0 b1_cycle en b1_off[2] g1_cycle[2] g1_cycle en b1_off[3] 0 0 g1_off[2] 0 0 g1_off[3] 0 r1_cycle[2] 0 r1_off[2] 0 r2sw D2 r1_cycle en r1_off[3] 0 b1sw D3 LP3952 Control Register Names and Default Values 0 0 loop 1 0 b2sw D0 ib1[1:0] 0 0 log 1 1 0 0 0 b2_pwm 0 b1_cycle[0] 0 b1_off[0] 0 g1_cycle[0] 0 g1_off[0] 0 r1_cycle[0] 0 r1_off[0] rgb_sel[1:0] freq_sel[2:0] 1 0 0 0 g2_pwm 0 b1_cycle[1] 0 b1_off[1] 0 g1_cycle[1] 0 g1_off[1] 0 r1_cycle[1] 0 r1_off[1] 0 g2sw D1 LP3952 31 www.national.com www.national.com 32 Command 5B Command 6A Command 6B Command 7A Command 7B 59 5A 5B 5C 5D Command 3A 54 Command 5A Command 2B 53 58 Command 2A 52 Command 4B Command 1B 51 57 Command 1A 50 Command 4A Audio sync CTRL2 2B 56 Audio sync CTRL1 2A Command 3B RGB2 max current 13 55 REGISTER ADDR (HEX) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D7 cet[1:0] cet[1:0] cet[1:0] cet[1:0] cet[1:0] cet[1:0] cet[1:0] 0 0 r[2:0] 0 0 r[2:0] 0 0 r[2:0] 0 0 r[2:0] 0 0 r[2:0] 0 0 r[2:0] 0 0 r[2:0] 0 gain_sel[2:0] D6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D5 0 0 b[2:0] 0 0 b[2:0] 0 0 b[2:0] 0 0 b[2:0] 0 0 b[2:0] 0 0 b[2:0] 0 0 b[2:0] 0 0 en_avg 0 sync_mode ir2[1:0] D4 0 0 g[2:0] 0 0 g[2:0] 0 0 g[2:0] 0 0 g[2:0] 0 0 g[2:0] 0 0 g[2:0] 0 0 ig2[1:0] 0 D2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 en_sync mode_ctrl[1:0] g[2:0] 0 0 en_agc 0 D3 0 tt[2:0] 0 0 tt[2:0] 0 0 tt[2:0] 0 0 tt[2:0] 0 0 tt[2:0] 0 0 cet[3:2] cet[3:2] cet[3:2] cet[3:2] cet[3:2] cet[3:2] cet[3:2] speed_ctrl[1:0] tt[2:0] 0 0 ib2[1:0] input_sel[1:0] tt[2:0] 0 0 1 0 D1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 D0 LP3952 REGISTER Command 8A Command 8B Reset ADDR (HEX) 5E 5F 60 0 0 D7 cet[1:0] 0 0 r[2:0] D6 0 0 D5 0 0 g[2:0] D3 0 0 D2 Writing any data to Reset Register resets LP3952 0 b[2:0] 0 D4 0 tt[2:0] 0 D1 cet[3:2] 0 0 D0 LP3952 33 www.national.com LP3952 LP3952 Registers REGISTER BIT EXPLANATIONS Each register is shown with a key indicating the accessibility of the each individual bit, and the initial condition: Register Bit Accessibility and Initial Condition Key Bit Accessibility rw r –0,–1 Read/write Read only Condition after POR RGB CTRL (00H) – RGB LEDS CONTROL REGISTER D7 D6 D5 D4 D3 D2 D1 D0 cc_rgb1 cc_rgb2 r1sw g1sw b1sw r2sw g2sw b2sw rw-1 rw-1 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 cc_rgb1 Bit 7 0 - R1, G1 and B1 are constant current sinks, current limited internally 1 - R1, G1 and B1 are switches, limit current with external ballast resistor cc_rgb2 Bit 6 0 – R2, G2 and B2 are constant current sinks, current limited internally 1 – R2, G2 and B2 are switches, limit current with external ballast resistor r1sw Bit 5 0 – R1 disabled 1 – R1 enabled g1sw Bit 4 0 – G1 disabled 1 – G1 enabled b1sw Bit 3 0 – B1 disabled 1 – B1 enabled r2sw Bit 2 0 – R2 disabled 1 – R2 enabled g2sw Bit 1 0 – G2 disabled 1 – G2 enabled b2sw Bit 0 0 – B2 disabled 1 – B2 enabled R1/G1/B1 BLINK (01H, 03H, 05H) – BLINKING ON/OFF TIME CONTROL REGISTER D7 D6 rw-0 rw-0 D5 D4 D3 rw-0 rw-0 R1/G1/B1_ON[3:0] www.national.com rw-0 D2 D1 D0 R1/G1/B1_OFF[3:0] 34 rw-0 rw-0 rw-0 LP3952 RGB1 ON and OFF time R1_ON[3:0], R1_OFF[3:0] G1_ON[3:0], G1_OFF[3:0] B1_ON[3:0], B1_OFF[3:0] Bits 7-4, 3-0 Bits ON/OFF time 0000 0% 0001 1% 0010 2.5% 0011 5% 0100 7.5% 0101 10% 0110 15% 0111 20% 1000 30% 1001 40% 1010 50% 1011 60% 1100 70% 1101 80% 1110 90% 1111 100% R1/G1/B1 CYCLE(02H, 04H, 06H) – BLINKING CYCLE CONTROL REGISTER D7 D6 D5 D4 D3 D2 R1/G1/ B1_CYCLE_EN r-0 r-0 r-0 R1_CYCLE_EN G1_CYCLE_EN B1_CYCLE_EN Bit 3 R1_CYCLE[2:0] G1_CYCLE[2:0] B1_CYCLE[2:0] Bits 2-0 r-0 D1 D0 R1/G1/B1_CYCLE[2:0] rw-0 rw-0 rw-0 rw-0 Blinking enable 0 = disabled, output state is defined with RGB registers 1 = enabled, output state is defined with blinking cycle RGB1 cycle time Bits Blinking cycle time Blinking frequency 000 0.1s 10 Hz 001 0.25s 4 Hz 010 0.5s 2 Hz 011 1s 1 Hz 100 2s 0.5 Hz 101 3s 0.33 Hz 110 4s 0.25 Hz 111 5s 0.2 Hz 35 www.national.com LP3952 EXT_PWM_CONTROL (07H) – EXTERNAL PWM CONTROL REGISTER D7 D6 D5 D4 D3 D2 D1 D0 r1_pwm g1_pwm b1_pwm r2_pwm g2_pwm b2_pwm rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 D2 D1 D0 r1_pwm Bit 5 0 – R1 PWM control disabled 1 – R1 PWM control enabled g1_pwm Bit 4 0 – G1 PWM control disabled 1 – G1 PWM control enabled b1_pwm Bit 3 0 – RB PWM control disabled 1 – B1 PWM control enabled r2_pwm Bit 2 0 – R2 PWM control disabled 1 – R2 PWM control enabled g2_pwm Bit 1 0 – G2 PWM control disabled 1 – G2 PWM control enabled b2_pwm Bit 0 0 – B2 PWM control disabled 1 – B2 PWM control enabled ENABLES (0BH) – ENABLES REGISTER D7 r-0 D6 D5 nstby en_boost D4 rw-0 rw-0 D3 en_autoload r-0 r-0 nstby Bit 6 0 – LP3952 standby mode 1 – LP3952 active mode en_boost Bit 5 0 – boost converter disabled 1 – boost converter enabled en_autoload Bit 2 0 – internal boost converter loader off 1 – internal boost converter loader on rw-1 rgb_sel[1:0] rw-0 rw-0 Color LED control mode selection rgb_sel[1:0] Audio sync Pattern generator Blinking sequence 00 - RGB1 & RGB2 - 01 - RGB2 RGB1 10 RGB2 RGB1 - 11 RGB1 & RGB2 - - Bits 1-0 rgb_sel[1:0] ADC_OUTPUT (0CH) – ADC DATA REGISTER D7 D6 D5 D4 D3 D2 D1 D0 r-0 r-0 r-0 r-0 data[7:0] r-0 r-0 data[7:0] www.national.com r-0 Bits 7-0 r-0 Data register ADC (Audio input, light or temperature sensors) 36 D7 D6 D5 D4 D3 D2 D1 D0 rw-1 rw-1 rw-1 rw-1 D1 D0 Boost[7:0] rw-0 rw-0 rw-1 rw-1 Adjustment Bits 7-0 Boost[7:0] Boost[7:0] Typical boost output (V) 0000 0000 4.00 0000 0001 4.25 0000 0011 4.40 0000 0111 4.55 0000 1111 4.70 0001 1111 4.85 0011 1111 5.00 (default) 0111 1111 5.15 1111 1111 5.30 BOOST_FRQ (0EH) – BOOST FREQUENCY CONTROL REGISTER D7 D6 D5 D4 D3 D2 r-0 r-0 r-0 r-0 r-0 rw-1 freq_sel[2:0] rw-1 rw-1 Adjustment freq_sel[2:0] freq_sel[2:0] Frequency 1xx 2.00 MHz 01x 1.67 MHz 00x 1.00 MHz Bits 7-0 PATTERN_GEN_CTRL (11H) – PATTERN GENERATOR CONTROL REGISTER D7 r-0 D6 r-0 D5 r-0 D4 D3 D2 D1 D0 en_blink rgb_start loop log rw-0 rw-0 rw-0 rw-0 r-0 en_blink Bit 3 0 - blinking sequences start bit disabled 1 - blinking sequences start bit enabled rgb_start Bit 2 0 – pattern generator disabled 1 – execution pattern starting from command 1 loop Bit 1 0 – pattern generator loop disabled (single pattern) 1 – pattern generator loop enabled (execute until stopped) log Bit 0 0 – color intensity mode 0 1 – color intensity mode 1 37 www.national.com LP3952 BOOST_OUTPUT (0DH) – BOOST OUTPUT VOLTAGE CONTROL REGISTER LP3952 RGB1_MAX_CURRENT (12H) – RGB1 DRIVER INDIVIDUAL MAXIMUM CURRENT CONTROL REGISTER D7 D6 D5 D4 D3 ir1[1:0] r-0 r-0 rw-0 D2 rw-0 rw-0 Bits 5-4 rw-0 ir1[2:0] Maximum output current 00 0.25×IMAX 01 0.50×IMAX 10 0.75×IMAX 11 1.00×IMAX Maximum current for G1 driver ig1[1:0] Bits 3-2 ig2[1:0] Maximum output current 00 0.25×IMAX 01 0.50×IMAX 10 0.75×IMAX 11 1.00×IMAX Maximum current for B1 driver ib1[1:0] www.national.com Bits 1-0 ib1[1:0] Maximum output current 00 0.25×IMAX 01 0.50×IMAX 10 0.75×IMAX 11 1.00×IMAX 38 D0 ib1[1:0] Maximum current for R1 driver ir1[1:0] D1 ig1[1:0] rw-0 rw-0 D7 D6 D5 D4 D3 ir2[1:0] r-0 r-0 rw-0 D2 D1 ig2[1:0] rw-0 rw-0 D0 ib2[1:0] rw-0 rw-0 rw-0 Maximum current for R2 driver ir2[1:0] Bits 5-4 ir2[2:0] Maximum output current 00 0.25×IMAX 01 0.50×IMAX 10 0.75×IMAX 11 1.00×IMAX Maximum current for G2 driver ig2[1:0] Bits 3-2 ig2[1:0] Maximum output current 00 0.25×IMAX 01 0.50×IMAX 10 0.75×IMAX 11 1.00×IMAX Maximum current for B2 driver ib2[1:0] Bits 1-0 ib2[1:0] Maximum output current 00 0.25×IMAX 01 0.50×IMAX 10 0.75×IMAX 11 1.00×IMAX 39 www.national.com LP3952 RGB2_MAX_CURRENT (13H) – RGB2 DRIVER INDIVIDUAL MAXIMUM CURRENT CONTROL REGISTER LP3952 AUDIO_SYNC_CTRL1 (2AH) – AUDIO SYNCHRONIZATION AND ADC CONTROL REGISTER 1 D7 D6 D5 gain_sel[2:0] rw-0 rw-0 D4 D3 D2 sync_mode en_agc en_sync rw-0 rw-0 rw-0 rw-0 D1 D0 input_sel[1:0] rw-1 rw-1 Input signal gain control gain_sel[2:0] gain, dB 000 0 (default) 001 3 010 6 Bits 7-5 gain_sel[2:0] 011 9 100 12 101 15 110 18 111 21 sync_mode Bit 4 Input filter mode control 0 – Amplitude mode 1 – Frequency mode en_agc Bit 3 0 – automatic gain control disabled 1 – automatic gain control enabled en_sync Bit 2 0 – audio synchronization disabled 1 – audio synchronization enabled ADC input selector input_sel[1:0] Input 00 Single ended input signal (ASE) 01 Not used Bits 1-0 input_sel[1:0] 10 Not used 11 No input (default) AUDIO_SYNC_CTRL2 (2BH) – AUDIO SYNCHRONIZATION AND ADC CONTROL REGISTER 2 D7 D6 D5 r-0 r-0 r-0 D4 D3 en_avg mode_ctrl[1:0] rw-0 en_avg Bit 4 mode_ctrl[1:0] Bits 3-2 D2 rw-0 www.national.com Bits 1-0 rw-0 0 – averaging disabled. fsample = 122 Hz, data in register changes every 8.2 ms. 1 – averaging enabled. fsample = 244 Hz, averaging of 64 samples, data in register changes every 262 ms (3.2Hz). Filtering mode control speed_ctrl[1:0] Response 00 FASTEST (default) 01 FAST 10 MEDIUM 11 SLOW 40 D0 speed_ctrl[1:0] rw-0 LEDs light response time to audio input speed_ctrl[1:0] D1 rw-0 LP3952 PATTERN CONTROL REGISTERS Command_[1:8]A – Pattern Control Register A D7 D6 D5 D4 rw-0 D3 r[2:0] D2 D1 rw-0 rw-0 rw-0 D1 D0 g[2:0] rw-0 rw-0 rw-0 D7 D6 D5 rw-0 rw-0 rw-0 D0 cet[3:2] Command_[1:8]B – Pattern Control Register B D4 cet[1:0] rw-0 D3 D2 rw-0 rw-0 b[2:0] tt[2:0] rw-0 rw-0 rw-0 Red color intensity r[2:0] current, % log=0 r[2:0] Bits 7-5A log=1 000 0×IMAX 0×IMAX 001 7%×IMAX 1%×IMAX 010 14%×IMAX 2%×IMAX 011 21%×IMAX 4%×IMAX 100 32%×IMAX 10%×IMAX 101 46%×IMAX 21%×IMAX 110 71%×IMAX 46%×IMAX 111 100%×IMAX 100%×IMAX Green color intensity g[2:0] current, % log=0 log=1 0×IMAX 0×IMAX 001 7%×IMAX 1%×IMAX 010 14%×IMAX 2%×IMAX 011 21%×IMAX 4%×IMAX 100 32%×IMAX 10%×IMAX 101 46%×IMAX 21%×IMAX 110 71%×IMAX 46%×IMAX 111 100%×IMAX 100%×IMAX 000 g[2:0] Bits 4-2A 41 www.national.com LP3952 Command execution time cet[3:0] Bits 1-0A 7-6B cet[3:0] CET duration, ms 0000 197 0001 393 0010 590 0011 786 0100 983 0101 1180 0110 1376 0111 1573 1000 1769 1001 1966 1010 2163 1011 2359 1100 2556 1101 2753 1110 2949 3146 1111 Blue color intensity b[2:0] current, % log=0 log=1 0×IMAX 0×IMAX 001 7%×IMAX 1%×IMAX 010 14%×IMAX 2%×IMAX 011 21%×IMAX 4%×IMAX 100 32%×IMAX 10%×IMAX 101 46%×IMAX 21%×IMAX 110 71%×IMAX 46%×IMAX 100%×IMAX 100%×IMAX 000 b[2:0] Bits 5-3B 111 Transition time tt[2:0] tt[2:0] Bits 2-0B Transition time, ms 000 0 001 55 010 110 011 221 100 442 101 885 110 1770 111 3539 RESET (60H) - RESET REGISTER D7 D6 D5 D4 D3 D2 D1 D0 w-0 w-0 Writing any data to Reset Register in address 60H can reset LP3952 w-0 www.national.com w-0 w-0 w-0 w-0 42 w-0 LP3952 Physical Dimensions inches (millimeters) unless otherwise noted The dimension for X1 ,X2 and X3 are as given: — X1=3.00 mm ±0.03 mm — X2=3.00 mm ±0.03 mm — X3=0.65 mm ±0.075 mm 36-bump Micro SMDxt Package, 3 x 3 x 0.65 mm, 0.5 mm pitch NS Package Number RLA36AAA See Application note AN1412 for PCB design and assembly instructions. 43 www.national.com LP3952 6-Channel Color LED Driver with Audio Synchronization Notes THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS, IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. TESTING AND OTHER QUALITY CONTROLS ARE USED TO THE EXTENT NATIONAL DEEMS NECESSARY TO SUPPORT NATIONAL’S PRODUCT WARRANTY. EXCEPT WHERE MANDATED BY GOVERNMENT REQUIREMENTS, TESTING OF ALL PARAMETERS OF EACH PRODUCT IS NOT NECESSARILY PERFORMED. NATIONAL ASSUMES NO LIABILITY FOR APPLICATIONS ASSISTANCE OR BUYER PRODUCT DESIGN. BUYERS ARE RESPONSIBLE FOR THEIR PRODUCTS AND APPLICATIONS USING NATIONAL COMPONENTS. PRIOR TO USING OR DISTRIBUTING ANY PRODUCTS THAT INCLUDE NATIONAL COMPONENTS, BUYERS SHOULD PROVIDE ADEQUATE DESIGN, TESTING AND OPERATING SAFEGUARDS. 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