N LM9823 3 Channel 48-Bit Color Scanner Analog Front End General Description Key Specifications The LM9823 is a high performance Analog Front End (AFE) for image sensor processing systems. It performs all the analog and mixed signal functions (correlated double sampling, color specific gain and offset correction, and analog to digital conversion) necessary to digitize the output of a wide variety of CIS and CCD sensors. The LM9823 has a 16 bit 6MHz ADC. • • • • • Features Applications • • • • • • • • • • • 6 million pixels/s conversion rate Digitally programmed gain and offset for red, green and blue color balancing Correlated Double Sampling for lowest noise from CCD sensors Compatible with CCD and CIS type image sensors Internal Voltage Reference Generation TTL/CMOS compatible input/output Output Data Resolution Pixel Conversion Rate Analog Supply Voltage I/O Supply Voltage Power Dissipation (typical) 16 Bits 6MHz 5V±5% 3.3V±10% or 5V±5% 375mW Color Flatbed Document Scanners Color Sheetfed Scanners Multifunction Imaging Products Digital Copiers General Purpose Linear Array Imaging Connection Diagram VBANDGAP VREFMID VA AGND OS R VREF+ OSG VREFOSB VA AGND SEN SDI SDO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 LM9823 28 pin SOIC 28 27 26 25 24 23 22 21 20 19 18 17 16 15 D7 D6 D5 D4 D3 D2 D1 D0 VD DGND CLMP VSMP MCLK SCLK Ordering Information Temperature Range 0°C ≤ TA ≤ +70°C Order Number Device Marking LM9823CCWM1 LM9823CCWMX2 LM9823CCWM LM9823CCWM NS Package Number M28B M28B Notes: 1 - Rail transport media, 26 parts per rail, 2 - Tape and reel transport media, 1000 parts per reel ©2000 National Semiconductor Corporation www.national.com LM9823 3 Channel 48-Bit Color Scanner Analog Front End October 2000 2 SEN SDO SDI SCLK BLUE OS from CCD GREEN OS from CCD RED OS from CCD OSB OSG OSR Serial Interface VCLAMP VA CDS CDS CDS 6 Offset DACB + + Offset DACG + + Offset DACR + + Static Offset DACs Timing and Control 1 x1or x3 x1or x3 x1or x3 Gain Boost MCLK CLMP VSMP AGND x0.93 to x3 x0.93 to x3 x0.93 to x3 5 Coarse Color Balance PGAs VA Internal Bandgap Reference 16-Bit ADC AGND 16 VD 16 bits to 8 bit Bytes DGND VBANDGAP VREF- VREFMID VREF+ D7 - D0 LM9823 Block Diagram www.national.com + Positive Supply Voltage (V =VA=VD) With Respect to GND=AGND=DGND Voltage On Any Input or Output Pin Input Current at any pin (Note 3) Package Input Current (Note 3) Package Dissipation at TA = 25°C ESD Susceptibility (Note 5) Human Body Model Machine Model Soldering Information Infrared, 10 seconds (Note 6) Storage Temperature 6.5V -0.3V to V +0.3V ±25mA ±50mA (Note 4) + 7000V 450V Operating Ratings (Notes 1& 2) Operating Temperature Range LM9823CCWM VA Supply Voltage VD Supply Voltage VD-VA OSR, OSG, OSB Input Voltage Range SCLK, SDI, SEN, MCLK, VSMP, CLMP Input Voltage Range TMIN≤TA≤TMAX 0°C≤TA≤+70°C +4.75V to +5.25V +3.0V to +5.25V ≤ 100mV -0.05V to VA + 0.05V -0.05V to VD + 0.05V 235°C -65°C to +150°C Electrical Characteristics The following specifications apply for AGND=DGND=0V, VA=+5.0VDC, VD=+3.0 or +5.0VDC, f MCLK=12MHz. Boldface limits apply for TA=TJ=TMIN to TMAX; all other limits TA=TJ=25°C. (Notes 7, 8, 12 & 16) Symbol Parameter Conditions Typical (Note 9) Limits (Note 10) Units (Limits) CCD/CIS Source Requirements for Full Specified Accuracy and Dynamic Range (Note 12) VOS PEAK Sensor’s Maximum Peak Differential Signal Range Gain = 0.933 Gain = 3.0 Gain = 9.0 2.1 0.65 0.21 V V V Full Channel Linearity (in units of 12 bit LSBs) (Note 14) DNL Differential Non-Linearity +0.9 -0.4 +2 -0.9 LSBs (max) INL Integral Non-Linearity Error (Note 11) ±2.2 +5 -7 LSBs (max) Analog Input Characteristics OSR, OSG, OSB Input Capacitance OSR, OSG, OSB Input Leakage Current 5 Measured with OS = 3.5VDC CDS disabled 20 CDS enabled 10 pF 25 µA (max) nA Coarse Color Balance PGA Characteristics Monotonicity 5 bits (min) V/V (min) V/V (max) G0 (Minimum PGA Gain) PGA Setting = 0 0.93 .90 .96 G31 (Maximum PGA Gain) PGA Setting = 31 3.0 2.95 3.07 V/V (min) V/V (max) x3 Boost Gain x3 Boost Setting On (Bit 5 of Gain Register is set) 3.0 2.86 3.08 V/V (min) V/V (max) ±0.3 1.6 % (max) Gain Error at any gain (Note 13) 3 www.national.com LM9823 Absolute Maximum Ratings (Notes 1& 2) LM9823 Electrical Characteristics (Continued) The following specifications apply for AGND=DGND=0V, VA=+5.0VDC, VD=+3.0 or +5.0VDC, f MCLK=12MHz. Boldface limits apply for TA=TJ=TMIN to TMAX; all other limits TA=TJ=25°C. (Notes 7, 8, 12 & 16) Symbol Parameter Conditions Typical (Note 9) Limits (Note 10) Units (Limits) Internal Reference Characteristics VREFMID Mid Reference Output Voltage 2.5 V VREF+ OUT Positive Reference Output Voltage 3.5 V VREF- OUT Negative Reference Output Voltage 1.5 V Differential Reference Voltage VREF+ OUT - VREF- OUT 2.0 V ∆VREF Static Offset DAC Characteristics (in units of 12 bit LSBs) Monotonicity 6 bits (min) Offset DAC LSB size PGA gain = 1 18.9 13 24 LSB (min) LSB (max) Offset DAC Adjustment Range PGA gain = 1 ±585 ±570 LSB (min) 2107 1934 2281 LSB (min) LSB (max) System Characteristics (in units of 12 bit LSBs) (see section 5.1, Internal Offsets) C Analog Channel Gain Constant (ADC Codes/V) Includes voltage reference variation, gain setting = 1 VOS1 Pre-Boost Analog Channel Offset Error, CCD Mode 17.3 -61 +94 LSB (min) LSB (max) VOS1 Pre-Boost Analog Channel Offset Error, CIS Mode 27 -49 +103 LSB (min) LSB (max) VOS2 Pre-PGA Analog Channel Offset Error -40 -124 +44 LSB (min) LSB (max) VOS3 Post-PGA Analog Channel Offset Error -38 -130 +55 LSB (min) LSB (max) DC and Logic Electrical Characteristics The following specifications apply for AGND=DGND=0V, VA=+5.0VDC, VD=+3.0 or +5.0VDC, fMCLK=12MHz. Boldface limits apply for TA=TJ=TMIN to TMAX; all other limits TA=TJ=25°C. (Notes 7 & 8) Symbol Parameter Conditions Typical (Note 9) Limits (Note 10) Units (Limits) SCLK, SDI, SEN, MCLK, VSMP, CLMP Digital Input Characteristics VIN(1) Logical “1” Input Voltage VA=5.25V 2.0 V (max) VIN(0) Logical “0” Input Voltage VA=4.75V 0.8 V (min) IIN Input Leakage Current VIN=VA VIN=DGND CIN Input Capacitance 0.1 -0.1 µA (max) µA (max) 5 pF D0-D7 Digital Output Characteristics VOUT(1) Logical “1” Output Voltage IOUT=-360µA 0.8*VD V (min) VOUT(0) Logical “0” Output Voltage IOUT=1.6mA 0.2*VD V (max) 4 www.national.com The following specifications apply for AGND=DGND=0V, VA=+5.0VDC, VD=+3.0 or +5.0VDC, fMCLK=12MHz. Boldface limits apply for TA=TJ=TMIN to TMAX; all other limits TA=TJ=25°C. (Notes 7 & 8) Symbol Typical (Note 9) Limits (Note 10) Units (Limits) 75 108 mA (max) Power Down 675 900 µA (max) Operating 210 475 µA (max) 2 25 µA (max) Parameter Conditions Power Supply Characteristics Operating IA ID Analog Supply Current Digital Supply Current (Note 15) Power Down AC Electrical Characteristics The following specifications apply for AGND=DGND=0V, VA=+5.0VDC, VD=+3.0 or +5.0VDC, fMCLK=12MHz, except where noted otherwise. Boldface limits apply for TA=TJ=TMIN to TMAX; all other limits TA=TJ=25°C. (Notes 7& 8) Symbol Parameter f MCLK Maximum MCLK frequency tMCLK MCLK period Conditions Typical (Note 9) Limits (Note 10) Units (Limits) 12 MHz (min) 83 ns (min) MCLK duty cycle 40 60 %(min) %(max) tSCLK Serial Clock Period 1 tMCLK(min) tSEN Serial Enable high time 3 tMCLK(min) tSSU SDI setup time 1 ns (min) tSH SDI hold time 3 ns (min) tSDDO SCLK edge to new valid data VD = 5.0V VD = 3.3V 8.5 19 20 ns (max) tVSU VSMP setup time 1 ns (min) tVH VSMP hold time 3 ns (min) tCSU CLMP setup time 1 ns (min) tCH CLMP hold time tDDO MCLK edge to new valid data VD = 5.0V VD = 3.3V 16 25 3 ns (min) 25 ns (max) ns (max) Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: All voltages are measured with respect to GND=AGND=DGND=0V, unless otherwise specified. Note 3: When the input voltage (VIN) at any pin exceeds the power supplies (V IN<GND or VIN >VA or VD ), the current at that pin should be limited to 25mA. The 50mA maximum package input current rating limits the number of pins that can simultaneously safely exceed the power supplies with an input current of 25mA to two. Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by T Jmax, Θ JA and the ambient temperature, TA . The maximum allowable power dissipation at any temperature is PD = (T Jmax - TA ) / Θ JA. TJmax = 150°C for this device. The typical thermal resistance (Θ JA) of this part when board mounted is 69°C/W for the M28B SOIC package. Note 5: Human body model, 100pF capacitor discharged through a 1.5kΩ resistor. Machine model, 200 pF capacitor discharged through a 0Ω resistor. Note 6: See AN450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in any National Semiconductor Linear Data Book for other methods of soldering surface mount devices. 5 www.national.com LM9823 DC and Logic Electrical Characteristics (Continued) LM9823 AC Electrical Characteristics (Continued) Note 7: Two diodes clamp the OS analog inputs to AGND and VA as shown below. This input protection, in combination with the external clamp capacitor and the output impedance of the sensor, prevents damage to the LM9823 from transients during power-up. VA TO INTERNAL CIRCUITRY OS Input AGND Note 8: To guarantee accuracy, it is required that VA and VD be connected to clean, low noise power supplies, with separate bypass capacitors at each supply pin. When both VA and VD are operated at 5.0V, they must be powered by the same regulator, with separate power planes or traces and separate bypass capacitors at each supply pin. Note 9: Typicals are at TJ =TA=25°C, f MCLK = 12MHz, and represent most likely parametric norm. Note 10: Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level). Note 11: Full channel integral non-linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that best fits the actual transfer function of the AFE. Note 12: The sensor’s maximum peak differential signal range is defined as the peak sensor output voltage for a white (full scale) image, with respect to the dark reference level. CIS Output Signal CCD Output Signal VRFT VREF V WHITE Black Level V WHITE Note 13: PGA Gain Error is the maximum difference between the measured gain for any PGA code and the ideal gain calculated by using the formula V 32 PGA code Gain PGA ---- = G 0 + X --------------------------- where X = ( G 31 – G 0 ) ------ . V 31 32 Note 14: Full Channel INL and DNL are tested with CDS disabled, negative signal polarity, DOE = 0, and a single OS input with a gain register setting of 1 (000001b) and an offset register setting of 0 (000000b). Note 15: The digital supply current (ID ) does not include the load, data and switching frequency dependent current required to drive the digital output bus on pins (D7 - D0). The current required to switch the digital data bus can be calculated from: ISW = 2*ND *P SW*C L*VD/tMCLK where N D is total number of data pins, PSW is the probability of each data bit switching, CL is the capacitive loading on each data pin, VD is the digital supply voltage and tMCLK is the period of the MCLK input. For most applications, ND is 8, PSW is ≈ 0.5, and VD is 5V, and the switching current can be calculated from: ISW = 40*C L/t MCLK . (With VD at 3.3V, the equation becomes: ISW = 26.4*CL/tMCLK.) For example, if the capacitive load on each digital output pin (D7 - D0) is 20pF and the period of t MCLK is 1/12MHz or 83ns, then the digital switching current would be 9.6mA. The calculated digital switching current will be drawn through the VD pin and should be considered as part of the total power budget for the LM9823. Note 16: All specifications quoted in LSBs are based on 12 bit resolution. 6 www.national.com LM9823 Typical Performance Characteristics Full Channel DNL and INL (Divide by 2, Monochrome Mode, 6 MHz Pixel Rate) Typical 16 Bit DNL 2 Typical 16 Bit INL 60 1.5 40 1 20 0.5 LSBs 0 LSBs 0 -20 -0.5 -40 -1 -60 0 16384 32768 49152 Output Code 65536 0 Typical 12 Bit DNL 1 16384 32768 49152 Output Code 65536 Typical 12 Bit INL 3 2 0.5 1 LSBs 0 0 LSBs -1 -0.5 -2 -1 -3 0 1024 2048 3072 Output Code 4096 0 1024 2048 3072 Output Code 4096 Note: The LM9823 provides 16-bit data for high resolution imaging applications. The typical full channel device performance is shown in the above graphs. In many applications, particularly those where high speed is important, or where lower cost CCD and CIS sensors are used, the signal source is only accurate to 12 bits. In these applications, only 12-bit of data may be used. 12-bit DNL and INL plots have also been provided to illustrate the performance of the LM9823 in these applications. 7 www.national.com LM9823 Pin Descriptions Analog Power VA The two VA pins are the analog supply pins. They should be connected to a voltage source of +5V and bypassed to AGND with a 0.1µF monolithic capacitor in parallel with a 10µF tantalum capacitor. AGND These two pins are the ground returns for the analog supplies. VD This is the positive supply pin for the digital I/O pins. It should be connected to a voltage source between +3.3V and +5.0V and be bypassed to DGND with a 0.1µF monolithic capacitor in parallel with a 10µF tantalum capacitor. DGND Data Output D7-D0 Data Output pins. The 16 bit conversion results of the ADC are multiplexed in 8 bit bytes to D7-D0 synchronous with MCLK. The MSB consists of data bits d15-d8 on pins D7-D0 and the LSB consists of d7-d0 on pins D7-D0. Serial Input/Output SCLK Serial Shift Clock. Input data on SDI is valid on the rising edge of SCLK. The minimum SCLK period is 1 tMCLK. SDO Serial Data Output. Data bits are shifted out of SDO on falling edges of SCLK. The first eight falling edges of SCLK after SEN goes low will shift out eight data bits (MSB first) from the configuration register addressed during the previous SEN low time. SDI Serial Data Input. A read/write bit, followed by a four address bits and eight data bits is shifted into SDI, MSB first. Data should be valid on the rising edge of SCLK. If the read/write bit is a “0” (a write), then the shifted data bits will be stored. If the read/write bit is a “1” (a read), then the data bits will be ignored, and SDO will shift out the addressed register’s contents during the next SEN low time. SEN Shift enable and load signal. When SEN is low, data is shifted into SDI. When SEN goes high, the last thirteen bits (one read/write, four address and eight data) shifted into SDI will be used to program the addressed configuration register. SEN must be high for at least 3 MCLK cycles between SEN low times. This is the ground return for the digital supply. Analog Input/Output OSR, OSG, OSB VREF+, VREFMID, VREF- Analog Inputs. These inputs (for Red, Green, and Blue) should be tied to the sensor’s OS (Output Signal) through DC blocking capacitors. Voltage reference bypass pins. VREF+, VREFMID, and VREF- should each be bypassed to AGND through a 0.1µF monolithic capacitor. Timing Control MCLK Master clock input. The ADC conversion rate will be 1/2 of MCLK. 12MHz is the maximum frequency for MCLK. VSMP Sample timing input signal. If VSMP is high on the rising edge of MCLK, the input is sampled on the rising edge of the next MCLK. The reference signal for the next pixel will be sampled one to four MCLKs later, depending on the value in the CDSREF configuration bits. If CDS is not enabled, the internal reference will be sampled during the reference sample time. Connection Diagram The number of MCLK cycles between VSMP pulses determines the pixel rate. Timing Diagrams 1 through 6 illustrate the VSMP timings for all the valid pixel rates. VBANDGAP VREFMID VA AGND OSR Note: See the applications section of the datasheet for the proper timing relationships between VSMP and MCLK. CLMP VREF+ OSG VREF- Clamp timing input. If CLMP and VSMP are high on the rising edge of MCLK, all three OS inputs will be internally connected to VCLAMP during the next pixel. VCLAMP is either VREF+ or VREF- depending on the state of the Signal Polarity bit in the Sample Mode register (Reg. 0, Bit 4). OSB VA AGND SEN SDI SDO 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 LM9823 28 pin SOIC 28 27 26 25 24 D7 23 22 21 20 19 18 17 16 15 D2 D6 D5 D4 D3 D1 D0 VD DGND CLMP VSMP MCLK SCLK www.national.com LM9823 Timing Diagrams OSR, OSG, OSB MCLK VSMP ADC Clock (internal) Sample Signal Level Sample Reference Level N-1 N N D7 -D0 GH GL BH N+1 BL RH N-5 N-5 DOE (Register 0, Bit 4) = 0 RL GH N-4 GL BH N-4 BL RH N-4 H = d15-d8 L = d7-d0 Diagram 1: Divide by 6 Color Mode Sample and Data Output Timing OSG MCLK VSMP ADC Clock (internal) Sample Signal Level Sample Reference Level N-1 N N D7 -D0 XX XX XX N+1 XX GH GL XX XX XX XX GH N-4 H = d15-d8 DOE (Register 0, Bit 4) = 0 L = d7-d0 Diagram 2: Divide by 6 Monochrome Mode Sample and Data Output Timing (Green Input shown) OSR, OSG, OSB MCLK VSMP ADC Clock (internal) Sample Signal Level Sample Reference Level D7 -D0 N-1 N N XX RH RL GH N+1 GL BH N-4 N-4 DOE (Register 0, Bit 4) = 0 BL XX XX RH N-4 RL GH N-3 H = d15-d8 L = d7-d0 Diagram 3: Divide by 8 Color Mode Sample and Data Output Timing 9 www.national.com LM9823 Timing Diagrams (continued) OSG MCLK VSMP ADC Clock (internal) Sample Signal Level Sample Reference Level D7 -D0 N N-1 N XX GH GL N+1 XX XX XX XX XX XX GH N-4 DOE (Register 0, Bit 4) = 0 GL XX N-3 H = d15-d8 L = d7-d0 Diagram 4: Divide by 8 Monochrome Mode Sample and Data Output Timing (Green Input Shown) OSG MCLK VSMP ADC Clock (internal) Sample Signal Level Sample Reference Level D7 -D0 N-1 N+1 N N N+1 N+2 N+2 CDSREF = 00 GH GL GH GL N-11 DOE (Register 0, Bit 4) = 0 GH GL N-10 GH GL N-9 H = d15-d8 L = d7-d0 Diagram 5: Divide by 3 Monochrome Mode Sample and Data Output Timing (Green Input shown) OSG MCLK VSMP ADC Clock (internal) Sample Signal Level Sample Reference Level D7 -D0 N-1 N N-1 N+2 N+1 N N+1 N+2 N+3 N+3 N+4 CDSREF = 00 GH GL N-11 GH GL GH N-10 GL N-9 GH GL N-8 GH GL N-7 H = d15-d8 DOE (Register 0, Bit 4) = 0 L = d7-d0 Diagram 6: Divide by 2 Monochrome Mode Sample and Data Output Timing (Green Input shown) 10 www.national.com LM9823 Timing Diagrams (continued) OSR, OSG, OSB MCLK VSMP Sample Signal Sample Reference CDSREF=00 D3 -D0 CDSREF=01 CDSREF=10 CDSREF=11 Diagram 7: Programmable Reference Sample Timing OS MCLK VSMP CLMP N-1 Sample Signal N+1 N N Sample Reference N+1 N+2 N+2 CDSREF = 00 Clamp On (internal signal) Diagram 8: Clamp Timing With SMPCL = 0 OS MCLK VSMP CLMP N-1 Sample Signal N+1 N N Sample Reference N+1 N+2 N+2 CDSREF = 00 Clamp On (internal signal) Diagram 9: Clamp Timing With SMPCL = 1 SCLK SEN SDI XX 0 R/W bit A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 XX Diagram 10: Configuration Register Serial Write Timing SCLK SEN SDI XX 1 SDO A3 - A0 XX XX 1 A3 - A0 b7 - b0 R/W bit Diagram 11: Configuration Register Serial Read Timing 11 www.national.com LM9823 Timing Diagrams (continued) tSCLK 1/2 tSCLK 1/2 tSCLK SCLK tSEN SEN tSSU SDI tSH D2 tSSU D1 D0 XX R/W A3 A2 tSH A1 A0 D7 D4 D3 D2 tSDDO SDO XX D7 D6 D5 Diagram 12: Serial Input and Output Timing tMCLK MCLK tVSU tVH tCSU tCH VSMP CLMP tDDO DOE = 1 D7 - D0 tDDO DOE = 0 D7 - D0 Diagram 13: MCLK, VSMP and CLMP Input Timing and Data Output Timing 12 www.national.com LM9823 Table 1: Configuration Register Address Table Address (Binary) Register Name and Bit Definitions A3 A2 A1 A0 0 0 0 0 B7 B6 B5 B4 B3 B2 B1 B0 Sample Mode (Power Up Default = 62h) I/O Mode DOE CDS Polarity SMPCL CDSREF1 CDSREF0 PD Red Offset Setting (Power Up Default = 00h) 0 0 0 1 N/A N/A Polarity MSB LSB Green Offset Setting (Power Up Default = 00h) 0 0 1 0 N/A N/A Polarity MSB LSB Blue Offset Setting (Power Up Default = 00h) 0 0 1 1 N/A N/A Polarity MSB LSB Red Gain Setting (Power Up Default = 00h) 0 1 0 0 N/A N/A x3 MSB LSB Green Gain Setting (Power Up Default = 00h) 0 1 0 1 N/A N/A x3 MSB LSB Blue Gain Setting (Power Up Default = 00h) 0 1 1 0 N/A N/A x3 MSB LSB Color Mode (Power Up Default = 00h) 0 1 1 1 N/A N/A N/A N/A N/A N/A CM1 CM0 0 0 0 0 0 0 Test Register 0 (Power Up Default = 00h) 1 0 0 0 0 0 0 0 0 0 Test Register 1 (Power Up Default = 10h) 1 0 0 1 0 0 0 1 0 0 Test Register 2 (Power Up Default = 00h) 1 0 1 0 0 0 0 13 0 0 0 www.national.com LM9823 Table 2: Configuration Register Parameters Note: Power-Up Default Register Settings are shown in Bold Italics Parameter (Address) Control Bits Result Sample Mode (0) I/O Mode (0) DOE (Data Output Edge) (0) B7 0 1 B6 0 Normal Output Driver Operation Reduced Slew Rate Output Driver Operation 1 D7-D0 are clocked out (change) on the falling edge of MCLK - Recommended setting for lowest noise and best overall performance. D7-D0 are clocked out (change) on the rising edge of MCLK CDS (Enable) (0) B5 0 1 CDS disabled (CIS) CDS Enabled (CCD) Signal Polarity (0) B4 0 1 Negative Polarity (CCD) Clamping to VREF+ Positive Polarity (CIS) Clamping to VREF- SMPCL (0) B3 0 1 Clamp is on for 1 MCLK before reference sampled Clamp is on between the reference and the signal sample points CDSREF (0) B2 0 0 1 1 PD (Power Down) (0) B0 0 1 B1 0 1 0 1 Reference Reference Reference Reference (for pixel N+1) sampled 1 MCLK cycle after (for pixel N+1) sampled 2 MCLK cycle after (for pixel N+1) sampled 3 MCLK cycle after (for pixel N+1) sampled 4 MCLK cycle after signal (for pixel N) sampled signal (for pixel N) sampled signal (for pixel N) sampled signal (for pixel N) sampled Operating Low Power Standby 14 www.national.com LM9823 Table 2: Configuration Register Parameters (Continued) Note: Power-Up Default Register Settings are shown in Bold Italics Parameter (Address) Control Bits Result Red, Green and Blue Offset DAC Settings (1, 2 & 3) Offset Polarity B5 0 1 Offset Value B4(MSB) B3 B2 B1 B0(LSB) B4 (MSB) 0 0 0 ••• 1 1 0 0 0 ••• 1 1 B3 B2 B1 Typical Offset Values B5 (SIGN) 0 0 0 ••• 0 0 1 1 1 ••• 1 1 0 0 0 ••• 1 1 0 0 0 ••• 1 1 0 0 0 ••• 1 1 0 0 0 ••• 1 1 0 0 1 ••• 1 1 0 0 1 ••• 1 1 Positive Offset Negative Offset Typical Offset = 20LSBs * Offset Value * PGA Gain Typical Offset (with PGA Gain = 1) B0 (LSB) 0 1 0 ••• 0 1 0 1 0 ••• 0 1 12 bit LSBs 0.00 +20 +40 ••• +600 +620 0 -20 -40 ••• -600 -620 Red, Green and Blue Gain Settings (4, 5 & 6) Boost Gain Enable B5 0 1 PGA Gain Value B4(MSB) Boost Gain = 1V/V Boost Gain = 3V/V B3 B2 Gain Typical Gain Values B1 B0(LSB) PGA Gain (V/V) =.933 + 0.0667 * (PGA Gain Value) Gain = Boost Gain * PGA Gain B5 (x3) 0 0 0 ••• 0 0 0 ••• 1 1 1 ••• 1 1 1 B4 (MSB) 0 0 0 ••• 1 1 1 ••• 0 0 0 ••• 1 1 1 B3 B2 B1 0 0 0 ••• 1 1 1 ••• 0 0 0 ••• 1 1 1 0 0 0 ••• 1 1 1 ••• 0 0 0 ••• 1 1 1 0 0 1 ••• 0 1 1 ••• 0 0 1 ••• 0 1 1 15 B0 (LSB) 0 1 0 ••• 1 0 1 ••• 0 1 0 ••• 1 0 1 Typical Gain (V/V) 0.93 1.00 1.07 ••• 2.87 2.93 3.00 ••• 2.79 3.00 3.20 ••• 8.60 8.80 9.00 www.national.com LM9823 Table 2: Configuration Register Parameters (Continued) Note: Power-Up Default Register Settings are shown in Bold Italics Parameter (Address) Control Bits Result Color Mode (7) Color Mode B1 0 0 1 1 B0 0 1 0 1 Color Monochrome - Red Monochrome - Green Monochrome - Blue Reserved Register 0 (8) Reserved Register 0 00000000 Reserved, always set to 00h. Reserved Register 1 (9) Reserved Register 1 00010000 Reserved, always set to 10h. Reserved Register 2 (A) Reserved Register 2 00000000 Reserved, always set to 00h. 16 www.national.com of Q1, and other sources of error. When the shift register clock (Ø1) makes a low to high transition (period 4), the electrons from the next pixel flow into C1. The charge across C1 now contains the voltage proportional to the number of electrons plus VRESIDUAL, an error term. If OS is sampled at the end of period 3 and that voltage is subtracted from the OS at the end of period 4, the VRESIDUAL term is canceled and the noise on the signal is reduced ([VSIGNAL+VRESIDUAL]-VRESIDUAL = VSIGNAL). This is the principal of Correlated Double Sampling. 1.0 Introduction The LM9823 is a high performance scanner Analog Font End (AFE) for image sensor processing systems. It is designed to work with color CCD and CIS image sensors and provides a full 3 channel sampling, gain and offset correction system, coupled with a 16 bit high speed analog to digital converter. A typical application of the LM9823 is in a color flatbed document scanner. The image sensing and processing portion of the system would be configured similar to that shown in Figure 1. 3.0 CIS Mode (CDS Off, Selectable Signal Polarity) The also LM9823 supports CIS (Contact Image Sensor) devices. The output signal of a CIS sensor (Figure 3) differs from a CCD signal in two primary ways: its output usually increases with increasing signal strength, and it does not usually have a reference level as an integral part of the output waveform of every pixel. To Host ASIC OSR AFE Control LM9823 CCD CCD Control OSG OSB 8 8 Output Data OS (CIS) RAM Other scanner elements omitted for simplicity. Figure 1. LM9823 in Basic Color Scanner OS (CCD) 2.0 CDS Correlated Double Sampler 1 The LM9823 uses a high-performance CDS (Correlated Double Sampling) circuit to remove many sources of noise and error from the image sensor output signal. It also supports CIS image sensors with a single ended sampling mode. 2 3 4 5 Figure 3. CIS When the LM9823 is in CIS (CDS off) mode (Register 0, B5=1), it uses either VREF+ or VREF- as the reference (or black) voltage for each pixel (depending on the signal polarity setting (Register 0, Bit 4)). If the signal polarity is set to one, then VREF- will be sampled as the reference level. If it is set to zero, then VREF+ will be sampled as the reference level. Figure 2 shows the output stage of a typical CCD and the resulting output waveform: VDD Q1 C1 RS (RESET) 4.0 Programmable Gain e- Q2 The output of the Sampler drives the input of the x3 Boost gain stage. The gain of each x3 Boost gain is 3V/V if bit B5 of that color’s gain register (register 4,5, or 6) is set, or 1V/V if bit B5 is cleared. The output of each x3 gain stage is the input an offset DAC and the output of each offset DAC is the input to a PGA (Programmable Gain Amplifier). Each PGA provides 5 bits of gain correction over a 0.93V/V to 3V/V (-0.6 to 9.5dB) range. The x3 Boost gain stage and the PGA can be combined for an overall gain range of 0.93V/V to 9.0V/V (-.6 to 19dB). The gain setting for each color (registers 4, 5 and 6) should be set during calibration to bring the maximum amplitude of the strongest pixel to a level just below the desired maximum output from the ADC. The PGA gain is determined by the following equation: V PGA Gain ---- = 0.933 + .0667 (value in bits B4-B0) V Equation 1. PGA Gain OS (from shift register) VSS Ø1 RS OS 1 2 3 4 5 Figure 2. CDS Capacitor C1 converts the electrons coming from the CCD’s shift register to an analog voltage. The source follower output stage (Q2) buffers this voltage before it leaves the CCD. Q1 resets the voltage across capacitor C1 between pixels at intervals 2 and 5. When Q1 is on, the output signal (OS) is at its most positive voltage. After Q1 turns off (period 3), the OS level represents the residual voltage across C1 (VRESIDUAL). VRESIDUAL includes charge injection from Q1, thermal noise from the ON resistance If the x3 Boost gain is enabled then the overall signal gain will be three times the PGA gain. 17 www.national.com LM9823 Applications Information LM9823 Applications Information (Continued) beginning of every line, the LM9823 implements a clamping function. The clamping function is initiated by asserting the CLMP input. If CLMP and VSMP are both high on a rising edge of MCLK, all three OS inputs will be internally connected to VREF+ or VREF- during the next pixel, depending on bit 4 of register 0. If bit 4 is set to one (positive signal polarity), then the OS input will be connected to VREF-. If bit 4 is set to zero (negative signal polarity), then it will be connected to VREF+. 5.0 Offset DAC The Offset DACs remove the DC offsets generated by the sensor and the LM9823’s analog signal chain (see section 5.1, Internal Offsets). The DAC value for each color (registers 1,2 and 3) should be set during calibration to the lowest value that still results in an ADC output code greater than zero for all the pixels when scanning a black line. With a PGA gain of 1V/V, each LSB of the offset DAC typically adds the equivalent of 20 ADC LSBs, providing a total offset adjustment range of ±590 ADC LSBs. The Offset DAC’s output voltage is given by: 6.1 Clamp Capacitor Selection The output signal of many sensors rides on a DC offset (greater than 5V for many CCDs) which is incompatible with the LM9823’s 5V operation. To eliminate this offset without resorting to additional higher voltage components, the output of the sensor is AC coupled to the LM9823 through a DC blocking capacitor, C CLAMP. The sensor’s DOS output, if available, is not used. The value of this capacitor is determined by the leakage current of the LM9823’s OS input and the output impedance of the sensor. The leakage through the OS input determines how quickly the capacitor value will drift from the clamp value of VREF+ or VREF-, which then determines how many pixels can be processed before the droop causes errors in the conversion (±0.1V is the recommended limit for CDS operation). The output impedance of the sensor determines how quickly the capacitor can be charged to the clamp value during the black reference period at the beginning of every line. V DAC = 9.75mV • (value in B4 - B0) Equation 2. Offset DAC Output Voltage In terms of 12 bit output codes, the offset is given by: Offset = 20LSBs • (value in B4 - B0) • PGA Gain Equation 3. Offset in ADC Output Codes The offset is positive if bit B5 is cleared and negative if B5 is set. Since the analog offset is added before the PGA gain, the value of the PGA gain must be considered when selecting the offset DAC values. 5.1 Internal Offsets Figure 4 is a model of the LM9823’s internal offsets. Equation 4 shows how to calculate the expected output code given the input voltage (VIN), the LM9823 internal offsets (VOS1, VOS2, VOS3), the programmed offset DAC voltage (VDAC), the programmed gains (GB, GPGA) and the analog channel gain constant C. The minimum clamp capacitor value is determined by the maximum droop the LM9823 can tolerate while converting one sensor line. The minimum clamp capacitor value is much smaller for CDS mode applications than it is for CIS mode applications. C is a constant that combines the gain error through the AFE, reference voltage variance, and analog voltage to digital code conversion into one constant. Ideally, C = 2048 codes/V (4096 codes/2V) in 12 bit LSBs. Manufacturing tolerances widen the range of C (see Electrical Specifications). x3 Boost 1V/V or 3V/V VIN + Σ GB + VOS1 Inside LM9823 VIN OS CS CCLAMP + + Σ + Σ GPGA Σ + + + VOS3 VOS2 VDAC ADC P2 P1 PGA 0.93V/V to 3V/V CI + CDS Mode Input Circuitry DOUT Inside LM9823 C I Offset DAC VIN Figure 4. Internal Offset Model OS P2 CCLAMP CS P1 + VREF D OUT = ( ( ( VIN + V O S1 )GB + VDAC + V OS2 )G PG A + VOS3 )C Equation 4. Output code calculation with internal offsets CIS Mode Input Circuitry Equation 5 is a simplification of the output code calculation, neglecting the LM9823’s internal offsets. Figure 5. Input Circuitry The LM9823 input current is considerably less when the LM9823 is operating in CDS mode. In CDS mode, the LM9823 average input current is no more than 25nA. With CDS disabled, which will likely be the case when CIS sensors are used, the LM9823 input impedance will be 1/(f Sample*CS). where fSample is the sample rate of the analog input and CS is 2pF. D O UT = ( VIN G B + VDAC )G PGA C Equation 5. Simplified output code calculation 6.0 Clamping 6.1.1 CDS mode Minimum Clamp Capacitor Calculation: To perform a DC restore across the AC coupling capacitors at the The following equation takes the maximum leakage current into 18 www.national.com CLMP is high. In this case the available charge time per line can be calculated using: the OS input, the maximum allowable droop, the number of pixels on the sensor, and the pixel conversion rate, fVSMP, and provides the minimum clamp capacitor value: Number of optical black pixels t CLAMP = ------------------------------------------------------------------------------2f VSMP i C CLAMP MIN = --------- dt dV leakage current (A) number of pixels = --------------------------------------------------- -------------------------------------------max droop(V) f VSMP Equation 12. Clamp Time Per Line Calculation For example, if a sensor has 18 black reference pixels and fVSMP is 2MHz with a 50% duty cycle, then tCLAMP is 4.5µs. Other “divide by” modes will have lower or higher clamp duty cycles accordingly, depending on the SMPCL setting. See Diagram 8, Clamp Timing With SMPCL = 0 and Diagram 9, Clamp Timing With SMPCL = 1. The following equation takes the number of optical black pixels, the amount of time (per pixel) that the clamp is closed, the sensor’s output impedance, and the desired accuracy of the final clamp voltage and provides the maximum clamp capacitor value that allows the clamp capacitor to settle to the desired accuracy within a single line: Equation 6. CDS mode CCLAMP MIN Calculation For example, if the OS input leakage current is 25nA worst-case, the sensor has 2700 active pixels, the conversion rate is 2MHz (tVSMP = 500ns), and the max droop desired is 0.1V, the minimum clamp capacitor value is: 25nA 2700 = -------------- --------------0.1V 2MHz = 340pF Equation 7. CDS mode C CLAMP MIN Example C CLAMP MIN t 1 = ------ -------------------------------R ln(accuracy) t CLAMP 1 = -------------------------- -------------------------------R CLAMP ln(accuracy) Equation 13. CCLAMP MAX for a single line of charge time C 6.1.2 CIS mode Minimum Clamp Capacitor Calculation: If CDS is disabled, then the maximum LM9823 OS input leakage current can be calculated from: I leakage = VSAT f SampCLK C SAMP CLAMP MAX Where tCLAMP is the amount of time (per line) that the clamp is on, RCLAMP is the output impedance of the CCD plus 50Ω for the LM9823 internal clamp switch, and accuracy is the ratio of the worst-case initial capacitor voltage to the desired final capacitor voltage. If t CLAMP is 4.5µs, the output impedance of the sensor is 1500Ω, the worst case voltage change required across the capacitor (before the first line) is 5V, and the desired accuracy after clamping is to within 0.1V (accuracy = 5/0.1 = 50), then: 4.5µs 1 C CLAMP MAX = ------------------ --------------1550Ω ln(50) = 728pF Equation 14. CCLAMP MAX Example The final value for CCLAMP should be less than or equal to CCLAMP MAX, but no less than C CLAMP MIN. Equation 8. CIS mode Input Leakage Current Calculation where VSAT is the peak pixel signal swing of the CIS OS output and CSAMP is the capacitance of the LM9823 internal sampling capacitor (2pF). Inserting this into Equation 6 results in: i C CLAMP MIN = --------- dt dV t SampCLK V SAT = ---------------------------C ----------------------------------- num pixels t SampCLK SAMP max droop(V) Equation 9. CIS mode CCLAMP MIN Calculation with CSAMP equal to 2pF and VSAT equal to 2V (the LM9823 maximum input signal), then Equation 9 reduces to: 4p(F)(V) CCLAMP MIN = ------------------------------------ num pixels max droop(V) In some cases, depending primarily on the choice of sensor, CCLAMP MAX may actually be less than CCLAMP MIN, meaning that the capacitor can not be charged to its final voltage during the black pixels at the beginning of a line and hold it’s voltage without drooping for the duration of that line. This is usually not a problem because in most applications the sensor is clocked continuously as soon as power is applied. In this case, a larger capacitor can be used (guaranteeing that the CCLAMP MIN requirement is met), and the final clamp voltage is forced across the capacitor over multiple lines. This equation calculates how many lines are required before the capacitor settles to the desired accuracy: C Initial Error Voltage CLAMP lines = R CLAMP ------------------------- ln ---------------------------------------------------- Final Error Voltage t CLAMP Equation 10. CIS mode C CLAMP MIN Calculation In CIS mode (CDS disabled), the max droop limit must be much more carefully chosen, since any change in the clamp capacitor’s DC value will affect the LM9823 conversion results. If a droop of one 10 bit LSB across a line is considered acceptable, then the allowed droop voltage is calculated as: 2V/1024, or approximately 2mV. If there are 2700 active pixels on a line then: 4p(F)(V) C CLAMP MIN = ---------------------- 2700 2mV = 5.4uF Equation 11. CIS mode CCLAMP MIN Calculation Example Equation 15. Number of Lines Required for Clamping 6.1.3 Maximum Clamp Capacitor Calculation: Using the values shown before and a clamp capacitor value of 0.01µF, this works out to be: 5V 0.01µF lines = 1550 ------------------- ln ------------ = 13.5 lines 4.5µs 0.1V Equation 16. Clamping Lines Required Example The maximum size of the clamp capacitor is determined by the amount of time available to charge it to the desired value during the optical black portion of the sensor output. The internal clamp occurs when CLMP and VSMP are both high on a rising edge of MCLK. If SMPCL=0, the clamps are on immediately before the sample reference time, if SMPCL=1, the clamps are on immediately after the sample reference time. If the LM9823 is operated in divide by 2 mode, then the clamp is on 50% of the time when In this example, a 0.01µF capacitor takes 14 lines after power-up to charge to its final value. On subsequent lines, the only error will be the droop across a single line which should be significantly 19 www.national.com LM9823 Applications Information (Continued) LM9823 Applications Information (Continued) to 1 to reduce the slew rate of the output drivers. less than the initial error. If the LM9823 is operating in CDS mode and multiple lines are used to charge up the clamping capacitors after power-up, then a clamp capacitor value of 0.01µF should be significantly greater than the calculated CCLAMP MIN value and can virtually always be used. 9.2 DOE (Data Output Edge) Setting The Data Output Edge bit selects which edge of MCLK is used to clock output data onto the output pins. For lowest noise performance, this bit should be set to 0. With this setting, new data is placed on the D7-D0 pins on every falling edge of MCLK. See Diagrams 1 through 6 and Diagram 13 for more information on data output timing for the different Divide By modes, and detailed timing of the output data signals. If the LM9823 is operating in CIS mode, then significantly larger clamp capacitors must be used. Fortunately, the output impedance of most CIS sensors is significantly smaller than the output impedance of CCD sensors, and RCLAMP will be dominated by the 50Ω from the LM9823 internal clamp switch. With a smaller RCLAMP value, the clamp capacitors will charge faster. The bit can be set to 1 to adjust the data output timing for some applications, but the noise performance of the LM9823 may be somewhat degraded. 7.0 Power Supply Considerations The LM9823 analog supplies (VA) should be powered by a single +5V source. The two analog supplies are brought out individually to allow separate bypassing for each supply input. They should not be powered by two or more different supplies. 9.3 CDS Enable The CDS Enable bit determines whether the sampling section of the LM9823 operates in Correlated Double Sampling mode or in Single Ended Sampling mode. CDS mode is normally used with CCD type sensors, while Single Ended mode is normally used with CIS type sensors. Each supply input should be bypassed to its respective ground with a 0.1µF capacitor located as close as possible to the supply input pin. A single 10µF tantalum capacitor should be placed near the VA supply pins to provide low frequency bypassing. 9.4 Signal Polarity The VD input can be powered at 3.3V or 5.0V. Power should be supplied by a clean, low noise linear power supply, with a 0.1µF ceramic capacitor and a 10µF tantalum capacitor placed near the VD and DGND pins. If possible, a separate power and ground plane should be provided to isolate the noisy digital output signals from the sensitive analog supply pins. If the VD voltage is lower than VA, a separate linear regulator should be used. If VD and VA are both at 5.0V, then they should be supplied by a common linear regulator, with separate analog and digital power and ground planes. Whether the LM9823 is operating in Correlated Double Sampling Mode, or Single Ended Sampling mode, the basic sampling operation is the same. First a reference level is sampled, then a signal level is sampled. For CDS mode operation, if the signal level is lower in voltage than the reference level, the Signal Polarity bit should be set to 0. This is the normal setting for CCD type sensors. If the signal level is more positive than the reference level, the Signal Polarity bit would be set to 1 for Positive Polarity mode. When Single Ended Mode is selected, the Signal Polarity bit determines which internal reference voltage is used to compare with the input signal. Most CIS type sensors have a positive polarity type output, and in this case the Signal Polarity Bit should be set to 1. In this case, the internal VREF- is used as the reference level during the Reference Sampling period. To minimize noise, keep the LM9823 and all analog components as far as possible from noise generators, such as switching power supplies and high frequency digital busses. If possible, isolate all the analog components and signals (OS, reference inputs and outputs, VA, AGND) on an analog ground plane, separate from the digital ground plane. The two ground planes should be tied together at a single point, preferably the point where the power supply enters the PCB. In addition, the Signal Polarity bit determines which internal reference voltage is used during the Clamping interval. If Signal Polarity = 0, VREF+ is used for clamping, if Signal Polarity = 1, VREF- is used. 8.0 Serial Interface and Configuration Registers The serial interface is used to program the configuration registers which control the operation of the LM9823. The SEN, SCLK, SDI and SDO signals are used to set and verify configuration register settings. In addition, MCLK must be active during all serial interface activity. MCLK is used to register the level of the SEN input and drives the logic that process information input on the SDI line. 9.5 SMPCL The SMPCL setting controls when the clamping action occurs during the acquisition cycle. If SMPCL is set to 0, the Clamp will be on for 1 MCLK before the reference sampling point. If SMPCL is set to 1, clamping will occur in the interval after the reference sampling point, and before the signal sampling point. In this case, the clamping time is dependent on the present “divide by” mode, and the settings of the CDSREF bits. 9.0 Sample Mode Register Settings A brief overview of the sample mode register and the bit locations is give in Table 2: Configuration Register Parameters on page 14. The function of each bit is summarized in the following sections. 9.6 CDSREF The CDSREF setting is provided to allow adjustable sampling points for the reference sample at the higher “divide by” modes. This may be useful to optimize the timing of the Reference Sampling point for particular CCD sensors. Diagram 7 shows how the various settings of CDSREF can be used to delay the Reference Sampling point. Care must be taken to avoid setting CDSREF to 9.1 Output Driver Mode The Output Driver Mode bit is normal set to 0. This bit can be set 20 www.national.com To clamp across multiple pixels in a row, CLMP can be set high and remain there for the entire number of pixels to be clamped, then returned to the low state for normal (signal) operation. This may simplify the timing required to generate the CLMP signal. an inappropriate value when operating in the lower “divide by” modes. Valid CDSREF settings are: “Divide By” Mode Valid CDSREF /8 00,01,10,11 /6 00,01,10,11 /3 00,01 /2 00 10.2 MCLK and VSMP Timing The relationship between VSMP and MCLK is used to determine the 'divide by' mode that is presently being used with the part. Valid 'divide by' settings are: Color - /8, /6 Monochrome - /8, /6, /3, /2 When entering a new mode, it is important to provide consistent MCLK/VSMP timing signals that meet the following condition. When switching to a new 'divide by' mode, VSMP should be held low for a minimum of 3 MCLK cycles, then valid timing according to the datasheet diagrams for the particular mode should be started. This ensures that all internal circuitry is properly synchronized to the new conversion 'divide by' mode being used. If the timing relationship between VSMP and MCLK is disturbed for any reason, the same procedure should be used before restarting operation in the chosen 'divide by' mode. 9.7 PD (Power Down) Mode A Power Down bit is provided to configure the LM9823 in a lower power Standby mode. In this mode, typical power consumption is reduced to less than 1% of normal operating power. The serial interface is still active, but the majority of the analog and digital circuitry is powered down. 10.0 LM9823 Basic Operation The normal operational sequence when using the LM9823 is as follows: Immediately after applying power, all configuration registers are reset to default settings. MCLK should be applied, and the appropriate values written to the registers using the procedure discussed in section 8.0 Serial Interface and Configuration Registers on page 20 and detailed in Diagrams 10, 11 and 12. Once the configuration registers are loaded, the timing control signals can be applied at the proper rates for the mode of conversion desired. MCLK is applied initially with VSMP and CLMP low. After at least 3 MCLKS, VSMP and CLMP signals can begin. The divide by mode is determined by the ratio of MCLK to VSMP frequency as described in section 10.2. For example: To change from monochrome divide by 3 mode to monochrome divide by 2 mode, VSMP should be held low for at least 3 MCLK cycles, then VSMP can be brought high using 'divide by 2' timing. If VSMP is not low for at least 3 MCLKs, the LM9823 may enter an unknown mode. MCLK VSMP Divide by 3 Transition (≥ 3 MCLK) Divide by 2 Diagram 6: Timing of Transitions between ‘Divide By’ Modes 16-Bit conversion results are placed on the data output pins as follows: The upper 8 bits are output first with bit 15 of the ADC on D7 and bit 8 of the ADC on D0. The lower 8 bits are then output with bit 7 of the ADC on D7 and bit 0 of the ADC on D0. The exact timing and conversion latency of the output data is affected by the settings of the DOE variable in the Sample Mode register, and the divide by mode of operation. If DOE = 0 (recommended setting for best performance), output data will change on the falling edge of MCLK. If DOE = 1, output data is updated on the rising edge of MCLK. See Diagrams 1 through 6 and Diagram 13 for more information on data output timing. 10.1 CLMP Operation The CLMP signal is used to engage the LM9823 internal clamp circuits at the proper time during the CCD or CIS data output cycle. If both CLMP and VSMP are high on a rising edge of MCLK, then CLMP will be applied during the next pixel. The exact timing of the internal Clamp signal is determined by the divide by mode of operation and the setting of the SMPCL variable in the Sample Mode register. If SMPCL = 0, then the Clamp is on for 1 MCLK before the reference is sampled. If SMPCL = 1 then the clamp is on between the reference and the signal sample points. Please see Diagram 8 and Diagram 9 for a graphic example of this timing. 21 www.national.com LM9823 Applications Information (Continued) LM9823 3 Channel 48-Bit Color Scanner Analog Front End Physical Dimensions inches (millimeters) unless otherwise noted 28-Lead (0.300" wide) Molded Small Outline Package (JEDEC) Order Number LM9823CCWM NS Package Number M28B LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. N National Semiconductor National Semiconductor Europe Corporation Fax: +49 (0) 1 80-530 85 86 Americas Tel: 1-800-272-9959 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Ltd. Japan Ltd. Email: europe.support @ nsc.com National Semiconductor Asia Pacific Customer Response Group Deutsch Tel: +49 (0) 69 9508 6208 Tel: 65-2544466 Fax: 81-3-5639-7507 Fax: 1-800-737-7018 English Tel: +44 (0) 870 24 0 2171 Fax: 65-2504466 Email: support @ nsc.com Francais Tel: +33 (0) 1 41 91 8790 Email: [email protected] Tel: 81-3-5639-7560 http://www.national.com National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.