ISSI IS42VM16400G

IS42VM16400G
1M x 16Bits x 4Banks Low Power Synchronous DRAM
Description
These IS42VM16400G are Low Power 67,108,864 bits CMOS Synchronous DRAM organized as 4 banks of 1,048,576 words x 16 bits.
These products are offering fully synchronous operation and are referenced to a positive edge of the clock. All inputs and outputs are
synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve high bandwidth. All input and
output voltage levels are compatible with LVCMOS.
Features
ƒ JEDEC standard 1.8V power supply.
• Auto refresh and self refresh.
• All pins are compatible with LVCMOS interface.
• All inputs and outputs referenced to the positive edge of the
system clock.
• Data mask function by DQM.
• 4K refresh cycle
y
/ 64ms.
• Internal 4 banks operation
operation.
• Programmable Burst Length and Burst Type.
• Burst Read Single Write operation.
- 1, 2, 4, 8 or Full Page for Sequential Burst.
- 4 or 8 for Interleave Burst.
• Programmable CAS Latency : 2,3 clocks.
• Programmable Driver Strength Control
- Full Strength or 1/2, 1/4 of Full Strength
• Special Function Support.
- PASR(Partial Array Self Refresh)
- Auto TCSR(Temperature Compensated Self Refresh)
• Automatic precharge, includes CONCURRENT Auto Precharge
Mode and controlled Precharge.
• Deep Power Down Mode
Mode.
Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its
products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services
described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information
and before placing orders for products.
Integrated Silicon
S
S
Solution, Inc. does not recommend the use off any off its products in life
f support applications where the failure
f
or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or
effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to
its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
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1
IS42VM16400G
Figure1: 54Ball FBGA Ball Assignment
1
2
3
4
5
6
7
8
9
A
VSS
DQ15
VSSQ
VDDQ
DQ0
VDD
B
DQ14
DQ13
VDDQ
VSSQ
DQ2
DQ1
C
DQ12
DQ11
VSSQ
VDDQ
DQ4
DQ3
D
DQ10
DQ9
VDDQ
VSSQ
DQ6
DQ5
E
DQ8
NC
VSS
VDD
LDQM
DQ7
F
UDQM
CLK
CKE
/CAS
/RAS
/WE
G
NC
A11
A9
BA0
BA1
/CS
A8
A7
A6
A0
A1
A10
VSS
A5
A4
A3
A2
VDD
H
J
[Top View]
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IS42VM16400G
Table2: Pin Descriptions
Pin
Pin Name
Descriptions
CLK
System Clock
The system clock input. All other inputs are registered to the
SDRAM on the rising edge CLK.
CKE
Clock Enable
Controls internal clock signal and when deactivated, the SDRAM
will be one of the states among power down, suspend or self
refresh.
/CS
Chip Select
Enable or disable all inputs except CLK, CKE and DQM.
BA0 BA1
BA0~BA1
B k Add
Bank
Address
Selects ba
bank to
o be
b activated
a
a d during
du g RAS activity.
a
y
Selects bank to be read/written during CAS activity.
A0~A11
Address
Row Address
Column Address
Auto Precharge
/RAS, /CAS, /WE
Row Address Strobe,
Column Address Strobe,
Write Enable
RAS, CAS and WE define the operation.
Refer function truth table for details.
LDQM,UDQM
Data Input/Output Mask
C t l output
Controls
t tb
buffers
ff
iin read
d mode
d and
d masks
k input
i
t data
d t in
i
write mode.
DQ0~DQ15
Data Input/Output
Data input/output pin.
VDD/VSS
Power Supply/Ground
Power supply for internal circuits and input buffers.
VDDQ/VSSQ
Data Output Power/Ground
Power supply for output buffers.
NC
No Connection
No connection.
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: RA0~RA11
: CA0~CA7
: A10
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IS42VM16400G
Figure3: Functional Block Diagram
EXTENDED
MODE
REGISTER
CLK
CLOCK
CKE
GENERATOR
TCSR
ROW DECODER
ROW DECODER
ROW DECODER
ROW DECO
ODER
PASR
ADDRESS
ROW
MODE
REGISTER
ADDRESS
BUFFER &
REFRESH
COUNTER
BANK D
BANK C
BANK B
BANK A
SENSE AMPLIFIER
/CAS
/
/WE
CONTROL LOGIC
L
/RAS
COMMAND DE
ECODER
/CS
COLUMN DECODER
& LATCH CIRCUIT
COLUMN
ADDRESS
BUFFER &
BURST
COUNTER
DATA CONTROL CIRCUIT
DQM
LATCH CIRCUIT
INPUT & OUTPUT
BUFFER
DQ
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IS42VM16400G
Figure4: Simplified State Diagram
EXTENDED
MODE
REGISTER
SET
MODE
REGISTER
SET
SELF
REFRESH
MRS
ACT
DEEP
POWER
DOWN
POWER
DOWN
ROW
ACTIVE
WRITE A
SUSPEND
CKE ↓
CKE
CKE ↓
ACTIVE
POWER
DOWN
READ
PRE
E
WRITE
WRITE
SUSPEND
CBR
REFRESH
REF
IDLE
CKE ↓
READ
WRITE
READ
WRITE
CKE
CKE
CKE ↓
CKE ↓
WRITE A
READ A
CKE
POWER
ON
CKE
PRECHARGE
READ
SUSPEND
READ A
SUSPEND
PRECHARGE
Automatic Sequence
Manual Input
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IS42VM16400G
Figure5: Mode Register Definition
BA1
BA0
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Bus
13
11
12
0
0
0
10
9
8
WB
0
7
0
6
5
4
CAS Latency
0
3
BT
2
1
0
Mode Register (Mx)
Burst Length
M9
Write Burst Mode
M6
M5
M4
CAS Latency
M3
Burst Type
0
Burst Read and Burst Write
0
0
0
Reserved
0
Sequential
1
Burst Read and Single Write
0
0
1
-
1
Interleave
0
1
0
0
1
1
M2
M1
M0
0
0
2
0
1
3
0
0
1
0
1
1
Burst Length
M3 = 0
M3 = 1
0
1
1
0
1
2
2
0
1
0
4
4
Reserved
0
1
1
8
8
1
Reserved
1
0
0
Reserved
Reserved
1
0
Reserved
1
0
1
Reserved
Reserved
1
1
Reserved
1
1
0
Reserved
Reserved
1
1
1
Full Page
Reserved
Note: M13/M12(BA1/BA0) must be set to “0/0” to select Mode Register (vs. the Extended Mode Register)
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is
selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column
add ess as shown
address,
sho n in Table 3.
3
Table 3: Burst Definition
Burst
Length
Starting Column
Address
A2
0
8
Note :
Sequential
Interleaved
0
0-1
0-1
1
1-0
1-0
0
0
0-1-2-3
0-1-2-3
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
2-3-0-1
1
1
3-0-1-2
3-2-1-0
0
0
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
block-of-eight burst; A0-A2 select the starting column
within the block.
A1
2
4
Order of Access Within a Burst
A0
0
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2
3456701
2-3-0-1-6-7-4-5
2
3016745
0
1
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
0
4-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
Full
n=A0 7
n=A0-7
Page
(Location 0-255)
Rev. A | July 2010
1. For full-page accesses: y = 256
2. For a burst length of two, A1-A7 select the blockof-two burst; A0 selects the starting column within the
block.
3. For a burst length of four, A2-A7 select the blockof-four burst; A0-A1 select the starting column within
the block.
4. For a burst length of eight, A3-A7 select the
5. For a full-page burst, the full row is selected and A0-A7
select the starting column.
6. Whenever a boundary of the block is reached within a
given sequence above, the following access wraps
within the block.
7. For a burst length of one, A0-A7 select the unique
column to be accessed, and mode register bit M3 is
ignored.
Cn, Cn+1. Cn+2,
Cn+3, Cn+4…
Not Supported
…Cn-1, Cn...
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IS42VM16400G
Figure6: Extended Mode Register
BA1
BA0
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Bus
13
12
1
0
11
0
10
0
9
0
8
0
7
6
0
5
DS
4
0
3
2
0
1
0
Extended Mode Register (Ex)
PASR
E6
E5
Driver Strength
E2
E1
E0
Self Refresh Coverage
0
0
Full Strength
0
0
0
All Banks
0
1
1/2 Strength
0
0
1
Two Banks (BA1=0)
1
0
1/4 Strength
0
1
0
One Bank (BA1=BA0=0)
1
1
Reserved
0
1
1
Reserved
1
0
0
Reserved
1
0
1
Half of One Bank (BA1=BA0=0, Row Address MSB=0)
1
1
0
Quarter of One Bank (BA1=BA0=0, Row Address 2 MSB=0)
1
1
1
Reserved
Note: E13/E12(BA1/BA0) must be set to “1/0” to select Extend Mode Register (vs. the base Mode Register)
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IS42VM16400G
Functional Description
In general, this 64Mb SDRAM (1M x 16Bits x 4banks) is a multi-bank DRAM that operates at 1.8V and includes a synchronous
interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 16,777,216-bit banks is organized as
4,096 rows by 256 columns by 16-bits
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed
number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed
by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and
row to be accessed (BA0-BA1 select the bank, A0-A11 select the row). The address bits (BA0-BA1 select the bank, A0-A7 select the
column) registered coincident with the READ or WRITE command are used to select the starting column location for the burst access.
P i to
Prior
t normall operation,
ti
th SDRAM mustt be
the
b initialized.
i iti li d The
Th following
f ll i
sections
ti
provide
id detailed
d t il d information
i f
ti
covering
i
d i
device
initialization, register definition, command descriptions and device operation.
Power up and Initialization
SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in
undefined operation. Once power is applied to VDD and VDDQ(simultaneously) and the clock is stable(stable clock is defined as a
signal cycling within timing constraints specified for the clock pin), the SDRAM requires a 100µs delay prior to issuing any command
other than a COMMAND INHIBIT or NOP.
NOP CKE must be held high during the entire initialization period until the PRECHARGE command
has been issued. Starting at some point during this 100µs period and continuing at least through the end of this period, COMMAND
INHIBIT or NOP commands should be applied.
Once the 100µs delay has been satisfied with at least one COMMAND INHIBIT or NOP command having been applied, a PRECHARGE
command should be applied. All banks must then be precharged, thereby placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the SDRAM is
ready for mode register programming. Because the mode register will power up in an unknown state, it should be loaded prior to
applying any operational command. And a extended mode register set command will be issued to program specific mode of self
refresh operation(PASR). The following these cycles, the Low Power SDRAM is ready for normal operation.
Register Definition
Mode Register
The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst
length, a burst type, a CAS latency, an operating mode and a write burst mode. The mode register is programmed via the LOAD
MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power.
power
Mode register bits M0-M2 specify the burst length, M3 specifies the type of burst (sequential or interleaved), M4-M6 specify the CAS
latency, M7 and M8 specify the operating mode, M9 specifies the write burst mode, and M10-M12 should be set to zero. M13 should
be set to zero to prevent extended mode register.
The mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the
subsequent operation. Violating either of these requirements will result in unspecified operation.
Extended Mode Register
The Extended Mode Register controls the functions beyond those controlled by the Mode Register. These additional functions are
special features of the BATRAM device. They include Partial Array Self Refresh (PASR) and Driver Strength (DS).
The Extended Mode Register is programmed via the Mode Register Set command and retains the stored information until it is
programmed again or the device loses power.
The Extended Mode Register must be programmed with M7 through M11 set to “0”. The Extended Mode Register must be loaded when
all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent
operation. Violating either of these requirements results in unspecified operation.
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IS42VM16400G
Burst Length
Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in Figure 1. The burst
length determines the maximum number of column locations that can be accessed for a given READ or WRITE command.
command Burst
lengths of 1, 2, 4 or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is available
for the sequential type. The full-page burst is used in conjunction with the BURST TERMINATE command to generate arbitrary burst
lengths.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE
command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-A7 when
the burst length
g is set to two;; byy A2-A7 when the burst length
g is set to four;; and byy A3-A7 when the burst length
g is set to eight.
g
The
remaining (least significant) address bit(s) is (are) used to select the starting location within the block. Full-page bursts wrap within
the page if the boundary is reached.
Bank(Row) Active
The Bank Active command is used to activate a row in a specified bank of the device. This command is initiated by activating CS, RAS and
deasserting CAS, WE at the positive edge of the clock. The value on the BA0-BA1 selects the bank, and the value on the A0-A11selects
the row.
This row remains active for column access until a precharge command is issued to that bank. Read and write operations can only be
initiated on this activated bank after the minimum tRCD time is passed from the activate command.
Read
The READ command is used to initiate the burst read of data. This command is initiated by activating CS, CAS, and deasserting WE, RAS at
the positive edge of the clock. BA0-BA1 input select the bank, A0-A7 address inputs select the starting column location. The value on input
A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected the row being accessed will be precharged at the
end of the READ burst; if Auto Precharge is not selected, the row will remain active for subsequent accesses. The length of burst and the
CAS latency will be determined by the values programmed during the MRS command.
Write
The WRITE command is used to initiate the burst write of data. This command is initiated by activating CS, CAS, WE and deasserting RAS
at the positive edge of the clock.
clock BA0-BA1 input select the bank
bank, A0-A7 address inputs select the starting column location.
location The value on
input A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected the row being accessed will be precharged at
the end of the WRITE burst; if Auto Precharge is not selected, the row will remain active for subsequent accesses.
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IS42VM16400G
CAS Latency
The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of
output data.
d
The
h latency
l
can be
b set to two or three
h
clocks.
l k Iff a READ command
d is registered
d at clock
l k edge
d
n, and
d the
h latency
l
is m
clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier (n + m 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the
clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to
two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in Figure 7. Reserved states should not be used
as unknown operation or incompatibility with future versions may result.
Figure7: CAS Latency
T0
T1
T2
T3
CLK
READ
COMMAND
NOP
NOP
tOH
tLZ
DQ
Dout
tAC
CAS Latency=2
T0
T1
T2
T3
T4
CLK
COMMAND
READ
NOP
NOP
tLZ
DQ
NOP
tOH
Dout
tAC
CAS Latency=3
DON’T CARE
UNDEFINED
Operating Mode
The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved
for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts. Test modes and reserved
states should not be used because unknown operation or incompatibility with future versions may result.
Write Burst Mode
When M9 = 0, the burst length programmed via M0-M2 applies to both READ and WRITE bursts; when M9 = 1, the programmed
burst length applies to READ bursts, but write accesses are single-location (nonburst) accesses.
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IS42VM16400G
Table4: Command Truth Table
Function
CKEn-1
CKEn
/CS
/RAS
/CAS
/WE
DQM
Command Inhinit (NOP)
H
X
H
X
X
X
X
X
No Operation (NOP)
H
X
L
H
H
H
X
X
Mode Register Set
H
X
L
L
L
L
X
OP CODE
4
Extended Mode Register Set
H
X
L
L
L
L
X
OP CODE
4
Active (select bank and
activate row)
H
X
L
L
H
H
X
Bank/Row
Read
H
X
L
H
L
H
L/H
Bank/Col
L
5
Read with Autoprecharge
H
X
L
H
L
H
L/H
Bank/Col
H
5
Write
H
X
L
H
L
L
L/H
Bank/Col
L
5
Write with Autoprecharge
H
X
L
H
L
L
L/H
Bank/Col
H
5
Precharge All Banks
H
X
L
L
H
L
X
X
H
Precharge
g Selected Bank
H
X
L
L
H
L
X
Bank
L
Burst Stop
H
H
L
H
H
L
X
X
Auto Refresh
H
H
L
L
L
H
X
X
3
Self Refresh Entry
H
L
L
L
L
H
X
X
3
Self Refresh Exit
L
H
H
X
X
X
L
H
H
H
X
X
2
Precharge Power Down Entry
H
L
H
X
X
X
L
H
H
H
X
X
Precharge Down Exit
L
H
H
X
X
X
L
H
H
H
X
X
Clock Suspend Entry
H
L
H
X
X
X
L
V
V
V
X
X
Clock Suspend Exit
L
H
X
X
Deep Power Down Entry
H
L
X
X
Deep Power Down Exit
L
H
X
X
X
L
H
H
X
L
ADDR
A10
Note
6
Note :
1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.
H: High Level, L: Low Level, X: Don't Care, V: Valid
2. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high and will put the device in the all banks idle state once
tXSR is met. Command Inhibit or NOP commands should be issued on any clock edges occuring during the tXSR period. A minimum
of two NOP commands must be provided during tXSR period.
3. During refresh operation, internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
4. A0-A11 define OP CODE written to the mode register, and BA1/BA0 must be issued “0/0” in the mode register set, and “1/0”
in the extended mode register set.
5. DQM “L” means the data Write/Ouput Enable and “H” means the Write inhibit/Output High-Z. Write DQM Latency is 0 CLK and Read
DQM Latency is 2 CLK.
6. Standard SDRAM parts assign this command sequence as Burst Terminate. For Bat Ram parts, the Burst Terminate command is
assigned to the Deep Power Down function.
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IS42VM16400G
Table5: Function Truth Table
Current
State
Idle
Row
Active
Read
Command
Action
Note
Mode Register Set
Set the Mode Register
14
X
Auto or Self Refresh
Start Auto or Self
Refresh
5
BA
X
Precharge
No Operation
H
BA
R
Row
Add.
Add
B kA
Bank
Activate
i
Activate the Specified
Bank and Row
L
L
BA
Col Add./ A10
Write/WriteAP
ILLEGAL
4
H
L
H
BA
Col Add./ A10
Read/ReadAP
ILLEGAL
4
L
H
H
H
X
X
No Operation
No Operation
3
H
X
X
X
X
X
Device Deselect
No Operation or Power
Down
3
L
L
L
L
Mode Register Set
ILLEGAL
13,14
L
L
L
H
X
X
Auto or Self Refresh
ILLEGAL
13
L
L
H
L
BA
X
Precharge
Precharge
7
L
L
H
H
BA
Row Add.
Bank Activate
ILLEGAL
4
L
H
L
L
BA
Col Add./A10
Write/Write AP
Start Write : Optional
AP(A10=H)
6
L
H
L
H
BA
Col Add./A10
Read/Read AP
Sta t Read : Optional
Start
AP(A10=H)
6
L
H
H
H
X
X
No Operation
No Operation
H
X
X
X
X
X
Device Deselect
No Operation
L
L
L
L
Mode Register Set
ILLEGAL
13,14
L
L
L
H
X
X
Auto or Self Refresh
ILLEGAL
13
L
L
H
L
BA
X
Precharge
Termination Burst :
Start the Precharge
L
L
H
H
BA
Row Add.
Bank Activate
ILLEGAL
L
H
L
L
BA
Col Add./A10
Write/WriteAP
Termination Burst :
Start Write(AP)
8,9
L
H
L
H
BA
Col Add./A10
Read/Read AP
Terimination Burst :
Start Read(AP)
8
L
H
H
H
X
X
No Operation
Continue the Burst
H
X
X
X
X
X
Device Deselect
Continue the Burst
/CS
/RAS
/CAS
/WE
L
L
L
L
L
L
L
H
X
L
L
H
L
L
L
H
L
H
L
Rev. A | July 2010
BA
A0-A11
OP CODE
OP CODE
OP CODE
Description
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4
12
IS42VM16400G
Table5: Function Truth Table
Current
State
Command
/CS
/RAS
/CAS
/WE
L
L
L
L
L
L
L
H
X
L
L
H
L
L
L
H
L
H
L
Write
Read
with
Auto
Precharge
Write
with
Auto
Precharge
Rev. A | July 2010
BA
A0-A11
OP CODE
Description
Action
Note
Mode Register Set
ILLEGAL
13,14
X
Auto or Self Refresh
ILLEGAL
13
BA
X
Precharge
Termination Burst :
Start the Precharge
10
H
BA
Row Add.
Bank Activate
ILLEGAL
4
L
L
BA
Col Add./A10
Write/WriteAP
Termination Burst :
Start Write(AP)
8
H
L
H
BA
Col Add./A10
Read/ReadAP
Terimination Burst :
Start READ(AP)
8,9
L
H
H
H
X
X
No Operation
Continue the Burst
H
X
X
X
X
X
Device Deselect
Continue the Burst
L
L
L
L
Mode Register Set
ILLEGAL
13,14
L
L
L
H
X
X
Auto or Self Refresh
ILLEGAL
13
L
L
H
L
BA
X
Precharge
ILLEGAL
4,12
L
L
H
H
BA
Row Add.
Bank Activate
ILLEGAL
4,12
L
H
L
L
BA
Col Add./A10
Write/WriteAP
ILLEGAL
12
L
H
L
H
BA
Col Add./A10
Read/ReadAP
ILLEGAL
12
L
H
H
H
X
X
No Operation
Continue the Burst
H
X
X
X
X
X
Device Deselect
Continue the Burst
L
L
L
L
Mode Register Set
ILLEGAL
13,14
L
L
L
H
X
X
Auto or Self Refresh
ILLEGAL
13
L
L
H
L
BA
X
Precharge
ILLEGAL
4,12
L
L
H
H
BA
Row Add.
Bank Activate
ILLEGAL
4,12
L
H
L
L
BA
Col Add./A10
Write/WriteAP
ILLEGAL
12
L
H
L
H
BA
Col Add./A10
Read/ReadAP
ILLEGAL
12
L
H
H
H
X
X
No Operation
Continue the Burst
H
X
X
X
X
X
Device Deselect
Continue the Burst
OP CODE
OP CODE
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IS42VM16400G
Table5: Function Truth Table
Current
State
P echa ging
Precharging
Row
Activating
Write
Recovering
Command
/CS
/RAS
/CAS
/WE
BA
L
L
L
L
L
L
L
H
X
L
L
H
L
L
L
H
L
H
L
A0-A11
Action
Note
Mode Register Set
ILLEGAL
13,14
X
Auto or Self Refresh
ILLEGAL
13
BA
X
Precharge
No Operation : Bank(s)
Idle after tRP
H
BA
Row Add.
Bank Activate
ILLEGAL
4,12
L
L
BA
Col Add./ A10
Write/WriteAP
ILLEGAL
4,12
H
L
H
BA
Col Add./ A10
Read/ReadAP
ILLEGAL
4,12
L
H
H
H
X
X
No Operation
No Operation : Bank(s)
Idle after tRP
H
X
X
X
X
X
Device Deselect
No Operation : Bank(s)
Idle after tRP
L
L
L
L
Mode Register Set
ILLEGAL
13,14
L
L
L
H
X
X
Auto or Self Refresh
ILLEGAL
13
L
L
H
L
BA
X
Precharge
ILLEGAL
4,12
L
L
H
H
BA
Row Add.
Bank Activate
ILLEGAL
4,11,12
L
H
L
L
BA
Col Add./A10
Write/Write AP
ILLEGAL
4,12
L
H
L
H
BA
Col Add./A10
Read/Read AP
ILLEGAL
4,12
L
H
H
H
X
X
No Operation
No Operation : ROw
Active after tRCD
H
X
X
X
X
X
Device Deselect
No Operation : ROw
Active after tRCD
L
L
L
L
Mode Register Set
ILLEGAL
13,14
L
L
L
H
X
X
Auto or Self Refresh
ILLEGAL
13
L
L
H
L
BA
X
Precharge
ILLEGAL
4,13
L
L
H
H
BA
Row Add.
Bank Activate
ILLEGAL
4,12
L
H
L
L
BA
Col Add./A10
Write/WriteAP
Start Write : Optional
AP(A10=H)
L
H
L
H
BA
Col Add./A10
Read/Read AP
Start Write : Optional
AP(A10=H)
L
H
H
H
X
X
No Operation
No Operation : Row
Active after tDPL
H
X
X
X
X
X
Device Deselect
No Operation : Row
Active after tDPL
Rev. A | July 2010
OP CODE
Description
OP CODE
OP CODE
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9
14
IS42VM16400G
Table5: Function Truth Table
Current
State
Command
/CS
/RAS
/CAS
/WE
L
L
L
L
L
L
L
H
X
L
L
H
L
L
L
H
L
H
L
Write
Recovering
with
Auto
Precharge
Refreshing
Mode
Register
Accessing
Rev. A | July 2010
BA
A0-A11
OP CODE
Description
Action
Note
Mode Register Set
ILLEGAL
13,14
X
Auto or Self Refresh
ILLEGAL
13
BA
X
Precharge
ILLEGAL
4,13
H
BA
Row Add.
Bank Activate
ILLEGAL
4,12
L
L
BA
Col Add./
Add / A10
Write/WriteAP
ILLEGAL
4 12
4,12
H
L
H
BA
Col Add./ A10
Read/ReadAP
ILLEGAL
4,9,12
L
H
H
H
X
X
No Operation
No Operation :
Precharge after tDPL
H
X
X
X
X
X
Device Deselect
No Operation :
Precharge after tDPL
L
L
L
L
Mode Register Set
ILLEGAL
13,14
L
L
L
H
X
X
Auto or Self Refresh
ILLEGAL
13
L
L
H
L
BA
X
Precharge
ILLEGAL
13
L
L
H
H
BA
Row Add.
Bank Activate
ILLEGAL
13
L
H
L
L
BA
Col Add./A10
Write/Write AP
ILLEGAL
13
L
H
L
H
BA
Col Add./A10
Read/Read AP
ILLEGAL
13
L
H
H
H
X
X
No Operation
No Operation : Idle
after
f
tRC
C
H
X
X
X
X
X
Device Deselect
No Operation : Idle
after tRC
L
L
L
L
Mode Register Set
ILLEGAL
13,14
L
L
L
H
X
X
Auto or Self Refresh
ILLEGAL
13
L
L
H
L
BA
X
Precharge
ILLEGAL
13
L
L
H
H
BA
Row Add.
Add
Bank Activate
ILLEGAL
13
L
H
L
L
BA
Col Add./A10
Write/WriteAP
ILLEGAL
13
L
H
L
H
BA
Col Add./A10
Read/Read AP
ILLEGAL
13
L
H
H
H
X
X
No Operation
No Operation : Idle
after 2 Clock Cycle
H
X
X
X
X
X
Device Deselect
No Operation : Idle
after 2 Clock Cycle
OP CODE
OP CODE
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15
IS42VM16400G
Note :
1 H:
1.
H LLogic
i High,
Hi h L:
L Logic
L i Low,
L
X:
X Don't
D 't care, BA:
BA Bank
B k Address,
Add
AP:
AP Auto
A t Precharge.
P h
2. All entries assume that CKE was active during the preceding clock cycle.
3. If both banks are idle and CKE is inactive, then in power down cycle
4. Illegal to bank in specified states. Function may be legal in the bank indicated by Bank Address,
depending on the state of that bank.
5. If both banks are idle and CKE is inactive, then Self Refresh mode.
6. Illegal if tRCD is not satisfied.
7. Illegal if tRAS is not satisfied.
8. Must satisfy burst interrupt condition.
9. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
10. Must mask preceding data which don't satisfy tDPL.
11. Illegal if tRRD is not satisfied
12. Illegal for single bank, but legal for other banks in multi-bank devices.
13. Illegal for all banks.
14. Mode Register Set and Extended Mode Register Set is same command truth table except BA.
Rev. A | July 2010
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IS42VM16400G
Table6: CKE Truth Table
Current
State
Self
Refresh
CKE
Command
/CS
/RAS
/CAS
/WE
BA
A0-A11
H
X
X
X
X
X
X
X
INVALID
2
L
H
H
X
X
X
X
X
Exit Self Refresh with Device
Deselect
3
L
H
L
H
H
H
X
X
Exit Self Refresh with No
Operation
3
L
H
L
H
H
L
X
X
ILLEGAL
3
L
H
L
H
L
X
X
X
ILLEGAL
3
L
H
L
L
X
X
X
X
ILLEGAL
3
L
L
X
X
X
X
X
X
Maintain Self Refresh
H
X
X
X
X
X
X
X
INVALID
2
L
H
H
X
X
X
X
X
L
H
H
H
X
X
Power Down Mode Exit, All
Banks Idle
3
L
X
X
X
X
X
L
X
X
X
X
X
L
X
X
L
All
Banks
Idle
Any
State
other
than
listed
above
N
Note
Current
Cycle
Power
Down
Deep
Power
Down
A i
Action
Prev
Cycle
H
L
ILLEGAL
3
L
L
X
X
X
X
X
X
Maintain Power Down Mode
H
X
X
X
X
X
X
X
INVALID
2
L
H
X
X
X
X
X
X
Deep Power Down Mode Exit
6
L
L
X
X
X
X
X
X
Maintain Deep Power Down
Mode
H
H
H
X
X
X
H
H
L
H
X
X
H
H
L
L
H
X
H
H
L
L
L
H
H
H
L
L
L
L
H
L
H
X
X
X
H
L
L
H
X
X
H
L
L
L
H
X
H
L
L
L
L
H
H
L
L
L
L
L
L
X
X
X
X
X
X
X
Power Down
H
H
X
X
X
X
X
X
Refer to Operations of the
Current State Truth Table
H
L
X
X
X
X
X
X
Begin Clock Suspend next
cycle
L
H
X
X
X
X
X
X
Exit Clock Suspend next
cycle
L
L
X
X
X
X
X
X
Maintain Clock Suspend
Rev. A | July 2010
Refer to the Idle State
section of the Current State
Truth Table
4
4
4
X
X
OP CODE
Auto Refresh
Mode Register Set
5
Refer to the Idle State
section of the Current State
Truth Table
4
4
4
X
X
Entry Self Refresh
OP CODE
Mode Register Set
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5
17
IS42VM16400G
Note :
1. H: Logic High, L: Logic Low, X: Don't care
2. For the given current state CKE must be low in the previous cycle.
3. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. When exiting power down mode,
a NOP (or Device Deselect) command is required on the first positive edge of clock after CKE goes high.
4. The address inputs depend on the command that is issued.
5. The Precharge Power Down mode, the Self Refresh mode, and the Mode Register Set can only be entered from the all banks idle state.
6. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously.
When exiting deep power down mode, a NOP (or Device Deselect) command is required on the first positive edge of clock after CKE goes
high and is maintained for a minimum 100usec.
100usec
Rev. A | July 2010
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18
IS42VM16400G
Table7: Absolute Maximum Rating
Parameter
Symbol
Ambient Temperature (Industrial)
Rating
-40 ~ 85
TA
Ambient Temperature (Commercial)
Unit
°C
0 ~ 70
TSTG
-55 ~ 150
°C
VIN, VOUT
-1.0 ~ 2.6
V
VDD, VDDQ
-1.0 ~ 2.6
V
Short Circuit Output Current
IOS
50
mA
Power Dissipation
PD
1
W
Storage Temperature
Voltage on Any Pin relative to VSS
Voltage on VDD relative to VSS
Note :
Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Table8: Capacitance (TA=25 °C, f=1MHz, VDD=1.8V)
Parameter
Input Capacitance
Pin
Symbol
Min
Max
Unit
CLK
CI1
2
4
pF
A0~A11, BA0~BA1, CKE, /CS, /RAS,
/CAS, /WE, LDQM, UDQM
CI2
2
4
pF
DQ0~DQ15
Q
Q
CIO
3
5
pF
p
p /
p Capacitance
p
Data Input/Output
Table9: DC Operating Condition (Voltage referenced to VSS=0V, TA= -40 ~ 85 °C)
Parameter
Symbol
Min
Typ
Max
Unit
VDD
1.70
1.8
1.95
V
VDDQ
1 70
1.70
18
1.8
1 95
1.95
V
1
Input High Voltage
VIH
0.8 X VDDQ
-
VDDQ+0.3
V
2
Input Low Voltage
VIL
-0.3
0
0.3
V
3
Output High Voltage
VOH
0.9 X VDDQ
-
-
V
IOH= -0.1mA
Output Low Voltage
VOL
-
-
0.2
V
IOL= +0.1mA
Input Leakage Current
ILI
-1
-
1
uA
4
Output Leakage Current
ILO
-1.5
1.5
uA
5
Power Supply Voltage
Note
Note :
1. VDDQ must not exceed the level of VDD
2. VIH(max) = VDDQ+1.5V AC. The overshoot voltage duration is ≤ 3ns.
3. VIL(min) = -1.0V AC. The overshoot voltage duration is ≤ 3ns.
4. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs.
5. DOUT is disabled, 0V ≤ VOUT ≤ VDDQ.
Rev. A | July 2010
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IS42VM16400G
Table10: AC Operating Condition (TA= -40 ~ 85 °C, VDD = 1.70V~1.95V, VSS=0V)
P
Parameter
t
S
Symbol
b l
T
Typ
U it
Unit
VIH / VIL
0.9 X VDDQ / 0.2
V
Input Timing Measurement Reference Level Voltage
VTRIP
0.5 x VDDQ
V
Input Rise / Fall Time
tR / tF
1/1
ns
VOUTREF
0.5 x VDDQ
V
CL
30
pF
AC Input High/Low Level Voltage
Output Timing Measurement Reference Level Voltage
Output Load Capacitance for Access Time Measurement
VTT=0.5 x VDDQ
VDDQ
500Ω
Output
50Ω
Output
500Ω
30pF
30pF
DC Output Load Circuit
Rev. A | July 2010
Z0=50Ω
Z0
50Ω
AC Output Load Circuit
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IS42VM16400G
Table11: DC Characteristic (DC operating conditions unless otherwise noted)
P
Parameter
t
Speed
S
Sym
T t Condition
Test
C diti
Operating Current
ICC1
Burst Length=1, One Bank Active,
tRC ≥ tRC(min) IOL = 0 mA
Precharge Standby Current
in Power Down Mode
ICC2P
CKE ≤ VIL(max), tCK = 10ns
0.3
ICC2PS
CKE & CLK ≤ VIL(max), tCK = ∞
0.3
ICC2N
CKE ≥ VIH(min), /CS ≥ VIH(min), tCK = 10ns
Input signals are changed one time during 2 clks
clks.
8
ICC2NS
CKE ≥ VIH(min), CLK ≤ VIL(max), tCK = ∞
Input signals are stable.
1
ICC3P
CKE ≤ VIL(max), tCK = 10ns
5
ICC3PS
CKE & CLK ≤ VIL(max), tCK = ∞
1
ICC3N
CKE ≥ VIH(min), /CS ≥ VIH(min), tCK = 10ns
Input signals are changed one time during 2 clks.
15
ICC3NS
CKE ≥ VIH(min), CLK ≤ VIL(max), tCK = ∞
Input signals are stable.
6
Precharge Standby Current
in Non Power Down Mode
Active Standby Current
in Power Down Mode
Active Standby Current
in Non Power Down Mode
-75
-10
50
45
U it
Unit
N t
Note
mA
1
mA
mA
mA
mA
Burst Mode Operating Current
ICC4
tCK>tCK(min), IOL = 0 mA, Page Burst
All Banks Activated, tCCD = 1 clk
55
50
mA
1
Auto Refresh Current (4K Cycle)
ICC5
tRC ≥ tRFC(min), All Banks Active
75
70
mA
2
PASR
4 banks
Self
Refresh
Current
2 Bank
1 Bank
TCSR
85°C
350
45°C
180
85°C
ICC6
CKE ≤ 0.2V
310
45°C
160
85°C
290
45°C
150
Deep Power Down Mode Current
ICC7
30
uA
uA
Note :
1. Measured with outputs open.
2. Refresh period is 64ms.
Rev. A | July 2010
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IS42VM16400G
Table12: AC Characteristic (AC operation conditions unless otherwise noted)
Parameter
CLK Cycle Time
Access time from CLK (pos. edge)
Sym
-75
75
Min
-10
10
Max
Min
CL = 3
tCK3
7.5
CL = 2
tCK2
10
CL = 3
tAC3
6
8
CL = 2
tAC2
8
8
1000
10
Max
10
Unit
1000
Note
1
2
CLK High-Level Width
tCH
2.5
2.5
3
CLK Low-Level Width
tCL
2.5
2.5
3
CKE Setup Time
tCKS
2.0
2.0
CKE Hold Time
tCKH
1.0
1.0
/CS, /RAS, /CAS, /WE, DQM Setup Time
tCMS
2.0
2.0
/CS, /RAS, /CAS, /WE, DQM Hold Time
tCMH
1.0
1.0
Address Setup Time
tAS
2.0
2.0
Address Hold Time
tAH
1.0
1.0
Data-In Setup Time
tDS
2.0
2.0
Data-In
Data
In Hold Time
tDH
10
1.0
10
1.0
Data-Out High-Impedance Time from
CLK (pos.edge)
ns
CL = 3
tHZ3
6
8
CL = 2
tHZ2
8
8
4
Data-Out Low-Impedance Time
tLZ
1.0
1.0
Data-Out Hold Time (load)
tOH
2.5
2.5
Data-Out Hold Time (no load)
tOHN
1.8
1.8
ACTIVE to PRECHARGE command
tRAS
45
PRECHARGE command period
tRP
22.5
24
ACTIVE bank
b k a to ACTIVE bank
b k a command
d
tRC
67.5
64
ACTIVE bank a to ACTIVE bank b command
tRRD
15
20
ACTIVE to READ or WRITE delay
tRCD
22.5
30
READ/WRITE command to READ/WRITE command
tCCD
1
1
WRITE command to input data delay
tDWD
0
0
Data-in to PRECHARGE command
tDPL
15
20
Data-in to ACTIVE command
tDAL
37.5
40
DQM to data high-impedance during READs
tDQZ
2
2
6
DQM to data mask during WRITEs
tDQM
0
0
6
LOAD MODE REGISTER command to ACTIVE or
REFRESH command
tMRD
2
2
100K
40
100K
5
CLK
ns
6
6
7
7
8
CLK
CL = 3
tROH3
3
3
CL = 2
tROH2
2
2
Last data-in to burst STOP command
tBDL
1
1
6
Last data-in to new READ/WRITE command
tCDL
1
1
6
Data-out to high-impedance from
PRECHARGE command
CKE to clock disable or power-down entry mode
tCKED
1
1
CKE to clock enable or power-down exit setup mode
tPED
1
1
Refresh period (4,096 rows)
tREF
64
tRFC
67.5
70
Exit SELF REFRESH to ACTIVE command
tXSR
67.5
70
tT
0.5
Rev. A | July 2010
1.2
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CLK
64
AUTO REFRESH period
Transition time
6
0.5
9
9
ms
5
ns
5
1.2
22
IS42VM16400G
Note :
1. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the
clock pin) during access or precharge states (READ, WRITE, including tDPL, and PRECHARGE commands). CKE may be used to
reduce the data rate.
2. tAC at CL = 3 with no load is 5.5ns and is guaranteed by design. Access time to be measured with input signals of 1V/ns edge
rate, from 0.8V to 0.2V. If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter.
3. AC characteristics assume tT = 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter.
4. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid
data element will meet tOH before going High-Z.
5. Parameter guaranteed by design.
A. Target values listed with alternative values in parentheses.
B tRFC mustt be
B.
b less
l
th or equall to
than
t tRC+1CLK
tRC 1CLK
tXSR must be less than or equal to tRC+1CLK
6. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter.
7. Timing actually specified by tDPL plus tRP; clock(s) specified as a reference only at minimum cycle rate
8. JEDEC and PC100 specify three clocks.
9. Timing actually specified by tCKs; clock(s) specified as a reference only at minimum cycle rate.
10. A new command can be given tRC after self refresh exit.
Rev. A | July 2010
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23
IS42VM16400G
Special Operation for Low Power Consumption
Temperature
e pe atu e Co
Compensated
pe sated Se
Self Refresh
e es
Temperature Compensated Self Refresh allows the controller to program the Refresh interval during SELF REFRESH mode, according to
the case temperature of the Low Power SDRAM device. This allows great power savings during SELF REFRESH during most operating
temperature ranges. Only during extreme temperatures would the controller have to select a TCSR level that will guarantee data during
SELF REFRESH.
Every cell in the DRAM requires refreshing due to the capacitor losing its charge over time. The refresh rate is dependent on
temperature. At higher temperatures a capacitor loses charge quicker than at lower temperatures, requiring the cells to be refreshed
more often. Historically, during Self Refresh, the refresh rate has been set to accommodate the worst case, or highest temperature
range expected.
Thus, during ambient temperatures, the power consumed during refresh was unnecessarily high, because the refresh rate was set to
accommodate the higher temperatures.
This temperature compensated refresh rate will save power when the DRAM is operating at normal temperatures.
Partial Array Self Refresh
For further power savings during SELF REFRESH, the PASR feature allows the controller to select the amount of memory that will be
refreshed during SELF REFRESH. The refresh options are All Banks;all four banks, Two Banks;bank a and b, One Bank;bank a, Half of
One Bank;1/2 of bank a, Quarter of One Bank;1/4 of bank a. WRITE and READ commands can still occur during standard operation, but
only the selected banks will be refreshed during SELF REFRESH. Data in banks that are disabled will be lost.
Deep Power Down
Deep Power Down is an operating mode to achieve maximum power reduction by eliminating the power of the whole memory array of
the devices. Data will not be retained once the device enters Deep Power Down Mode.
This mode is entered by having all banks idle then /CS and /WE held low with /RAS and /CAS held high at the rising edge of the clock,
while CKE is low. This mode is exited by asserting CKE high.
Rev. A | July 2010
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24
IS42VM16400G
Figure7: Deep Power Down Mode Entry
CLK
CKE
/CS
//RAS
/CAS
/WE
tRP
DON’T CARE
Deep Power Down Entry
Precharge if needed
Figure8: Deep Power Down Mode Exit
CLK
CKE
/CS
/RAS
/CAS
/WE
100 µ s
Deep Power Down Exit
tRP
tRFC
Auto Refresh
All Banks Precharge
Mode Register Set
Auto Refresh
New Command
Extended Mode Register Set
DON’T CARE
Rev. A | July 2010
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25
Package O
Outline
10/17/22007
IS42VM16400G
Rev. A | July 2010
www.issi.com - [email protected]
26
IS42VM16400G
Ordering Information – VDD = 1.8V
Industrial Range: (-40oC to +85oC)
Configuration
Frequency
(MHz)
Speed
(ns)
4Mx16
133
7.5
Rev. A | July 2010
Order Part No.
Package
IS42VM16400G-75BLI
54-ball BGA, Lead-free
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27