KERSEMI SIHFRC20TR-E3A

IRFRC20, IRFUC20, SiHFRC20, SiHFUC20
Power MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
•
•
•
•
•
•
•
•
600
RDS(on) (Ω)
VGS = 10 V
4.4
Qg (Max.) (nC)
18
Qgs (nC)
3.0
Qgd (nC)
8.9
Configuration
Single
D
DPAK
(TO-252)
IPAK
(TO-251)
Dynamic dV/dt Rating
Repetitive Avalanche Rated
Surface Mount (IRFRC20/SiHFRC20)
Straight Lead (IRFUC20/SiHFUC20)
Available in Tape and Reel
Fast Switching
Ease of Paralleling
Lead (Pb)-free Available
Available
RoHS*
COMPLIANT
DESCRIPTION
Third generation Power MOSFETs from Vishay provide the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and
cost-effectiveness.
The D PAK is designed for surface mounting using vapor
phase, infrared, or wave soldering techniques. The straight
lead version (IRFUC/SiHFUC series) is for through-hole
mounting applications. Power dissipation levels up to 1.5 W
are possible in typical surcace mount applications.
G
S
N-Channel MOSFET
ORDERING INFORMATION
Package
Lead (Pb)-free
SnPb
DPAK (TO-252)
IRFRC20PbF
SiHFRC20-E3
IRFRC20
SiHFRC20
DPAK (TO-252)
IRFRC20TRLPbFa
SiHFRC20TL-E3a
IRFRC20TRLa
SiHFRC20TLa
DPAK (TO-252)
IRFRC20TRPbFa
SiHFRC20T-E3a
IRFRC20TRa
SiHFRC20Ta
DPAK (TO-252)
IRFRC20TRRPbFa
SiHFRC20TR-E3a
IRFRC20TRRa
SiHFRC20TRa
IPAK (TO-251)
IRFUC20PbF
SiHFUC20-E3
IRFUC20
SiHFUC20
Note
a. See device orientation.
ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted
PARAMETER
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current
Pulsed Drain Currenta
Linear Derating Factor
Linear Derating Factor (PCB Mount)e
Single Pulse Avalanche Energyb
Repetitive Avalanche Currenta
Repetitive Avalanche Energya
Maximum Power Dissipation
Maximum Power Dissipation (PCB Mount)e
Peak Diode Recovery dV/dtc
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
SYMBOL
VDS
VGS
VGS at 10 V
TC = 25 °C
TC = 100 °C
ID
IDM
EAS
IAR
EAR
TC = 25 °C
TA = 25 °C
PD
dV/dt
TJ, Tstg
for 10 s
LIMIT
600
± 20
2.0
1.3
8.0
0.33
0.020
450
2.0
4.2
42
2.5
3.0
- 55 to + 150
260d
UNIT
V
A
W/°C
mJ
A
mJ
W
V/ns
°C
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IRFRC20, IRFUC20, SiHFRC20, SiHFUC20
THERMAL RESISTANCE RATINGS
SYMBOL
MIN.
TYP.
MAX.
Maximum Junction-to-Ambient
PARAMETER
RthJA
-
-
110
Maximum Junction-to-Ambient
(PCB Mount)a
RthJA
-
-
50
Maximum Junction-to-Case (Drain)
RthJC
-
-
3.0
UNIT
°C/W
Note
a. When mounted on 1" square PCB (FR-4 or G-10 material).
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDS
VGS = 0 V, ID = 250 µA
600
-
-
V
ΔVDS/TJ
Reference to 25 °C, ID = 1 mA
-
0.88
-
V/°C
VGS(th)
VDS = VGS, ID = 250 µA
2.0
-
4.0
V
nA
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage
Gate-Source Leakage
Zero Gate Voltage Drain Current
Drain-Source On-State Resistance
Forward Transconductance
IGSS
IDSS
RDS(on)
gfs
VGS = ± 20 V
-
-
± 100
VDS = 600 V, VGS = 0 V
-
-
100
VDS = 480 V, VGS = 0 V, TJ = 125 °C
-
-
500
-
-
4.4
Ω
1.4
-
-
S
-
350
-
-
48
-
-
8.6
-
ID = 1.2 Ab
VGS = 10 V
VDS = 50 V, ID = 1.2 A
µA
Dynamic
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Total Gate Charge
Qg
Gate-Source Charge
Qgs
VGS = 0 V,
VDS = - 25 V,
f = 1.0 MHz, see fig. 5
VGS = 10 V
ID = 2.0 A, VDS = 360 V,
see fig. 6 and 13b
-
-
18
-
-
3.0
Gate-Drain Charge
Qgd
-
-
8.9
Turn-On Delay Time
td(on)
-
10
-
-
23
-
-
30
-
-
25
-
-
4.5
-
-
7.5
-
-
-
2.0
-
-
8.0
Rise Time
Turn-Off Delay Time
Fall Time
Internal Drain Inductance
Internal Source Inductance
tr
td(off)
VDD = 300 V, ID = 2.0 A,
RG = 18 Ω, RD = 135 Ω, see fig. 10b
tf
LD
LS
Between lead,
6 mm (0.25") from
package and center of
die contact
pF
nC
ns
D
nH
G
S
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulsed Diode Forward Currenta
ISM
Body Diode Voltage
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Forward Turn-On Time
ton
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MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
S
TJ = 25 °C, IS = 2.0 A, VGS = 0 Vb
TJ = 25 °C, IF = 2.0 A, dI/dt = 100 A/µsb
-
-
1.6
V
-
290
580
ns
-
0.67
1.3
µC
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
IRFRC20, IRFUC20, SiHFRC20, SiHFUC20
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Fig. 1 - Typical Output Characteristics, TC = 25 °C
Fig. 2 - Typical Output Characteristics, TC = 150 °C
Fig. 3 - Typical Transfer Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
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IRFRC20, IRFUC20, SiHFRC20, SiHFUC20
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
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Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 8 - Maximum Safe Operating Area
IRFRC20, IRFUC20, SiHFRC20, SiHFUC20
RD
VDS
VGS
D.U.T.
RG
+
- VDD
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
Fig. 10a - Switching Time Test Circuit
VDS
90 %
10 %
VGS
td(on)
Fig. 9 - Maximum Drain Current vs. Case Temperature
tr
td(off) tf
Fig. 10b - Switching Time Waveforms
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
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IRFRC20, IRFUC20, SiHFRC20, SiHFUC20
L
Vary tp to obtain
required IAS
VDS
VDS
tp
VDD
D.U.T
RG
+
-
I AS
V DD
VDS
10 V
0.01 Ω
tp
Fig. 12a - Unclamped Inductive Test Circuit
IAS
Fig. 12b - Unclamped Inductive Waveforms
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Current regulator
Same type as D.U.T.
50 kΩ
QG
VGS
12 V
0.2 µF
0.3 µF
QGS
QGD
+
D.U.T.
VG
-
VDS
VGS
3 mA
Charge
IG
ID
Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform
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Fig. 13b - Gate Charge Test Circuit
IRFRC20, IRFUC20, SiHFRC20, SiHFUC20
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
•
•
•
•
RG
dV/dt controlled by R G
Driver same type as D.U.T.
ISD controlled by duty factor "D"
D.U.T. - device under test
Driver gate drive
P.W.
+
Period
D=
+
-
VDD
P.W.
Period
VGS = 10 V*
D.U.T. ISD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
VDD
Body diode forward drop
Inductor current
Ripple ≤ 5 %
ISD
* VGS = 5 V for logic level devices
Fig. 14 - For N-Channel
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