MICREL SY100E222L_11

Precision Edge®
3.3V, 1.5GHz ÷1/÷2 DIFFERENTIAL
SY100E222L
®
LVECL/LVPECL PROGRAMMABLE CLOCK Precision Edge
SY100E222L
GENERATOR AND 1:15 FANOUT BUFFER
Micrel, Inc.
FEATURES
■ Four programmable output banks and 15 total
LVPECL-compatible differential outputs
■ Pin-compatible, plug-in replacement to
MC100LVE222FA
■ fMAX clock = 1.5GHz
■ 50ps output-to-output skew
■ Four output banks with independent ÷1, ÷2
frequency control
■ 100k compatible I/O
■ Power supply 3.3V ±10%
■ –40°C to +85°C temperature range
■ Available in 52-pin LQFP package
Precision Edge®
DESCRIPTION
The SY100E222L is a low-skew, low-jitter device capable
of receiving a high-speed LVECL/LVPECL input in either a
single-ended or differential configuration. For single-ended
configurations, a VBB output reference is supplied by the
SY100E222L. A 2:1 input multiplexer selects from two
differential input pairs by means of the CLK_SEL input select.
The internal programmable divider for each of the four
banks generates a ÷1 or ÷2 frequency of the selected input.
The ÷1/÷2 divider outputs can be asynchronously
synchronized with the master reset (MR) input so that the
outputs will start out in a known state.
The 15 total outputs are partitioned into four independently
selected output banks in a 2/3/4/6 fanout configuration. Each
of the four banks can independently select the ÷1 or ÷2
output frequency by means of the four separate frequency
select pins (FSELA-FSELD) inputs.
The SY100E222L is pin-for-pin compatible with the
MC100LVE222FA device.
The SY100E222L is part of a Micrel’s Precision Edge™
product family. For other integrated clock divider plus fanout
buffer options, consider Micrel’s SY89200 family.
All support documentation can be found on Micrel’s web
site at www.micrel.com.
APPLICATIONS
■ SONET/SDH channel applications
■ Fibre Channel multi-channel applications
■ Gigabit Ethernet multi-channel applications
FUNCTIONAL BLOCK DIAGRAM
1:2 FOB
QA0
CLK_SEL
/QA0
CLK0
/CLK0
VBB
CLK1
÷1
2:1
MUX
QA1
2:1
MUX
CLK
÷2
/QA1
1:3 FOB
/CLK1
QB0
MR
FSELA
/QB0
QB1
/QB1
CROSS REFERENCE TABLE
QB2
2:1
MUX
/QB2
1:4 FOB
QC0
Micrel Part Number
ON Semiconductor
SY100E222LTI
MC100LVE222FA
SY100E222LTI TR
MC100LVE222FAR2
/QC0
FSELB
QC1
/QC1
QC2
2:1
MUX
/QC2
QC3
/QC3
1:6 FOB
FSELC
QD0
/QD0
QD1
2:1
MUX
/QD1
QD2
/QD2
FSELD
QD3
/QD3
QD4
/QD4
QD5
/QD5
Precision Edge is a registered trademark of Micrel, Inc.
M9999-021511
[email protected] or (408) 955-1690
Rev.: C
1
Amendment: /0
Issue Date: February 2011
Precision Edge®
SY100E222L
Micrel, Inc.
PACKAGE/ORDERING INFORMATION
Ordering Information(1)
Part Number
Package
Type
Operating
Range
Package
Marking
Lead
Finish
SY100E222LTI
LQFP-52
Industrial
SY100E222LTI
Sn-Pb
SY100E222LTITR(2)
LQFP-52
Industrial
SY100E222LTI
Sn-Pb
SY100E222LTY(3)
LQFP-52
Industrial
SY100E222LTY with
Matte-Sn
Pb-Free bar-line indicator
SY100E222LTYTR(2, 3)
LQFP-52
Industrial
SY100E222LTY with
Matte-Sn
Pb-Free bar-line indicator
SY100E222LTYTX(2, 4)
LQFP-52
Industrial
SY100E222LTY with
Matte-Sn
Pb-Free bar-line indicator
Notes:
QB2
/QB2
VCCO
/QB1
QB1
/QB0
QB0
VCCO
/QA1
QA1
/QA0
QA0
VCCO
Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only.
Tape and Reel.
Pb-Free package is recommended for new designs.
EIA specification orientation.
VCCO
NC
NC
VCCO
VCCO
QD1
/QD0
QD0
30
11
29
12
28
13
27
14 15 16 17 18 19 20 21 22 23 24 25 26
/QD1
10
VBB
FSELC
FSELD
VEE
QD2
/QC1
QC2
/QC2
QC3
/QC3
/QD2
35
34
33
32
31
QD3
5
6
7
8
9
/QD3
CLK0
/CLK0
CLK_SEL
CLK1
/CLK1
QD4
52 51 50 49 48 47 46 45 44 43 42 41 40
39
38
37
36
/QD4
1
2
3
4
QD5
VCC
MR
FSELA
FSELB
/QD5
1.
2.
3.
4.
52-Pin LQFP (LQFP-52)
M9999-021511
[email protected] or (408) 955-1690
2
VCCO
QC0
/QC0
QC1
Precision Edge®
SY100E222L
Micrel, Inc.
PIN DESCRIPTION
Pin Number
Pin Name
2
MR
100k ECL compatible: Master reset function resets all outputs to a differential LOW when
MR pin goes HIGH.
5, 6,
8, 9
CLK0, /CLK0,
CLK1, /CLK1
Differential inputs: These input pairs are the differential signal inputs to the device. Inputs
accept 100k LVPECL/LVECL levels.
7
CLK_SEL
3
FSELA
100k ECL compatible bank A output select. LOW: QA0-QA1 = ÷1, HIGH: QA0-QA1 = ÷2.
4
FSELB
100k ECL compatible bank B output select. LOW: QB0-QB2 = ÷1, HIGH: QB0-QB2 = ÷2.
11
FSELC
100k ECL compatible bank C output select. LOW: QC0-QC3 = ÷1, HIGH: QC0-QC3 = ÷2.
12
FSELD
100k ECL compatible bank D output select. LOW: QD0-QD5 = ÷1, HIGH: QD0-QD5 = ÷2.
51, 49,
50, 48
QA0 – QA1,
/QA0 – /QA1
Bank A 100k differential output pairs controlled by FSELA.
FSELA: LOW, QA = ÷1, HIGH, QA = ÷2.
46, 44, 42,
45, 43, 41
QB0 – QB2,
/QB0 – /QB2
Bank B 100k differential output pairs controlled by FSELB.
FSELB: LOW, QB = ÷1, HIGH, QB = ÷2.
38, 36, 34, 32,
37, 35, 33, 31
QC0 – QC3,
/QC0 – /QC3
Bank C 100k differential output pairs controlled by FSELC.
FSELC: LOW, QC = ÷1, HIGH, QC = ÷2.
26, 24, 22, 20,
18, 16, 25, 23,
21, 19, 17, 15
QD0 – QD5,
/QD0 – /QD5
Bank D 100k differential output pairs controlled by FSELD.
FSELD: LOW, QD = ÷1, HIGH, QD = ÷2.
1
VCC
14, 27, 30, 39,
40, 47, 52
VCCO
13
VEE
Negative power supply. For LVPECL systems, VEE is GND.
10
VBB
Reference voltage.
28, 29
NC
No connect: Not internally connected (unused pins).
M9999-021511
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Pin Function
100k ECL compatible input select. LOW = CLK0, HIGH= CLK1.
Positive power supply: Bypass with 0.1µF0.01µF low ESR capacitors.
Positive power supply for output buffers. Bypass with 0.1µF0.01µF low ESR capacitors.
3
Precision Edge®
SY100E222L
Micrel, Inc.
Absolute Maximum Ratings(1)
Supply Voltage (VCC) ................................. –0.5V to + 4.0V
Input Voltage (VIN) ......................................... –0.5V to VCC
Termination Current(3)
Source or sink current on VBB (IBB) ..................... ±0.5mA
DC Output Current
LVPECL Outputs .................................................. –50mA
Lead Temperature (soldering, 10 sec.) ................... +265°C
Storage Temperature (TS) ...................... –65°C to +150°C
DC ELECTRICAL CHARACTERISTICS(4)
Symbol
Parameter
Condition
Min
ICC
Power Supply Current
Max. VCC all inputs and outputs OPEN
Typ
Max
Units
122
139
mA
LVPECL DC ELECTRICAL CHARACTERISTICS(4, 5)
VCC = +3.3V ±0.3V; VEE = 0V; TA = –40°C to +85°C, typicals are TA = 25°C.
Symbol
Parameter
Condition
Min
Typ
Max
Units
VOH
Output High Voltage
RL = 50Ω to VCC–2V
2215
2345
2420
mV
VOL
Output Low Voltage
RL = 50Ω to VCC–2V
1470
1595
1680
mV
VIH
Input High Voltage
2135
2420
mV
VIL
Input Low Voltage
1490
1825
mV
VIHCMR
Input High Voltage Common
Mode Range (Differential)
(CLK, /CLK) VPP < 500mV
VPP ≥ 500mV
1.3
1.6
2.9
2.9
V
V
1.92
2.04
V
150
µA
VBB
Output Reference Voltage
IIH
Input HIGH Current
IIL
Input LOW Current
(CLK, CLK_SEL, FSEL, MR)
(/CLK)
Note 6
0.5
–300
µA
µA
Notes:
1. Permanent device damage may occur if the ratings in “Absolute Maximum Ratings” section are exceeded. This is a stress rating only and functional
operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings
conditions for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Due to the limited drive capability use for input of the same package only.
4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
5. Input and output parameters are for VCC = 3.3V. They vary 1:1 with VCC.
6. VIHCMR is defined as the range within which the VIH level may vary with the device still meeting the propagation delay specification. The VIL level
must be such that the peak-to-peak voltage is less than 1.0V and then greater than or equal to VPP(min).
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Precision Edge®
SY100E222L
Micrel, Inc.
LVECL DC ELECTRICAL CHARACTERISTICS(5)
VCC = 0V; VEE = –3.3V ±0.3V; TA = –40°C to +85°C, typicals are TA = 25°C.
Symbol
Parameter
Condition
VOH
Output High Voltage
VOL
Output Low Voltage
VIH
Input High Voltage
VIL
Input Low Voltage
VIIHCMR
Input High Voltage Common
Mode Range (Differential)
(CLK, /CLK) VPP < 500mV
VPP ≥ 500mV
VBB
Output Reference Voltage
IIH
Input HIGH Current
IIL
Input LOW Current
(CLK, CLK_SEL, FSEL, MR)
(/CLK)
Min
Typ
Max
Units
RL = 50Ω to VCC–2V
–1085
–955
–880
mV
RL = 50Ω to VCC–2V
–1830
–1705
–1620
mV
–1165
–880
mV
–1810
–1475
mV
–2.0
–1.7
–0.4
–0.4
V
V
–1.38
–1.26
V
150
µA
Note 6
0.5
–300
µA
µA
AC ELECTRICAL CHARACTERISTICS(7)
VCC = +3.0 to +3.6V and VEE = 0V or VCC = 0V and VEE = –3.0 to –3.6V; TA = –40°C to +85°C, typicals are TA = 25°C.
Symbol
Parameter
Condition
fMAX
Maximum Operating Frequency
tPD
Propagation Delay
IN (Differential), Note 8
IN (Single-ended), Note 9
MR
tSKEW
Within-Device Skew
Note 10
Min
Typ
1.2
>1.5
1040
1090
1000
1210
1335
1200
Part-to-Part Skew (Differential)
Max
Units
GHz
1420
1570
1520
ps
ps
ps
50
ps
300
ps
tJITTER
Random Clock Jitter
<1
psRMS
VPP
Differential Input Swing
Note 11
400
1000
mV
tr, tf
Output Rise/Fall Time (Q, /Q)
(20% to 80%)
200
600
ps
Notes:
5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
6. VIHCMR is defined as the range within which the VIH level may vary with the device still meeting the propagation delay specification. The VIL level
must be such that the peak-to-peak voltage is less than 1.0V and then greater than or equal to VPP(min).
7. High-frequency AC parameters are guaranteed by design and characterization.
8. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the
differential output signals.
9. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal.
10. The within-device skew is defined as the worst-case difference between any two similar delay paths within a single device.
11. VPP(min) is defined as the minimum input differential voltage, which will cause no increase in the propagation delay. The VPP(min) is AC limited for
the SY100E222L as a differential input as low as 50 mV will still produce full ECL levels at the output.
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[email protected] or (408) 955-1690
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Precision Edge®
SY100E222L
Micrel, Inc.
SINGLE-ENDED AND DIFFERENTIAL SWINGS
VDIFF_IN,
VDIFF_OUT 700mV (Typ.)
VIN,
VOUT 350mV (Typ.)
Figure 1a. Single-Ended Voltage Swing
Figure 1b. Differential Voltage Swing
TIMING DIAGRAM
CLK
/CLK
MR
Q
÷1
/Q
Q
÷2
/Q
TRUTH TABLE
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MR
CLK_SEL
FSEL
Q
0
0
0
CLK0 ÷ 1
0
0
1
CLK0 ÷ 2
0
1
0
CLK1 ÷ 1
0
1
1
CLK1 ÷ 2
1
X
X
0
6
Precision Edge®
SY100E222L
Micrel, Inc.
52-PIN LQFP (LQFP-52)
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL
+ 1 (408) 944-0800
FAX
+ 1 (408) 474-1000
WEB
http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use.
Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can
reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into
the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s
use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify
Micrel for any damages resulting from such use or sale.
© 2006 Micrel, Incorporated.
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7