MICRON MT46H16M16LFBF-6ITH

256Mb: x16, x32 Mobile DDR SDRAM
Features
Mobile DDR SDRAM
MT46H16M16LF – 4 Meg x 16 x 4 banks
MT46H8M32LF/LG – 2 Meg x 32 x 4 banks
For the latest data sheet, refer to Micron’s Web site: www.micron.com
Features
Table 2:
• VDD/VDDQ = 1.70–1.95V
• Bidirectional data strobe per byte of data (DQS)
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; centeraligned with data for WRITEs
• Four internal banks for concurrent operation
• Data masks (DM) for masking write data—one mask
per byte
• Programmable burst lengths: 2, 4, or 8
• Concurrent auto precharge option supported
• Auto refresh and self refresh modes
• 1.8V LVCMOS compatible inputs
• On-chip temperature sensor to control self refresh
rate
• Partial-array self refresh (PASR)
• Deep power-down (DPD)
• Selectable output drive (DS)
• Clock stop capability
• 64ms refresh period
Table 1:
DQ
Bus
Width
x16
x32
Architecture
Reduced
Page-Size
Option
Number of banks
Bank address balls
Row address balls
Column address balls
Row address balls
Column address balls
4
BA0, BA1
A0–A12
A0–A8
A0–A11
A0–A8
4
BA0, BA1
–
–
A0–A12
A0–A7
PDF: 09005aef82091978 / Source: 09005aef8209195b
MT46H16M16LF__1.fm - Rev. H 6/08 EN
Clock Rate (MHz)
Access Time
Speed
Grade
CL = 2
CL = 3
CL = 2
CL = 3
-6
-75
83.3
83.3
166
133
6.5ns
6.5ns
5.0ns
6.0ns
Options
• VDD/VDDQ
– 1.8V/1.8V
• Configuration
– 16 Meg x 16 (4 Meg x 16 x 4 banks)
– 8 Meg x 32 (2 Meg x 32 x 4 banks)
• Row size option
– JEDEC-standard option
– Reduced page-size option2
• Plastic “green” packages
– 60-ball VFBGA 8mm x 9mm1
– 90-ball VFBGA 8mm x 13mm2
• Timing – cycle time
– 6ns at CL = 3
– 7.5ns at CL = 3
• Power
– Standard
– Low IDD2P/IDD6
• Operating temperature range
– Commercial (0°C to +70°C)
– Industrial (–40°C to +85°C)
• Design revision
Configuration Addressing
JEDECStandard
Option
Key Timing Parameters
Marking
H
16M16
8M32
LF
LG
BF
B5
-6
-75
None
L
None
IT
:A
Notes: 1. Only available for x16 configuration.
2. Only available for x32 configuration.
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
256Mb: x16, x32 Mobile DDR SDRAM
Table of Contents
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
FBGA Part Marking Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Functional Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Ballouts and Ball Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Standard Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Operating Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Extended Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Temperature-Compensated Self Refresh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Partial-Array Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Output Driver Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Stopping the External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
DESELECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
NO OPERATION (NOP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
LOAD MODE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
ACTIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
BURST TERMINATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
AUTO REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Deep Power-Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Bank/Row Activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
READs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Truncated READs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
WRITEs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Deep Power-Down (DPD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
PDF: 09005aef82091978 / Source: 09005aef8209195b
MT46H16M16LFTOC.fm - Rev. H 6/08 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
256Mb: x16, x32 Mobile DDR SDRAM
List of Figures
List of Figures
Figure 1:
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Figure 6:
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Figure 25:
Figure 26:
Figure 27:
Figure 28:
Figure 29:
Figure 30:
Figure 31:
Figure 32:
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Figure 40:
Figure 41:
Figure 42:
Figure 43:
Figure 44:
Figure 45:
Figure 46:
Figure 47:
Figure 48:
Figure 49:
Figure 50:
Figure 51:
256Mb Mobile DDR Part Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Functional Block Diagram (16 Meg x 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Functional Block Diagram (8 Meg x 32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
60-Ball VFBGA Ball Assignments – 8mm x 9mm (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
90-Ball VFBGA Ball Assignments – 8mm x 13mm (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Standard Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Extended Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Clock Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Mobile DRAM State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Activating a Specific Row in a Specific Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Example: Meeting tRCD (tRRD) MIN When 2 < tRCD (tRRD) MIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
READ Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Consecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Nonconsecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Random READ Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Terminating a READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
READ-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
READ-to-PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Consecutive WRITE-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Nonconsecutive WRITE-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Random WRITE Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
WRITE-to-READ – Uninterrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
WRITE-to-READ – Interrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
WRITE-to-READ – Odd Number of Data, Interrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
WRITE-to-PRECHARGE – Uninterrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
WRITE-to-PRECHARGE – Interrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
WRITE-to-PRECHARGE – Odd Number of Data, Interrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Power-Down Command (in Active or Precharge Modes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Deep Power-Down Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Deep Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Typical Self Refresh Current vs. Temperature (x16, x32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Data Output Timing – tDQSQ, tQH, and Data Valid Window (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Data Output Timing – tDQSQ, tQH, and Data Valid Window (x32) . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Data Output Timing – tAC and tDQSCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Data Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Initialize and Load Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Power-Down Mode (Active or Precharge) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Auto Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Self Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Bank Read – Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Bank Read – with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Bank Write – Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Bank Write – with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Write – DM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
60-Ball VFBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
90-Ball VFBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
PDF: 09005aef82091978 / Source: 09005aef8209195b
MT46H16M16LFLOF.fm - Rev. H 6/08 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
256Mb: x16, x32 Mobile DDR SDRAM
List of Tables
List of Tables
Table 1:
Table 2:
Table 3:
Table 4:
Table 5:
Table 6:
Table 7:
Table 8:
Table 9:
Table 10:
Table 11:
Table 12:
Table 13:
Table 14:
Table 15:
Table 16:
Table 17:
Table 18:
Configuration Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Key Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
60-Ball VFBGA Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
90-Ball VFBGA Ball Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Burst Definition Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Partial-Array Self Refresh Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Truth Table – Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Truth Table – DM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Truth Table – CKE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Truth Table – Current State Bank n – Command to Bank n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Truth Table – Current State Bank n – Command to Bank m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Electrical Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Capacitance (x16, x32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
IDD Specifications and Conditions (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
IDD Specifications and Conditions (x32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
IDD6 Specifications and Conditions (x16, x32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Electrical Characteristics and Recommended AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . .61
PDF: 09005aef82091978 / Source: 09005aef8209195b
MT46H16M16LFLOT.fm - Rev. H 6/08 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
256Mb: x16, x32 Mobile DDR SDRAM
FBGA Part Marking Decoder
Figure 1:
256Mb Mobile DDR Part Numbering
Example Part Number: MT46H16M 16LFXX-75IT :A
Micron DDR MT46 VDD/
VDDQ
Mobile Configuration
Package
–
Speed
Temp
Revision
VDD/VDDQ
1.8V/1.8V
Revision
H
:A
Configuration
First Generation
Operating Temp
16 Meg x 16
16M16LF
8 Meg x 32
8M32LF
Commercial
IT
Industrial
Package
60-Ball VFBGA (lead-free) BF
90-Ball VFBGA (lead-free) B5
Speed Grade
-6
tCK = 6.0ns
-75
tCK = 7.5ns
-10
tCK = 9.6ns
FBGA Part Marking Decoder
Due to space limitations, FBGA-packaged components have an abbreviated part
marking that is different from the part number. For a quick conversion of an FBGA code,
see the FBGA part marking decoder at www.micron.com/decoder.
General Description
The 256Mb Mobile DDR SDRAM is a high-speed CMOS, dynamic random-access
memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM.
On the x16 device, each of the 67,108,864-bit banks is organized as 8,192 rows by 512
columns by 16 bits. On the x32 device, each of the 67,108,864-bit banks is organized as
4,096 rows by 512 columns by 32 bits.
The 256Mb Mobile DDR SDRAM uses a double data rate architecture to achieve highspeed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O
balls. A single read or write access for the 256Mb Mobile DDR SDRAM effectively
consists of a single 2n-bit-wide, one-clock-cycle data transfer at the internal DRAM core
and two corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O balls.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in
data capture at the receiver. DQS is a strobe transmitted by the Mobile DDR SDRAM
during READs and by the memory controller during WRITEs. DQS is edge-aligned with
data for READs and center-aligned with data for WRITEs. The x16 offering has two data
strobes: one for the lower byte and one for the upper byte. The x32 offering has four data
strobes, one per byte.
PDF: 09005aef82091978 / Source: 09005aef8209195b
MT46H16M16LF__2.fm - Rev. H 6/08 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
256Mb: x16, x32 Mobile DDR SDRAM
General Description
The 256Mb Mobile DDR SDRAM operates from a differential clock (CK and CK#); the
crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of
CK. Commands (address and control signals) are registered at every positive edge of CK.
Input data is registered on both edges of DQS, and output data is referenced to both
edges of DQS, as well as to both edges of CK.
Read and write accesses to the Mobile DDR SDRAM are burst oriented; accesses start at
a selected location and continue for a programmed number of locations in a
programmed sequence. Accesses begin with the registration of an ACTIVE command,
which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed.
The address bits registered coincident with the READ or WRITE command are used to
select the bank and the starting column location for the burst access.
The Mobile DDR SDRAM provides for programmable READ or WRITE burst lengths of 2,
4, or 8. An auto precharge function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst access.
As with standard SDR SDRAM, the pipelined, multibank architecture of Mobile DDR
SDRAM enables concurrent operation, thereby providing high effective bandwidth by
hiding row precharge and activation time.
An auto refresh mode is provided, along with a power-saving power-down mode. Deep
power-down mode is offered to achieve maximum power reduction by eliminating the
power draw of the memory array. Data will not be retained when the device enters DPD
mode.
Self refresh mode offers temperature compensation through an on-chip temperature
sensor and partial-array self refresh, which enables users to achieve additional power
savings. The temperature sensor is enabled by default, and the partial-array self refresh
can be programmed through the extended mode register.
Notes:
1. Throughout the data sheet, various figures and text refer to DQs as “DQ.” The DQ
term is to be interpreted as any and all DQ collectively, unless specifically stated otherwise.
2. Complete functionality is described throughout the document, and any page or diagram may have been simplified to convey a topic and may not be inclusive of all
requirements.
3. Any specific requirement takes precedence over a general statement.
PDF: 09005aef82091978 / Source: 09005aef8209195b
MT46H16M16LF__2.fm - Rev. H 6/08 EN
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
256Mb: x16, x32 Mobile DDR SDRAM
General Description
Functional Block Diagrams
Figure 2:
Functional Block Diagram (16 Meg x 16)
CKE
CK#
CK
Command
decode
CS#
WE#
CAS#
RAS#
Control
logic
Bank 3
Bank 2
Bank 1
Refresh
counter
13
Standard mode
register
Extended mode
register
Rowaddress
MUX
13
13
13
Bank 0
Rowaddress
Latch
and
decoder
8,192
Bank 0
Memory
array
(8,192 x 256 x 32)
Data
16
32
Read
latch
Sense amplifiers
16
MUX
DRVRS
16
DQS
generator
16,384
2
DQ0–
DQ15
COL 0
I/O gating
DM mask logic
2
A0–A12,
BA0, BA1
15
Address
register
2
Input
registers
2
2
2
2
16
16
MASK
256
(x32)
Column
decoder
9
32
Bank
control
logic
Columnaddress
Counter/
latch
DQS
CK
8
32
WRITE
FIFO
and
drivers
CK
out
CK
in
LDQS,
UDQS
2
4
32
RCVRS
16
16
LDM,
UDM
16
DATA
CK
2
COL 0
1
PDF: 09005aef82091978 / Source: 09005aef8209195b
MT46H16M16LF__2.fm - Rev. H 6/08 EN
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
256Mb: x16, x32 Mobile DDR SDRAM
General Description
Figure 3:
Functional Block Diagram (8 Meg x 32)
CKE
CK#
CK
Command
decode
CS#
WE#
CAS#
RAS#
Control
logic
Bank 3
Bank 2
Bank 1
Refresh
counter
13
Standard mode
register
Extended mode
register
Rowaddress
MUX
12
12
12
Bank 0
Rowaddress
Latch
and
decoder
8,192
Bank 0
Memory
array
(4,096 x 256 x 64)
DATA
32
64
READ
latch
Sense amplifiers
32
MUX
DRVRS
32
4
DQS
generator
4,092
DQ0–
DQ31
COL 0
2
A0–A11,
BA0, BA1
14
Address
register
2
I/O gating
DM mask logic
Bank
control
logic
DQS
CK
64
4
Input
registers
256
(x64)
64
WRITE
FIFO
and
drivers
4
4
4
32
32
8
64
Column
decoder
9
Columnaddress
Counter/
latch
CK
out
8
DQS0
DQS1
DQS2
DQS3
4
MASK
CK
in
RCVRS
32
32
32
DATA
CK
DQM0
DQM1
DQM2
DQM3
4
COL 0
1
Notes:
1. JEDEC-standard x32 DQ configuration shown.
PDF: 09005aef82091978 / Source: 09005aef8209195b
MT46H16M16LF__2.fm - Rev. H 6/08 EN
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
256Mb: x16, x32 Mobile DDR SDRAM
General Description
Ballouts and Ball Descriptions
Figure 4:
60-Ball VFBGA Ball Assignments – 8mm x 9mm (Top View)
1
2
3
VSS
DQ15
VDDQ
4
5
6
7
8
9
VSSQ
VDDQ
DQ0
VDD
DQ13
DQ14
DQ1
DQ2
VSSQ
VSSQ
DQ11
DQ12
DQ3
DQ4
VDDQ
VDDQ
DQ9
DQ10
DQ5
DQ6
TEST1
VSSQ
UDQS
DQ8
DQ7
LDQS
VDDQ
VSS
UDM
NC
NC
LDM
VDD
CKE
CK
CK#
WE#
CAS#
RAS#
A9
A11
A12
CS#
BA0
BA1
A6
A7
A8
A10/AP
A0
A1
VSS
A4
A5
A2
A3
VDD
A
B
C
D
E
F
G
H
J
K
Ball Down
Notes:
1. D9 is a test pin that must be connected to VSS or VSSQ in normal operation.
PDF: 09005aef82091978 / Source: 09005aef8209195b
MT46H16M16LF__2.fm - Rev. H 6/08 EN
9
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
256Mb: x16, x32 Mobile DDR SDRAM
General Description
Figure 5:
90-Ball VFBGA Ball Assignments – 8mm x 13mm (Top View)
1
2
3
VSS
DQ31
VDDQ
4
5
6
7
8
9
VSSQ
VDDQ
DQ16
VDD
DQ29
DQ30
DQ17
DQ18
VSSQ
VSSQ
DQ27
DQ28
DQ19
DQ20
VDDQ
VDDQ
DQ25
DQ26
DQ21
DQ22
TEST1
VSSQ
DQS3
DQ24
DQ23
DQS2
VDDQ
VDD
DM3
NC
NC
DM2
VSS
CKE
CK
CK#
WE#
CAS#
RAS#
A9
A11
A12/DNU
CS#
BA0
BA1
A6
A7
A8
A10/AP
A0
A1
A4
DM1
A5
A2
DM0
A3
VSSQ
DQS1
DQ8
DQ7
DQS0
VDDQ
VDDQ
DQ9
DQ10
DQ5
DQ6
VSSQ
VSSQ
DQ11
DQ12
DQ3
DQ4
VDDQ
VDDQ
DQ13
DQ14
DQ1
DQ2
VSSQ
VSS
DQ15
VSSQ
VDDQ
DQ0
VDD
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
Ball Down
Notes:
1. D9 is a test pin that must be connected to VSS or VSSQ in normal operation.
PDF: 09005aef82091978 / Source: 09005aef8209195b
MT46H16M16LF__2.fm - Rev. H 6/08 EN
10
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
256Mb: x16, x32 Mobile DDR SDRAM
General Description
Table 3:
60-Ball VFBGA Ball Descriptions
Ball Numbers
Symbol
Type
Description
G2, G3
CK, CK#
Input
G1
CKE
Input
H7
CS#
Input
G9, G8, G7
Input
F2, F8
RAS#, CAS#,
WE#
UDM, LDM
Input
H8, H9
BA0, BA1
Input
J8, J9, K7, K8, K2, K3,
J1, J2, J3, H1, J7, H2, H3
A0–A12
Input
A8, B7, B8, C7, C8, D7,
D8, E7, E3, D2, D3, C2,
C3, B2, B3, A2
E2, E8
DQ0–DQ15
I/O
Clock: CK is the system clock input. CK and CK# are differential clock
inputs. All address and control input signals are sampled on the
crossing of the positive edge of CK and the negative edge of CK#.
Input and output data is referenced to the crossing of CK and CK#
(both directions of the crossing).
Clock enable: CKE HIGH activates and CKE LOW deactivates the
internal clock signals, input buffers, and output drivers. Taking CKE
LOW enables PRECHARGE power-down and SELF REFRESH operations
(all banks idle) or ACTIVE power-down (row active in any bank). CKE is
synchronous for all functions except SELF REFRESH exit. All input
buffers (except CKE) are disabled during power-down and self refresh
modes.
Chip select: CS# enables (registered LOW) and disables (registered
HIGH) the command decoder. All commands are masked when CS# is
registered HIGH. CS# provides for external bank selection on systems
with multiple banks. CS# is considered part of the command code.
Command inputs: RAS#, CAS#, and WE# (along with CS#) define the
command being entered.
Input data mask: DM is an input mask signal for write data. Input
data is masked when DM is sampled HIGH along with that input data
during a WRITE access. DM is sampled on both edges of DQS. Although
DM balls are input-only, the DM loading is designed to match that of
DQ and DQS balls. For the x16, LDM is DM for DQ0–DQ7, and UDM is
DM for DQ8–DQ15.
Bank address inputs: BA0 and BA1 define to which bank an ACTIVE,
READ, WRITE, or PRECHARGE command is being applied. BA0 and BA1
also determine which mode register (standard mode register or
extended mode register) is loaded during a LOAD MODE REGISTER
command.
Address inputs: Provide the row address for ACTIVE commands, and
the column address and auto precharge bit (A10) for READ/WRITE
commands, to select one location out of the memory array in the
respective bank. During a PRECHARGE command, A10 determines
whether the PRECHARGE applies to one bank (A10 LOW, bank selected
by BA0, BA1) or all banks (A10 HIGH). The address inputs also provide
the op-code during a LOAD MODE REGISTER command.
Data input/output: Data bus for x16.
UDQS, LDQS
I/O
VDDQ
VSSQ
VDD
VSS
Supply
Supply
Supply
Supply
–
–
A7, B1, C9, D1, E9
A3, B9, C1, E1
A9, F9, K9
A1, F1, K1
F3, F7
D9
PDF: 09005aef82091978 / Source: 09005aef8209195b
MT46H16M16LF__2.fm - Rev. H 6/08 EN
NC
TEST
Data strobe: Output with read data, input with write data. DQS is
edge-aligned with read data, center-aligned with write data. Data
strobe is used to capture data.
DQ power supply.
DQ ground.
Power supply.
Ground.
No connect: May be left unconnected.
Test pin that must be connected to Vss or VSSQ in normal operation.
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
256Mb: x16, x32 Mobile DDR SDRAM
General Description
Table 4:
90-Ball VFBGA Ball Description
Ball Numbers
Symbol
Type
Description
G2, G3
CK, CK#
Input
G1
CKE
Input
H7
CS#
Input
G9, G8, G7
Input
K8, K2, F8, F2
RAS#, CAS#,
WE#
DM0–DM3
H8, H9
BA0, BA1
Input
J8, J9, K7, K9, K1, K3,
J1, J2, J3, H1, J7, H2
A0–A11
Input
H3
A12/DNU
Input
R8, P7, P8, N7, N8, M7,
M8, L7, L3, M2, M3,
N2, N3, P2, P3, R2, A8,
B7, B8, C7, C8, D7, D8,
E7, E3, D2, D3, C2, C3,
B2, B3, A2
L8, L2, E8, E2
DQ0–DQ31
I/O
Clock: CK is the system clock input. CK and CK# are differential clock
inputs. All address and control input signals are sampled on the
crossing of the positive edge of CK and the negative edge of CK#. Input
and output data is referenced to the crossing of CK and CK# (both
directions of the crossing).
Clock enable: CKE HIGH activates and CKE LOW deactivates the
internal clock signals, input buffers, and output drivers. Taking CKE
LOW enables PRECHARGE power-down and SELF REFRESH operations
(all banks idle) or ACTIVE power-down (row active in any bank). CKE is
synchronous for all functions except SELF REFRESH exit. All input
buffers (except CKE) are disabled during power-down and self refresh
modes.
Chip select: CS# enables the command decoder (registered LOW) and
disables the command decoder (registered HIGH). All commands are
masked when CS# is registered HIGH. CS# provides for external bank
selection on systems with multiple banks. CS# is considered part of the
command code.
Command inputs: RAS#, CAS#, and WE# (along with CS#) define the
command being entered.
Input data mask: DM is an input mask signal for write data. Input
data is masked when DM is sampled HIGH along with that input data
during a WRITE access. DM is sampled on both edges of DQS. Although
DM balls are input-only, the DM loading is designed to match that of
DQ and DQS balls. For the x32, DM0 is DM for DQ0–DQ7; DM1 is DM
for DQ8–DQ15; DM2 is DM for DQ16–DQ23; and DM3 is DM for DQ24–
DQ31.
Bank address inputs: BA0 and BA1 define to which bank an ACTIVE,
READ, WRITE, or PRECHARGE command is being applied. BA0 and BA1
also determine which mode register (standard mode register or
extended mode register) is loaded during a LOAD MODE REGISTER
command.
Address inputs: Provide the row address for ACTIVE commands, and
the column address and auto precharge bit (A10) for READ or WRITE
commands, to select one location out of the memory array in the
respective bank. During a PRECHARGE command, A10 determines
whether the PRECHARGE applies to one bank (A10 LOW, bank selected
by BA0, BA1) or all banks (A10 HIGH). The address inputs also provide
the op-code during a LOAD MODE REGISTER command.
A12 is an address input for the LG reduced page-size option (see
“Options” on page 1). Leave as DNU for JEDEC-standard option.
Data input/output: Data bus for x32.
DQS0–DQS3
I/O
VDDQ
Supply
A7, B1, C9, D1, E9, L9,
M1, N9, P1, R7
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MT46H16M16LF__2.fm - Rev. H 6/08 EN
Input
Data strobe: Output with read data, input with write data. DQS is
edge-aligned with read data, center-aligned with write data. Data
strobe is used to capture data.
DQ power supply.
12
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256Mb: x16, x32 Mobile DDR SDRAM
General Description
Table 4:
90-Ball VFBGA Ball Description (Continued)
Ball Numbers
Symbol
Type
A3, B9, C1, E1, L1, M9,
N1, P9, R3
A9, F1, R9
A1, F9, R1
F3, F7
D9
VSSQ
Supply
DQ ground.
VDD
VSS
Supply
Supply
–
–
Power supply
Ground.
No connect: May be left unconnected.
Test pin that must be connected to VSS or VSSQ in normal operation.
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NC
TEST
Description
13
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256Mb: x16, x32 Mobile DDR SDRAM
Functional Description
Functional Description
The 256Mb Mobile DDR SDRAM is a high-speed CMOS, dynamic random-access
memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM.
Each of the 67,108,864-bit banks on the x16 is organized as 8,192 rows by 512 columns by
16 bits. Each of the 67,108,864-bit banks on the x32 is organized as 4,096 rows by 512
columns by 32 bits for the standard addressing configuration.
The 256Mb Mobile DDR SDRAM uses a double data rate architecture to achieve highspeed operation. The double data rate architecture is essentially a 2n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O
balls. Single read or write access for the 256Mb Mobile DDR SDRAM consists of a single
2n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O balls.
Read and write accesses to the Mobile DDR SDRAM are burst oriented; accesses start at
a selected location and continue for a programmed number of locations in a
programmed sequence. Accesses begin with the registration of an ACTIVE command,
which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed.
The address bits registered coincident with the READ or WRITE command are used to
select the starting column location for the burst access.
The DLL circuit that is typically used on standard DDR devices is not necessary on the
Mobile DDR SDRAM. It has been omitted to save power.
Prior to normal operation, the Mobile DDR SDRAM must be initialized. The following
sections provide detailed information covering device initialization, register definition,
command descriptions, and device operation.
Initialization
Mobile DDR SDRAMs must be powered up and initialized in a predefined manner.
Operational procedures other than those specified may result in undefined operation.
If there is an interruption to the device power, the initialization routine must be
followed to ensure proper functionality of the Mobile DDR SDRAM. The clock stop
feature is not available until the device has been properly initialized.
To properly initialize the Mobile DDR SDRAM, this sequence must be followed:
1. The core power (VDD) and I/O power (VDDQ) must be brought up simultaneously. It is
recommended that VDD and VDDQ be from the same power source, or VDDQ must
never exceed VDD. Assert and hold CKE HIGH.
2. After power supply voltages are stable and the CKE has been driven HIGH, it is safe to
apply the clock.
3. After the clock is stable, a 200µs (MIN) delay is required by the Mobile DDR SDRAM
prior to applying an executable command. During this time, a NOP or DESELECT
command must be issued on the command bus.
4. Issue a PRECHARGE ALL command.
5. Issue a NOP or DESELECT command for at least tRP time.
6. Issue an AUTO REFRESH command followed by a NOP or DESELECT command for
at least tRFC time. Issue a second AUTO REFRESH command followed by a NOP or
DESELECT command for at least tRFC time. As part of the initialization sequence, two
AUTO REFRESH commands must be issued.
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256Mb: x16, x32 Mobile DDR SDRAM
Register Definition
7. Using the LOAD MODE REGISTER command, load the standard mode register as
desired.
8. Issue a NOP or DESELECT command for at least tMRD time.
9. Using the LOAD MODE REGISTER command, load the extended mode register to the
desired operating modes. Note that the sequence in which the standard and extended
mode registers are programmed is not critical.
10. Issue NOP or DESELECT commands for at least tMRD time.
The Mobile DDR SDRAM has been properly initialized and is ready to receive any valid
command.
Register Definition
Mode Registers
The mode registers are used to define the specific mode of operation of the Mobile DDR
SDRAM. Two mode registers are used to specify the operational characteristics of the
device.
Standard Mode Register
The standard mode register bit definition enables the selection of burst length, burst
type, CAS latency, and operating mode, as shown in Figure 6 on page 16. Reserved states
should not be used, as this may result in setting the device into an unknown state or
cause incompatibility with future versions of Mobile DDR SDRAM. The standard mode
register is programmed via the LOAD MODE REGISTER command (with BA0 = 0 and
BA1 = 0) and will retain the stored information until it is programmed again, the device
goes into deep power-down mode, or the device loses power.
Reprogramming the mode register will not alter the contents of the memory, provided it
is performed correctly. The mode register must be loaded when all banks are idle and no
bursts are in progress, and the controller must wait before initiating the subsequent
operation. Violating any of these requirements will result in unspecified operation.
Burst Length
Read and write accesses to the Mobile DDR SDRAM are burst oriented; the burst length
is programmable. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 2, 4, or
8 locations are available for both sequential and interleaved burst types.
When a READ or WRITE command is issued, a block of columns equal to the burst
length is effectively selected. All accesses for that burst take place within this block,
meaning that the burst will wrap when a boundary is reached. The block is uniquely
selected by A1–Ai when BL = 2, by A2–Ai when BL = 4, and by A3–Ai when BL = 8, where
Ai is the most significant column address bit for a given configuration. The remaining
(least significant) address bits are used to specify the starting location within the block.
The programmed burst length applies to both READ and WRITE bursts.
Burst Type
Accesses within a given burst may be programmed either to be sequential or interleaved
via the standard mode register.
The ordering of accesses within a burst is determined by the burst length, the burst type,
and the starting column address (see Table 5 on page 17).
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256Mb: x16, x32 Mobile DDR SDRAM
Register Definition
CAS Latency
The CAS latency is the delay, in clock cycles, between the registration of a READ
command and the availability of the first output data. The latency can be set to two or
three clocks, as shown in Figure 7 on page 18.
For CAS latency three (CL = 3), if the READ command is registered at clock edge n, then
the data will nominally be available at (n + 2 clocks + tAC). For CL = 2, if the READ
command is registered at clock edge n, then the data will be nominally be available at (n
+ 1 clock + tAC).
Figure 6:
Standard Mode Register Definition
Address Bus
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
14 13 12
0
11 10
9
8
7
Operating Mode
0
6
5
4
3
2
1
0
Standard Mode Register (Mx)
CAS Latency BT Burst Length
M14 M13 Mode Register Definition
Burst Length
0
0
Standard mode register
0
1
Reserved
0
1
0
Extended mode register
1
1
Reserved
M2 M1 M0
M3
M6 M5 M4
M3 = 0
M3 = 1
0 0
Reserved
Reserved
0
0 1
2
2
0
1 0
4
4
0
1 1
8
8
1
0 0
Reserved
Reserved
1
0 1
Reserved
Reserved
1
1 0
Reserved
Reserved
1
1 1
Reserved
Reserved
Burst Type
0
Sequential
1
Interleaved
CAS Latency
0
0
0
Reserved
0
0
1
Reserved
0
1
0
2
0
1
1
3
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
M12 M11 M10 M9 M8 M7 M6–M0 Operating Mode
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0
0
0
0
0
0
–
–
–
–
–
–
Valid
Normal operation
All other states reserved
16
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256Mb: x16, x32 Mobile DDR SDRAM
Register Definition
Table 5:
Burst
Length
Burst Definition Table
Order of Accesses Within a Burst
Starting Column Address
2
4
8
A2
0
0
0
0
1
1
1
1
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A1
0
0
1
1
A1
0
0
1
1
0
0
1
1
A0
0
1
A0
0
1
0
1
A0
0
1
0
1
0
1
0
1
Type = Sequential
Type = Interleaved
0-1
1-0
0-1
1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
17
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256Mb: x16, x32 Mobile DDR SDRAM
Register Definition
Figure 7:
CAS Latency
T0
T1
READ
NOP
T1n
T2
T2n
T3
T3n
CK#
CK
Command
NOP
NOP
tAC
1n clock
CL = 2
DQS
DQ
DOUT
n
DOUT
n+1
DOUT
n+2
DOUT
n+3
T2n
T3
T3n
T0
T1
T2
READ
NOP
NOP
CK#
CK
Command
NOP
tAC
2n clock
CL = 3
DQS
DOUT
n
DQ
Transitioning data
Notes:
DOUT
n+1
Don’t Care
1. BL = 4 in the cases shown.
2. Shown with nominal tAC and nominal tDQSQ.
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256Mb: x16, x32 Mobile DDR SDRAM
Register Definition
Operating Mode
The normal operating mode is selected by issuing a LOAD MODE REGISTER command
with bits A7–A11 (x32) or A7–A12 (x16) each set to zero and bits A0–A6 set to the desired
values.
All other combinations of values for A7–A11/A12 are reserved for future use and/or test
modes. Test modes and reserved states should not be used, because unknown operation
or incompatibility with future versions may result.
Extended Mode Register
The extended mode register controls functions specific to Mobile SDRAM operation.
These additional functions include drive strength, temperature-compensated self
refresh, and partial-array self refresh.
The extended mode register is programmed via the LOAD MODE REGISTER command
(with BA0 = 0 and BA1 = 1) and will retain the stored information until it is programmed
again, the device goes into deep power-down mode, or the device loses power.
Temperature-Compensated Self Refresh
On this version of the Mobile DDR SDRAM, a temperature sensor is implemented for
automatic control of the SELF REFRESH oscillator. Programming the TCSR bits will have
no effect on the device. The SELF REFRESH oscillator will continue to refresh at the
factory-programmed optimal rate for the device temperature.
Partial-Array Self Refresh
For further power savings during SELF REFRESH, the partial-array self refresh (PASR)
feature enables the controller to select the amount of memory that will be refreshed
during SELF REFRESH.
Table 6:
Partial-Array Self Refresh Options
Memory
Bank
Full array
Half array
Quarter array
Eighth array
Sixteenth array
Banks 0, 1, 2, and 3
Banks 0 and 1
Bank 0
Bank 0 with row address MSB = 0
Bank 0 with row address MSB = 0 and MSB - 1 = 0
WRITE and READ commands can still occur during standard operation, but only the
selected regions of the array will be refreshed during SELF REFRESH. Data in regions
that are not selected will be lost.
Output Driver Strength
Because the Mobile DDR SDRAM is designed for use in smaller systems that are typically
point-to-point connections, an option to control the drive strength of the output buffers
is provided. Drive strength should be selected based on expected loading of the memory
bus. There are four allowable settings for the output drivers: 25Ω, 55Ω, 80Ω, and 100Ω
internal impedance.
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256Mb: x16, x32 Mobile DDR SDRAM
Register Definition
Figure 8:
Extended Mode Register
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1
A0
E14 E13 E12 E11 E10 E9
E8
E7
E6
E0
14
1
8
7
6 5
DS
13 12
0
11
E14 E13 Mode Register Definition
0 Standard mode register
0
1 Reserved
0
0 Extended mode register
1
1 Reserved
1
E12 E11 E10 E9
0
0
0
0
–
–
–
–
E8
0
–
Notes:
E7
0
–
E6–E0
Valid
–
9
10
Set to “0”
E5
E4
E3
4
3
TCSR1
0
0
E5 Driver Strength
0 Full-strength driver
1 Half-strength driver
1
1
0
1
E6
E2
2
E1
0
1
PASR
Address Bus
Extended Mode
Register
Quarter-strength driver
One-eighth-strength driver
Operating Mode
Normal operation
All other states reserved
E2
E1
E0
0
0
0
Partial-Array Self Refresh Coverage
Full array
0
0
1
Half array
0
1
0
Quarter array
0
1
1
Reserved
1
0
0
Reserved
1
0
1
One-eighth array
1
1
0
One-sixteenth array
1
1
1
Reserved
1. On-die temperature sensor is used in place of TCSR. Setting these bits will have no effect.
Stopping the External Clock
One method of controlling the power efficiency in applications is to throttle the clock
that controls the DDR SDRAM. Control the clock in two ways:
• Change the clock frequency.
• Stop the clock.
The Mobile DDR SDRAM enables the clock to change frequency during operation only if
all the timing parameters are met and all refresh requirements are satisfied.
The clock can be stopped if no DRAM operations are in progress that would be affected
by this change. Any DRAM operation already in process must be completed before
entering clock stop mode; this includes the following timings: tRCD, tRP, tRFC, tMRD,
t
WR, and all data-out for READ bursts.
For example, if a WRITE or a READ is in progress, the entire data burst must be complete
prior to stopping the clock. For READs, a burst completion is defined when the read
postamble is satisfied. For WRITEs, a burst completion is defined when the write postamble and tWR or tWTR are satisfied.
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256Mb: x16, x32 Mobile DDR SDRAM
Register Definition
CKE must be held HIGH with CK = LOW and CK# = HIGH for the full duration of the
clock stop mode. One clock cycle and at least one NOP or DESELECT is required after
the clock is restarted before a valid command can be issued. Figure 9 on page 21 illustrates the clock stop mode.
Figure 9:
Clock Stop Mode
Ta1
CK#
CK
CKE
((
))
((
))
Address
((
))
((
))
DQ, DQS
((
))
(High-Z)
Tb3
((
))
((
))
((
))
((
))
Command
Ta2
((
))
((
))
NOP1
Tb4
((
))
((
))
((
))
((
))
2
( ( CMD
))
CMD2
((
))
((
))
Valid
((
))
((
))
Exit clock stop mode
NOP
NOP
((
))
((
))
((
))
((
))
Valid
((
))
All DRAM activities
must be complete
Enter clock stop mode
Don’t Care
Notes:
1. Prior to Ta1, the device is in clock stop mode. To exit, at least one NOP is required before
any valid command is issued.
2. Any valid command is allowed; device is not in clock stop mode.
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256Mb: x16, x32 Mobile DDR SDRAM
Commands
Commands
Tables 7 and 8 provide a quick reference of available commands. This is followed by a
description of each command. Three additional truth tables provide CKE commands
and current/next state information (see Table 9 on page 51, Table 10 on page 52, and
Table 11 on page 54).
Table 7:
Truth Table – Commands
Notes 1 and 2 apply to all commands
Name (Function)
DESELECT (NOP)
NO OPERATION (NOP)
ACTIVE (select bank and activate row)
READ (select bank and column, and start READ burst)
WRITE (select bank and column, and start WRITE burst)
BURST TERMINATE or deep power-down
(enter deep power-down mode)
PRECHARGE (deactivate row in bank or banks)
AUTO REFRESH (refresh all or single bank) or
SELF REFRESH (enter self refresh mode)
LOAD MODE REGISTER (standard or extended mode
registers)
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
Table 8:
CS#
RAS#
CAS#
WE#
Address
Notes
H
L
L
L
L
L
X
H
L
H
H
H
X
H
H
L
L
H
X
H
H
H
L
L
X
X
Bank/row
Bank/column
Bank/column
X
3
3
4
5
5
6, 7
L
L
L
L
H
L
L
H
Code
X
8
9, 10
L
L
L
L
Op-code
11
CKE is HIGH for all commands shown except SELF REFRESH and deep power-down.
All states and sequences not shown are reserved and/or illegal.
DESELECT and NOP are functionally interchangeable.
BA0–BA1 provide bank address and A0–A12/A13 provide row address.
BA0–BA1 provide bank address; A0–A8 provide column address; A10 HIGH enables the auto
precharge feature (nonpersistent); A10 LOW disables the auto precharge feature.
Applies only to read bursts with auto precharge disabled; this command is undefined (and
should not be used) for READ bursts with auto precharge enabled and for WRITE bursts.
This command is a BURST TERMINATE if CKE is HIGH and deep power-down if CKE is LOW.
A10 LOW: BA0–BA1 determine which bank is precharged.
A10 HIGH: all banks are precharged and BA0–BA1 are “Don’t Care.”
This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
Internal refresh counter controls row addressing; all self refresh inputs and I/Os are “Don’t
Care” except for CKE.
BA0–BA1 either select the standard mode register or the extended mode register
(BA0 = 0, BA1 = 0 select the standard mode register; BA0 = 0, BA1 = 1 select extended mode
register; other combinations of BA0–BA1 are reserved). A0–A12/A13 provide the op-code to
be written to the selected mode register.
Truth Table – DM Operation
Name (Function)
Write enable
Write inhibit
Notes:
DM
DQ
Notes
L
H
Valid
X
1, 2
1, 2
1. Used to mask write data; provided coincident with the corresponding data.
2. All states and sequences not shown are reserved and illegal.
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256Mb: x16, x32 Mobile DDR SDRAM
Commands
DESELECT
The DESELECT function (CS# HIGH) prevents new commands from being executed by
the Mobile DDR SDRAM. Operations already in progress are not affected.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to instruct the selected Mobile DDR
SDRAM to perform a NOP (CS# is LOW with RAS#, CAS#, and WE# HIGH). This prevents
unwanted commands from being registered during idle or wait states. Operations
already in progress are not affected.
LOAD MODE REGISTER
The mode registers are loaded via inputs BA0–BA1 and A0–A12. See mode register
descriptions in “Register Definition” on page 15. The LOAD MODE REGISTER
command can only be issued when all banks are idle, and a subsequent executable
command cannot be issued until tMRD is met.
ACTIVE
The ACTIVE command is used to open (or activate) a row in a particular bank for a
subsequent access. The value on the BA0 and BA1 inputs selects the bank, and the
address provided on inputs A0–A12 selects the row. This row remains active (or open)
for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE
command must be issued before opening a different row in the same bank.
READ
The READ command is used to initiate a burst read access to an active row. The value on
the BA0, BA1 inputs selects the bank, and the address provided on inputs A0–Ai (where i
= the most significant column address bit for each configuration) selects the starting
column location. The value on input A10 determines whether auto precharge is used. If
auto precharge is selected, the row being accessed will be precharged at the end of the
READ burst; if auto precharge is not selected, the row will remain open for subsequent
accesses.
WRITE
The WRITE command is used to initiate a burst write access to an active row. The value
on the BA0–BA1 inputs selects the bank, and the address provided on inputs A0–Ai
(where i = the most significant column address bit for each configuration) selects the
starting column location. The value on input A10 determines whether auto precharge is
used. If auto precharge is selected, the row being accessed will be precharged at the end
of the WRITE burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Input data appearing on the DQ is written to the memory array subject
to the DM input logic level appearing coincident with the data. If a given DM signal is
registered LOW, the corresponding data will be written to memory; if the DM signal is
registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be
executed to that byte/column location.
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256Mb: x16, x32 Mobile DDR SDRAM
Commands
PRECHARGE
The PRECHARGE command is used to deactivate the open row in a particular bank or
the open row in all banks. The bank(s) will be available for a subsequent row access a
specified time (tRP) after the PRECHARGE command is issued. The exception is the case
of concurrent auto precharge, where a READ or WRITE command to a different bank is
allowed as long as it does not interrupt the data transfer in the current bank and does
not violate any other timing parameters. Input A10 determines whether one or all banks
are to be precharged, and in the case where only one bank is to be precharged, inputs
BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as “Don’t Care.” After a bank
has been precharged, it is in the idle state and must be activated prior to any READ or
WRITE commands being issued to that bank. A PRECHARGE command will be treated
as a NOP if there is no open row in that bank (idle state) or if the previously open row is
already in the process of precharging.
BURST TERMINATE
The BURST TERMINATE command is used to truncate READ bursts (with auto
precharge disabled). The most recently registered READ command prior to the BURST
TERMINATE command will be truncated, as described in “Operations” on page 26. The
open page from which the READ burst was terminated remains open.
AUTO REFRESH
The AUTO REFRESH command is nonpersistent and must be issued each time a refresh
is required.
The addressing is generated by the internal refresh controller. This makes the address
bits a “Don’t Care” during an AUTO REFRESH command. The 256Mb Mobile DDR
SDRAM requires AUTO REFRESH cycles at an average interval of 7.8125µs (MAX).
To enable improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided.
Although not a JEDEC requirement, CKE must be active (HIGH) during the auto refresh
period to provide for future functionality features. The auto refresh period begins when
the AUTO REFRESH command is registered, and it ends tRFC later.
SELF REFRESH
The SELF REFRESH command can be used to retain data in the Mobile DDR SDRAM,
even if the rest of the system is powered down. When in the self refresh mode, the
Mobile DDR SDRAM retains data without external clocking. The SELF REFRESH
command is initiated like an AUTO REFRESH command, except that CKE is disabled
(LOW). All command and address input signals except CKE are “Don’t Care” during
SELF REFRESH. For details on entering and exiting self refresh mode, see Figure 44 on
page 72. During SELF REFRESH, the device is refreshed as identified in the extended
mode register (see PASR setting).
Auto Precharge
Auto precharge is a feature that performs the same individual-bank PRECHARGE function described above, without requiring an explicit command. This is accomplished by
using A10 to enable auto precharge in conjunction with a specific READ or WRITE
command. A precharge of the bank/row that is addressed with the READ or WRITE
command is automatically performed upon completion of the READ or WRITE burst.
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©2005 Micron Technology, Inc. All rights reserved.
256Mb: x16, x32 Mobile DDR SDRAM
Commands
Auto precharge is nonpersistent in that it is either enabled or disabled for each individual READ or WRITE command. This device supports concurrent auto precharge if the
command to the other bank does not interrupt the data transfer to the current bank.
Auto precharge ensures that the precharge is initiated at the earliest valid stage within a
burst. This earliest valid stage is determined as if an explicit PRECHARGE command
were issued at the earliest possible time, without violating tRAS (MIN), as described for
each burst type in “Operations” on page 26. The user must not issue another command
to the same bank until the precharge time (tRP) is completed.
Deep Power-Down
Deep power-down is an operating mode used to achieve maximum power reduction by
eliminating the power draw of the memory array. Data will not be retained when the
device enters deep power-down mode.
Figure 10:
Mobile DRAM State Diagram
Power
applied
Power
on
Deep
power-down
DPDSX
Precharge
all banks
Self
refresh
DPDS
REFSX
Idle
all banks
precharged
MRS
MRS
EMRS
REFS
REFA
Auto
refresh
CKEL
CKEH
Active
power-down
Precharge
power-down
ACT
CKEH
CKEL
Row
active
Burst
stop
READ
WRITE
BST
WRITE
WRITE A
READ A
WRITE
READ
WRITE A
READ A
PRE
WRITE A
READ
READ
READ A
PRE
PRE
READ A
Precharge
PREALL
PRE
Automatic sequence
Command sequence
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256Mb: x16, x32 Mobile DDR SDRAM
Operations
Operations
Bank/Row Activation
Before any READ or WRITE commands can be issued to a bank within the Mobile DDR
SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE
command, which selects both the bank and the row to be activated, as shown in
Figure 11.
After a row is opened with an ACTIVE command, a READ or WRITE command may be
issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by
the clock period and rounded up to the next whole number to determine the earliest
clock edge after the ACTIVE command on which a READ or WRITE command can be
entered. For example, a tRCD specification of 20ns with a 133 MHz clock (7.5ns period)
results in 2.7 clocks rounded to 3. This is reflected in Figure 12 on page 27, which covers
any case where 2 < tRCD (MIN)/ tCK ≤ 3. (Figure 12 also shows the same case for tRRD;
the same procedure is used to convert other specification limits from time units to clock
cycles.)
A subsequent ACTIVE command to a different row in the same bank can only be issued
after the previous active row has been “closed” (precharged). The minimum time
interval between successive ACTIVE commands to the same bank is defined by tRC.
A subsequent ACTIVE command to another bank can be issued while the first bank is
being accessed, which results in a reduction of total row-access overhead. The
minimum time interval between successive ACTIVE commands to different banks is
defined by tRRD.
Figure 11:
Activating a Specific Row in a Specific Bank
CK#
CK
CKE
HIGH
CS#
RAS#
CAS#
WE#
Notes:
A0–A12
RA
BA0, BA1
BA
1. RA = row address
2. BA = bank address
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256Mb: x16, x32 Mobile DDR SDRAM
Operations
Figure 12:
Example: Meeting tRCD (tRRD) MIN When 2 < tRCD (tRRD) MIN
T0
T1
ACT
NOP
T2
T3
T4
T5
T6
T7
NOP
NOP
RD/WR
NOP
CK#
CK
Command
A0–A12
BA0, BA1
NOP
Row
ACT
Row
Bank x
Col
Bank y
tRRD
Bank y
tRCD
Don’t Care
READs
READ burst operations are initiated with a READ command, as shown in Figure 13 on
page 28.
The starting column and bank addresses are provided with the READ command, and
auto precharge is either enabled or disabled for that burst access. If auto precharge is
enabled, the row being accessed is precharged at the completion of the burst. For the
READ commands used in the following illustrations, auto precharge is disabled.
During READ bursts, the valid data-out element from the starting column address will
be available following the CAS latency after the READ command. Each subsequent dataout element will be valid nominally at the next positive or negative clock edge (for
example, at the next crossing of CK and CK#). Figure 14 on page 29 shows general timing
for different CAS latency settings. DQS is driven by the Mobile DDR SDRAM along with
output data. The initial LOW state on DQS is known as the read preamble; the LOW state
coincident with the last data-out element is known as the read postamble.
Upon completion of a burst, assuming no other commands have been initiated, the DQ
will go High-Z. A detailed explanation of tDQSQ (valid data-out skew), tQH (data-out
window hold), and the valid data window is depicted in Figure 37 on page 66. A detailed
explanation of tDQSCK (DQS transition skew to CK) and tAC (data-out transition skew to
CK) is depicted in Figure 39 on page 68.
Data from any READ burst may be concatenated with or truncated with data from a
subsequent READ command. In either case, a continuous flow of data can be maintained. The first data element from the new burst either follows the last element of a
completed burst or the last desired data element of a longer burst that is being truncated. The new READ command should be issued x cycles after the first READ
command, where x equals the number of desired data element pairs (pairs are required
by the 2n-prefetch architecture). This is shown in Figure 15 on page 30. A READ
command can be initiated on any clock cycle following a previous READ command.
Nonconsecutive read data is illustrated in Figure 16 on page 31. Full-speed random read
accesses within a page (or pages) can be performed, as shown in Figure 17 on page 32.
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©2005 Micron Technology, Inc. All rights reserved.
256Mb: x16, x32 Mobile DDR SDRAM
Operations
Figure 13:
READ Command
CK#
CK
CKE
HIGH
CS#
RAS#
CAS#
WE#
A0–A8
CA
A9, A11, A12
EN AP
A10
DIS AP
BA0,1
BA
Don’t Care
Notes:
1.
2.
3.
4.
5.
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CA = column address
BA = bank address
EN AP = enable auto precharge
DIS AP = disable auto precharge
x16 DQ configuration example
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256Mb: x16, x32 Mobile DDR SDRAM
Operations
Figure 14:
READ Burst
T0
T1
READ
NOP
T1n
T2
T2n
T3
T3n
T4
T5
NOP
NOP
T4
T5
NOP
NOP
CK#
CK
Command
Address
NOP
NOP
Bank a,
Col n
CL = 2
DQS
DQ
DOUT
n
DOUT
n+1
DOUT
n+2
DOUT
n+3
T2n
T3
T3n
T0
T1
T2
READ
NOP
NOP
CK#
CK
Commmand
Address
NOP
Bank a,
Col n
CL = 3
DQS
DOUT
n
DQ
DOUT
n+1
DOUT
n+2
Transitioning data
Notes:
DOUT
n+3
Don’t Care
1. DOUT n = data-out from column n.
2. BL = 4.
3. Shown with nominal tAC, tDQSCK, and tDQSQ.
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256Mb: x16, x32 Mobile DDR SDRAM
Operations
Figure 15:
Consecutive READ Bursts
T0
T1
Command
READ
NOP
Address
Bank,
Col n
T1n
T2
T2n
T3
T3n
T4
T4n
T5
T5n
CK#
CK
READ
NOP
NOP
NOP
Bank,
Col b
CL = 2
DQS
DQ
DOUT
n
DOUT
n+1
DOUT
n+2
DOUT
n+3
DOUT
b
DOUT
b+1
DOUT
b+2
T2n
T3
T3n
T4
T4n
T5
T0
T1
T2
Command
READ
NOP
READ
Address
Bank,
Col n
DOUT
b+3
T5n
CK#
CK
NOP
NOP
NOP
Bank,
Col b
CL = 3
DQS
DOUT
n
DQ
DOUT
n+1
DOUT
n+2
Transitioning data
Notes:
1.
2.
3.
4.
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DOUT
n+3
DOUT
b
DOUT
b+1
Don’t Care
DOUT n (or b) = data-out from column n (or column b).
BL = 4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first).
Shown with nominal tAC, tDQSCK, and tDQSQ.
Example applies only when READ commands are issued to the same device.
30
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256Mb: x16, x32 Mobile DDR SDRAM
Operations
Figure 16:
Nonconsecutive READ Bursts
T0
T1
Command
READ
NOP
Address
Bank,
Col n
T1n
T2
T2n
T3
T3n
T4
T4n
T5
T5n
T6
CK#
CK
NOP
READ
NOP
NOP
NOP
Bank,
Col b
CL = 2
CL = 2
DQS
DQ
T0
T1
Command
READ
NOP
Address
Bank,
Col n
T1n
DOUT
n
DOUT
n+1
DOUT
n+2
DOUT
n+3
T2
T2n
T3
T3n
DOUT
b
T4
T4n
T5
DOUT
b+1
T5n
DOUT
b+2
T6
CK#
CK
NOP
READ
NOP
NOP
NOP
Bank,
Col b
CL = 3
CL = 3
DQS
DOUT
n
DQ
DOUT
n+1
DOUT
n+2
DOUT
n+3
Transitioning data
Notes:
1.
2.
3.
4.
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DOUT
b
Don’t Care
DOUT n (or b) = data-out from column n (or column b).
BL = 4 or 8 (if burst is 8, the second burst interrupts the first).
Shown with nominal tAC, tDQSCK, and tDQSQ.
Example applies when READ commands are issued to different devices or nonconsecutive
READs.
31
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256Mb: x16, x32 Mobile DDR SDRAM
Operations
Figure 17:
Random READ Accesses
T1n
T0
T1
T2
T2n
T3
Command
READ
READ
READ
READ
Address
Bank,
Col n
Bank,
Col x
Bank,
Col b
Bank,
Col g
T3n
T4
T4n
T5
T5n
CK#
CK
NOP
NOP
CL = 2
DQS
DOUT
n
DQ
T1n
T2
DOUT
n+1
T2n
DOUT
x
DOUT
x+1
DOUT
b
DOUT
b+1
DOUT
g
T3
T3n
T4
T4n
T5
T0
T1
Command
READ
READ
READ
READ
Address
Bank,
Col n
Bank,
Col x
Bank,
Col b
Bank,
Col g
DOUT
g+1
T5n
CK#
CK
NOP
NOP
CL = 3
DQS
DOUT
n
DQ
DOUT
n+1
DOUT
x
Transitioning data
Notes:
1.
2.
3.
4.
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MT46H16M16LF__2.fm - Rev. H 6/08 EN
DOUT
x+1
DOUT
b
DOUT
b+1
Don’t Care
DOUT n (or x, b, g) = data-out from column n (column x, column b, column g).
BL = 2, 4, or 8 (if 4 or 8, the following burst interrupts the previous).
READs are to an active row in any bank.
Shown with nominal tAC, tDQSCK, and tDQSQ.
32
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256Mb: x16, x32 Mobile DDR SDRAM
Operations
Truncated READs
Data from any non-auto precharge READ burst may be truncated with a BURST TERMINATE command, as shown in Figure 18. The BURST TERMINATE latency is equal to the
READ (CAS) latency; for example, the BURST TERMINATE command should be issued x
cycles after the READ command, where x equals the number of desired data element
pairs (pairs are required by the 2n-prefetch architecture).
Data from any non-auto precharge READ burst must be completed or truncated before a
subsequent WRITE command can be issued. If truncation is necessary, the BURST
TERMINATE command must be used, as shown in Figure 18. The tDQSS (MIN) case is
shown; the tDQSS (MAX) case has a longer bus idle time. (tDQSS [MIN] and tDQSS
[MAX] are defined in the section on WRITEs.)
A READ burst may be followed by, or truncated with, a PRECHARGE command to the
same bank provided that auto precharge was not activated. The PRECHARGE command
should be issued x cycles after the READ command, where x equals the number of
desired data element pairs (pairs are required by the n-prefetch architecture). This is
shown in Figure 20 on page 35. Following the PRECHARGE command, a subsequent
command to the same bank cannot be issued until tRP is met.
Note:
Figure 18:
Part of the row precharge time is hidden during the access of the last data elements.
Terminating a READ Burst
T0
T1
T1n
T2
T2n
T3
T4
T5
NOP
NOP
NOP
T4
T5
NOP
NOP
CK#
CK
Command
READ
Address
Bank a,
Col n
BST4
NOP
CL = 2
DQS
DOUT
n
DQ
T0
T1
T2
BST4
NOP
DOUT
n+1
T2n
T3
T3n
CK#
CK
Command
READ
Address
Bank a,
Col n
NOP
CL = 3
DQS
DOUT
n
DQ
DOUT
n+1
Transitioning data
Notes:
1.
2.
3.
4.
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MT46H16M16LF__2.fm - Rev. H 6/08 EN
Don’t Care
DOUT n = data-out from column n.
BL = 4 or 8.
Shown with nominal tAC, tDQSCK, and tDQSQ.
BST = BURST TERMINATE command; page remains open.
33
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256Mb: x16, x32 Mobile DDR SDRAM
Operations
5. CKE = HIGH.
Figure 19:
READ-to-WRITE
T0
T1
Command
READ
BST5
Address
Bank,
Col n
T1n
T2
T2n
T3
T3n
T4
T4n
T5
T5n
CK#
CK
NOP
WRITE
NOP
NOP
Bank,
Col b
tDQSS (NOM)
CL = 2
DQS
DQ
DOUT
n
DOUT
n+1
T2n
DIN
b
DIN
b+1
DIN
b+2
DIN
b+3
T4
T4n
T5
T5n
DM
T0
T1
T2
Command
READ
BST5
NOP
Address
Bank,
Col n
T3
T3n
CK#
CK
NOP
WRITE
NOP
Bank,
Col b
tDQSS (NOM)
CL = 3
DQS
DOUT
n
DQ
DOUT
n+1
DIN
b
DIN
b+1
DM
Transitioning data
Notes:
Don’t Care
1. DOUT n = data-out from column n.
2. DIN b = data-in from column b.
3. BL = 4 in the cases shown (applies for bursts of 8 as well; if BL = 2, the BST command shown
can be a NOP).
4. Shown with nominal tAC, tDQSCK, and tDQSQ.
5. BST = BURST TERMINATE command; page remains open.
6. CKE = HIGH.
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256Mb: x16, x32 Mobile DDR SDRAM
Operations
Figure 20:
READ-to-PRECHARGE
T0
T1
Command5
READ
NOP
Address
Bank a,
Col n
T1n
T2
T2n
T3
T3n
T4
T5
CK#
CK
PRE
NOP
NOP
ACT
Bank a,
(a or all)
Bank a,
Row
tRP
CL = 2
DQS
DQ
T0
T1
Command5
READ
NOP
Address
Bank a,
Col n
T1n
DOUT
n
DOUT
n+1
DOUT
n+2
DOUT
n+3
T2
T2n
T3
T3n
T4
T5
NOP
ACT
CK#
CK
PRE
NOP
Bank a,
(a or all)
Bank a,
Row
tRP
CL = 3
DQS
DOUT
n
DQ
DOUT
n+1
DOUT
n+2
Transitioning data
Notes:
DOUT
n+3
Don’t Care
1.
2.
3.
4.
5.
DOUT n = data-out from column n.
BL = 4 or an interrupted burst of 8.
Shown with nominal tAC, tDQSCK, and tDQSQ.
READ-to-PRECHARGE equals 2 clock cycles, which allows 2 data pairs of data-out.
A READ command with auto precharge enabled, provided tRAS (MIN) is met, would cause a
precharge to be performed at x number of clock cycles after the READ command, where x =
BL/2.
6. PRE = PRECHARGE command; ACT = ACTIVE command.
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256Mb: x16, x32 Mobile DDR SDRAM
Operations
WRITEs
WRITE bursts are initiated with a WRITE command, as shown in Figure 21 on page 37.
The starting column and bank addresses are provided with the WRITE command, and
auto precharge is either enabled or disabled for that access. If auto precharge is enabled,
the row being accessed is precharged at the completion of the burst. For the WRITE
commands used in the following illustrations, auto precharge is disabled.
During WRITE bursts, the first valid data-in element will be registered on the first rising
edge of DQS following the WRITE command, and subsequent data elements will be
registered on successive edges of DQS. The LOW state on DQS between the WRITE
command and the first rising edge is known as the write preamble; the LOW state on
DQS following the last data-in element is known as the write postamble.
The time between the WRITE command and the first corresponding rising edge of DQS
(tDQSS) is specified with a relatively wide range (from 75 percent to 125 percent of one
clock cycle). All the WRITE diagrams show the nominal case, and where the two extreme
cases (for example, tDQSS [MIN] and tDQSS [MAX]) might not be intuitive, they have
also been included. Figure 22 on page 38 shows the nominal case and the extremes of
tDQSS for a burst of 4. Upon completion of a burst, assuming no other commands have
been initiated, the DQ will remain High-Z, and any additional input data will be ignored.
Data for any WRITE burst may be concatenated with or truncated with a subsequent
WRITE command. In either case, a continuous flow of input data can be maintained.
The new WRITE command can be issued on any positive edge of clock following the
previous WRITE command. The first data element from the new burst is applied either
after the last element of a completed burst or the last desired data element of a longer
burst that is being truncated. The new WRITE command should be issued x cycles after
the first WRITE command, where x equals the number of desired data element pairs
(pairs are required by the 2n-prefetch architecture).
Figure 23 on page 39 shows concatenated bursts of 4. An example of nonconsecutive
WRITEs is shown in Figure 24 on page 39. Full-speed random write accesses within a
page or pages can be performed, as shown in Figure 25 on page 40.
Data for any WRITE burst may be followed by a subsequent READ command. To follow
a WRITE without truncating the WRITE burst, tWTR should be met, as shown in
Figure 26 on page 41.
Data for any WRITE burst may be truncated by a subsequent READ command, as shown
in Figure 27 on page 42. Note that only the data-in pairs that are registered prior to the
t
WTR period are written to the internal array, and any subsequent data-in should be
masked with DM, as shown in Figure 28 on page 43.
Data for any WRITE burst may be followed by a subsequent PRECHARGE command. To
follow a WRITE without truncating the WRITE burst, tWR should be met, as shown in
Figure 29 on page 44. At least one clock cycle is required during tWR time when in autoprecharge mode.
Data for any WRITE burst may be truncated by a subsequent PRECHARGE command, as
shown in Figure 30 on page 45 and Figure 31 on page 46. Note that only the data-in pairs
that are registered prior to the tWR period are written to the internal array, and any
subsequent data-in should be masked with DM, as shown in Figures 30 and 31. After the
PRECHARGE command, a subsequent command to the same bank cannot be issued
until tRP is met.
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©2005 Micron Technology, Inc. All rights reserved.
256Mb: x16, x32 Mobile DDR SDRAM
Operations
Figure 21:
WRITE Command
CK#
CK
CKE
HIGH
CS#
RAS#
CAS#
WE#
A0–A9
CA
A11, A12
EN AP
A10
DIS AP
BA0, BA1
BA
Don’t Care
Notes:
1.
2.
3.
4.
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MT46H16M16LF__2.fm - Rev. H 6/08 EN
CA = column address.
BA = bank address.
EN AP = enable auto precharge.
DIS AP = disable auto precharge.
37
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©2005 Micron Technology, Inc. All rights reserved.
256Mb: x16, x32 Mobile DDR SDRAM
Operations
Figure 22:
WRITE Burst
T0
T1
T2
T2n
Command
WRITE
NOP
NOP
Address
Bank a,
Col b
T3
CK#
CK
tDQSS (NOM)
NOP
tDQSS
DQS
DIN
b
DQ
DIN
b+1
DIN
b+2
DIN
b+3
DM
tDQSS (MIN)
tDQSS
DQS
DIN
b
DQ
DIN
b+1
DIN
b+2
DIN
b+3
DIN
b
DIN
b+1
DIN
b+2
DM
tDQSS (MAX)
tDQSS
DQS
DQ
DIN
b+3
DM
Transitioning data
Notes:
Don’t Care
1. DIN b = data-in for column b.
2. An uninterrupted burst of 4 is shown.
3. A10 is LOW with the WRITE command (auto precharge is disabled).
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Operations
Figure 23:
Consecutive WRITE-to-WRITE
T0
T1
Command
WRITE
NOP
Address
Bank,
Col b
T1n
T2
T2n
T3
T3n
T4
T4n
T5
CK#
CK
tDQSS (NOM)
WRITE
NOP
NOP
NOP
Bank,
Col n
tDQSS
DQS
DIN
b
DQ
DIN
b+1
DIN
b+2
DIN
b+3
DIN
n
DIN
n+1
DIN
n+2
DIN
n+3
DM
Transitioning data
Notes:
Figure 24:
Don’t Care
1. DIN b (n) = data-in for column b (n).
2. An uninterrupted burst of 4 is shown.
3. Each WRITE command may be to any bank.
Nonconsecutive WRITE-to-WRITE
T0
T1
Command
WRITE
NOP
Address
Bank,
Col b
T1n
T2
T2n
T3
T4
T4n
T5
T5n
CK#
CK
tDQSS (NOM)
NOP
WRITE
NOP
NOP
Bank,
Col n
tDQSS
DQS
DIN
b
DQ
DIN
b+1
DIN
b+2
DIN
b+3
DIN
n
DIN
n+1
DIN
n+2
DIN
n+3
DM
Transitioning data
Notes:
Don’t Care
1. DIN b (n) = data-in for column b (n).
2. An uninterrupted burst of 4 is shown.
3. Each WRITE command may be to any bank.
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Operations
Figure 25:
Random WRITE Cycles
T0
T1
T1n
T2
T2n
T3
T3n
T4
Command
WRITE
WRITE
WRITE
WRITE
WRITE
Address
Bank,
Col b
Bank,
Col x
Bank,
Col n
Bank,
Col a
Bank,
Col g
T4n
T5
T5n
CK#
CK
NOP
tDQSS (NOM)
DQS
DIN
b
DQ
DIN
b'
DIN
x
DIN
x'
DIN
n
DIN
n'
DIN
a
DIN
a'
DIN
g
DIN
g'
DM
Transitioning data
Notes:
Don’t Care
1. DIN b (or x, n, a, g) = data-in for column b (or x, n, a, g).
2. b' (or x', n', a', g') = the next data-in following DIN b (x, n, a, g), according to the programmed burst order.
3. Programmed BL = 2, 4, or 8 in cases shown.
4. Each WRITE command may be to any bank.
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Operations
Figure 26:
WRITE-to-READ – Uninterrupting
T0
T1
WRITE
NOP
T1n
T2
T2n
T3
T4
T5
READ
NOP
T5n
T6
T6n
CK#
CK
Command
NOP
NOP
NOP
tWTR
Address
Bank a,
Col b
tDQSS (NOM)
Bank a,
Col n
tDQSS
CL = 2
DQS
DIN
b
DQ
DIN
b+1
DIN
b+2
DIN
b+3
DOUT
n
DOUT
n+1
DOUT
n
DOUT
n+1
DOUT
n
DOUT
n+1
DM
tDQSS (MIN)
tDQSS
CL = 2
DQS
DIN
b
DQ
DIN
b+1
DIN
b+2
DIN
b+3
DM
tDQSS (MAX)
tDQSS
CL = 2
DQS
DIN
b
DQ
DIN
b+1
DIN
b+2
DIN
b+3
DM
Transitioning data
Notes:
Don’t Care
1.
2.
3.
4.
DIN b = data-in for column b; DOUT n = data-out for column n.
An uninterrupted burst of 4 is shown.
t
WTR is referenced from the first positive CK edge after the last data-in pair.
The READ and WRITE commands are to the same bank. However, the READ and WRITE
commands can be directed to different banks in which case tWTR is not required, and the
READ command could be applied earlier.
5. A10 is LOW with the WRITE command (auto precharge is disabled).
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Operations
Figure 27:
WRITE-to-READ – Interrupting
T0
T1
T1n
WRITE
NOP
T2
T2n
T3
T4
T5
NOP
NOP
T5n
T6
T6n
CK#
CK
Command
NOP
READ
NOP
tWTR
Address
Bank a,
Col b
tDQSS (NOM)
Bank a,
Col n
tDQSS
CL = 3
DQS
DIN
b+1
DIN
b
DQ
DOUT
n
DOUT
n+1
DM
tDQSS (MIN)
tDQSS
CL = 3
DQS
DIN
b
DQ
DIN
b+1
DOUT
n
DOUT
n+1
DM
tDQSS (MAX)
tDQSS
CL = 3
DQS
DIN
b
DQ
DIN
b+1
DOUT
n
DOUT
n+1
DM
Transitioning data
Notes:
1.
2.
3.
4.
5.
6.
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MT46H16M16LF__2.fm - Rev. H 6/08 EN
Don’t Care
DIN b = data-in for column b; DOUT n = data-out for column n.
An interrupted burst of 4 is shown; two data elements are written.
t
WTR is referenced from the first positive CK edge after the last data-in pair.
A10 is LOW with the WRITE command (auto precharge is disabled).
DQS is required at T2 and T2n (nominal case) to register DM.
If the burst of 8 was used, DM and DQS would be required at T3 and T3n because the READ
command would not mask these two data elements.
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Operations
Figure 28:
WRITE-to-READ – Odd Number of Data, Interrupting
T0
T1
WRITE
NOP
T1n
T2
T2n
T3
T4
T5
NOP
NOP
T5n
T6
T6n
CK#
CK
Command
NOP
READ
NOP
tWTR
Bank a,
Col b
Address
tDQSS (NOM)
Bank a,
Col n
tDQSS
CL = 3
DQS
DIN
b
DQ
DOUT
n
DOUT
n+1
DM
tDQSS (MIN)
tDQSS
CL = 3
DQS
DIN
b
DQ
DOUT
n
DOUT
n+1
DM
tDQSS (MAX)
tDQSS
CL = 3
DQS
DIN
b
DQ
DOUT
n
DOUT
n+1
DM
Transitioning data
Notes:
1.
2.
3.
4.
5.
6.
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MT46H16M16LF__2.fm - Rev. H 6/08 EN
Don’t Care
DIN b = data-in for column b; DOUT n = data-out for column n.
An interrupted burst of 4 is shown; one data element is written, and three are masked.
t
WTR is referenced from the first positive CK edge after the last data-in.
A10 is LOW with the WRITE command (auto precharge is disabled).
DQS is required at T2 and T2n (nominal case) to register DM.
If the burst of 8 was used, DM and DQS would be required at T3 and T3n because the READ
command would not mask these two data elements.
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Operations
Figure 29:
WRITE-to-PRECHARGE – Uninterrupting
T0
T1
WRITE
NOP
T1n
T2
T2n
T3
T4
T5
T6
NOP
NOP
PRE 6
NOP
CK#
CK
Command
NOP
tWR
Address
Bank a,
Col b
tDQSS (NOM)
Bank
(a or all)
tDQSS
DQS
DIN
b+1
DIN
b
DQ
DIN
b+2
DIN
b+3
DM
tDQSS (MIN)
tDQSS
DQS
DIN
b
DQ
DIN
b+1
DIN
b+2
DIN
b+3
DIN
b
DIN
b+1
DIN
b+2
DM
tDQSS (MAX)
tDQSS
DQS
DQ
DIN
b+3
DM
Transitioning data
Notes:
Don’t Care
1.
2.
3.
4.
DIN b = data-in for column b.
An uninterrupted burst of 4 is shown.
tWR is referenced from the first positive CK edge after the last data-in pair.
The PRECHARGE and WRITE commands are to the same bank. However, the PRECHARGE
and WRITE commands may be to different banks in which case tWR is not required, and the
PRECHARGE command could be applied earlier.
5. A10 is LOW with the WRITE command (auto precharge is disabled).
6. PRE = PRECHARGE command.
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Operations
Figure 30:
WRITE-to-PRECHARGE – Interrupting
CK#
T0
T1
T1n
WRITE
NOP
T2
T2n
T3
T3n
T4
T4n
T5
T6
NOP
NOP
CK
Command
NOP
NOP
PRE 5
tWR
Bank a,
Col b
Address
tDQSS
(NOM)
Bank
(a or all)
tDQSS
DQS
DIN
b+1
DIN
b
DQ
DM
tDQSS
tDQSS
(MIN)
DQS
DIN
b
DQ
DIN
b+1
DM
tDQSS
(MAX)
tDQSS
DQS
DIN
b
DQ
DIN
b+1
DM
Transitioning data
Notes:
1.
2.
3.
4.
5.
6.
7.
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MT46H16M16LF__2.fm - Rev. H 6/08 EN
Don’t Care
DIN b = data-in for column b.
An interrupted burst of 8 is shown; two data elements are written.
t
WR is referenced from the first positive CK edge after the last data-in pair.
A10 is LOW with the WRITE command (auto precharge is disabled).
PRE = PRECHARGE command.
DQS is required at T4 and T4n (nominal case) to register DM.
If a burst of 4 is used, DQS and DM are not required at T3, T3n, T4, and T4n.
45
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Operations
Figure 31:
WRITE-to-PRECHARGE – Odd Number of Data, Interrupting
CK#
T0
T1
WRITE
NOP
T1n
T2
T2n
T3
T3n
T4
T4n
T5
T6
NOP
NOP
CK
Command
NOP
NOP
PRE
5
tWR2
Address
tDQSS (NOM)
Bank a,
Col b
Bank
(a or all)
tDQSS
DQS
DIN
b
DQ
DM
tDQSS (MIN)
tDQSS
DQS
DIN
b
DQ
DM
tDQSS (MAX)
tDQSS
DQS
DIN
b
DQ
DM
Transitioning data
Notes:
1.
2.
3.
4.
5.
6.
7.
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MT46H16M16LF__2.fm - Rev. H 6/08 EN
Don’t Care
DIN b = data-in for column b.
An interrupted burst of 8 is shown.
t
WR is referenced from the first positive CK edge after the last data-in pair.
A10 is LOW with the WRITE command (auto precharge is disabled).
PRE = PRECHARGE command.
DQS is required at T4 and T4n to register DM.
If the burst of 4 is used, DQS and DM are not required at T3, T3n, T4, and T4n.
46
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Operations
PRECHARGE
The PRECHARGE command (Figure 32) is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent
row access some specified time (tRP) after the PRECHARGE command is issued. Input
A10 determines whether one or all banks are to be precharged. In the case where only
one bank is to be precharged (A10 = LOW), inputs BA0–BA1 select the bank. When all
banks are to be precharged (A10 = HIGH), inputs BA0–BA1 are treated as a “Don’t Care.”
After a bank has been precharged, it is in the idle state and must be activated prior to any
READ or WRITE commands being issued to that bank.
Figure 32:
PRECHARGE Command
CK#
CK
CKE
HIGH
CS#
RAS#
CAS#
WE#
A0–A9,
A11–Ai
All
A10
Single
BA0, BA1
BA
Don’t Care
Notes:
1.
2.
3.
4.
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MT46H16M16LF__2.fm - Rev. H 6/08 EN
BA = bank address.
A10 = 1 HIGH, all banks to be precharged, BA1, BA0 are “Don’t Care.”
A10 = 0 LOW, only bank selected by BA1 and BA0 will be precharged.
i = the most significant column address bit for each configuration.
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Operations
Power-Down
Power-down (Figure 42 on page 70) is entered when CKE is registered LOW. If powerdown occurs when all banks are idle, this mode is referred to as precharge power-down;
if power-down occurs when there is a row active in any bank, this mode is referred to as
active power-down. Entering power-down deactivates all input and output buffers,
including CK and CK# and excluding CKE. Exiting power-down requires the device to be
at the same voltage as when it entered power-down and received a stable clock.
Note:
The power-down duration is limited by the refresh requirements of the device.
While in power-down, CKE LOW must be maintained at the inputs of the Mobile DDR
SDRAM, while all other input signals are “Don’t Care.” The power-down state is exited
when CKE is registered HIGH (in conjunction with a NOP or DESELECT command). A
NOP or DESELECT command must be maintained on the command bus until tXP is
satisfied.
Figure 33:
Power-Down Command (in Active or Precharge Modes)
CK#
CK
CKE
CS#
RAS#, CAS#, WE#
Or
CS#
RAS#, CAS#, WE#
A0–A12
BA0–BA1
BA0,1
Don’t Care
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Operations
Deep Power-Down (DPD)
Deep power-down is an operating mode used to achieve maximum power reduction by
eliminating the power of the memory array. Data will not be retained when the device
enters deep power-down mode.
Before entering DPD mode, the DRAM must be in all banks idle state with no activity on
the data bus (tRP time must be met). This mode is entered by holding CS# and WE# LOW
with RAS# and CAS# HIGH at the rising edge of the clock, while CKE is LOW. CKE must
be held LOW to maintain DPD mode. The clock must be stable prior to exiting DPD
mode. This mode is exited by asserting CKE HIGH with either a NOP or DESELECT
command present on the command bus. Upon exit from DPD mode, 200µs of valid
clocks either with a NOP or DESELECT command present on the command bus are
required, and a PRECHARGE ALL command and a full DRAM initialization sequence are
required.
Figure 34:
Deep Power-Down Command
CKE
CS#
RAS#
CAS#
WE#
A0–A12
BA0, BA1
Don’t Care
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Operations
Figure 35:
Deep Power-Down
T0
T1
CK#
Ta1
Ta2
Ta3
))
((
))
CK
tCKE
tIS
CKE
Cdommand
Ta01
T2 ( (
((
))
DPD2
NOP
All banks idle with no
activity on the data bus
T = 200µs
((
))
((
))
NOP
Enter deep power-down mode
Valid3
NOP
Exit deep power-down mode
Don’t Care
Notes:
1. Clock must be stable prior to CKE going HIGH.
2. DPD = deep power-down command.
3. Upon exit from deep power-down mode, a PRECHARGE ALL command must be issued,
followed by the initialization sequence (see page 14).
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Operations
Table 9:
Truth Table – CKE
Notes 1–5 apply to all commands in this table
CKEn - 1
CKEn
Current State
Commandn
L
L
L
L
L
L
L
L
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
Active power-down
Deep power-down
(Precharge) power-down
SELF REFRESH
Active power-down
Deep power-down
(Precharge) Power-down
SELF REFRESH
Bank(s) active
All banks idle
All banks idle
All banks idle
X
X
X
X
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
BURST TERMINATE
DESELECT or NOP
AUTO REFRESH
See Table 11 on page 54
Notes:
Actionn
Notes
Maintain active power-down
Maintain deep power-down
Maintain (precharge) power-down
Maintain SELF REFRESH
Exit active power-down
Exit deep power-down
Exit (precharge) power-down
Exit SELF REFRESH
Active power-down entry
Deep power-down entry
(Precharge) Power-down entry
SELF REFRESH entry
6, 7
10, 11
6, 7
8, 9
1. CKEn is the logic state of CKE at clock edge n; CKEn - 1 was the state of CKE at the previous
clock edge.
2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.
3. COMMANDn is the command registered at clock edge n; and ACTIONn is a result of COMMANDn.
4. All states and sequences not shown are illegal or reserved.
5. tCKE pertains.
6. DESELECT or NOP commands should be issued on any clock edges occurring during the tXP
period.
7. The clock must toggle at least one time during the tXP period.
8. DESELECT or NOP commands should be issued on any clock edges occurring during the tXSR
period.
9. The clock must toggle at least one time during the tXSR period.
10. 200µs of valid clocks and NOP (or DESELECT) commands are required before any other valid
command is allowed.
11. Upon exit from deep power-down mode and after the 200µs, a PRECHARGE ALL command
is required, followed by the standard initialization sequence.
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Operations
Table 10:
Truth Table – Current State Bank n – Command to Bank n
Notes 1–6 apply to all states listed in this table; notes appear below and on next page
Current State
Any
Idle
Row active
Read
(auto precharge
disabled)
Write
(auto precharge
disabled)
CS#
RAS#
CAS#
WE#
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
H
L
L
L
H
H
L
H
H
L
H
H
H
L
X
H
H
L
L
L
L
H
L
L
H
H
L
L
H
X
H
H
H
L
H
L
L
H
L
L
L
H
L
L
Notes:
Command (Action)
Notes
DESELECT (NOP/continue previous operation)
NO OPERATION (NOP/continue previous operation)
ACTIVE (select and activate row)
AUTO REFRESH
LOAD MODE REGISTER
READ (select column and start READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE (deactivate row in bank or banks)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE (truncate READ burst, start PRECHARGE)
BURST TERMINATE
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE (truncate WRITE burst, start PRECHARGE)
7
7
10
10
8
10
10, 12
8
9
10, 11
10
8, 11
1. This table applies when CKEn - 1 was HIGH and CKEn is HIGH and after tXSR has been met (if
the previous state was SELF REFRESH), after tXP has been met (if the previous state was
power-down), or 200µs if the previous state was DPD.
2. This table is bank-specific, except where noted (for example, the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in
that state). Exceptions are discussed in the notes below.
3. Current state definitions:
Idle:
Row active:
Read:
Write:
4.
The following states must not be interrupted by a command issued to the same
bank. COMMAND INHIBIT or NOP commands, or allowable commands to the other bank
should be issued on any clock edge occurring during these states. Allowable commands to
any other bank are determined by that bank’s current state.
Precharging:
Row activating:
Read with auto
precharge
enabled:
Write with auto
precharge
enabled:
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The bank has been precharged, and tRP has been met.
A row in the bank has been activated, and tRCD has been met. No data
bursts/accesses and no register accesses are in progress.
A READ burst has been initiated, with auto precharge disabled, and has
not yet terminated or been terminated.
A WRITE burst has been initiated, with auto precharge disabled, and has
not yet terminated or been terminated.
Starts with registration of a PRECHARGE command and ends when tRP
is met. When tRP is met, the bank will be in the idle state.
Starts with registration of an ACTIVE command and ends when tRCD is
met. When tRCD is met, the bank will be in the row active state.
Starts with registration of a READ command with auto precharge
enabled and ends when tRP has been met. When tRP is met, the bank
will be in the idle state.
Starts with registration of a WRITE command with auto precharge
enabled and ends whentRP has been met. WhentRP is met, the bank
will be in the idle state.
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Operations
5.
: The following states must not be interrupted by any executable command; DESELECT or NOP commands must be applied on each positive clock edge during these states.
Refreshing
Starts with registration of an AUTO REFRESH command and ends when
RFC is met. When tRFC is met, the Mobile DDR SDRAM will be in the all
banks idle state.
Starts with registration of a LOAD MODE REGISTER command and ends
when tMRD has been met. When tMRD is met, the Mobile DDR SDRAM
will be in the all banks idle state.
Starts with registration of a PRECHARGE ALL command and ends when
t
RP is met. When tRP is met, all banks will be in the idle state.
t
Accessing mode
register
Precharging
all:
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks be idle, and bursts not be in progress.
8. May or may not be bank-specific; if multiple banks are to be precharged, each must have an
open row.
9. Not bank-specific; BURST TERMINATE affects the most recent READ burst, regardless of
bank.
10. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with
auto precharge enabled and READs or WRITEs with auto precharge disabled.
11. Requires appropriate DM masking.
12. A WRITE command may be applied after the completion of the READ burst; otherwise, a
BURST TERMINATE must be used to end the READ burst prior to asserting a WRITE command.
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MT46H16M16LF__2.fm - Rev. H 6/08 EN
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256Mb: x16, x32 Mobile DDR SDRAM
Operations
Table 11:
Truth Table – Current State Bank n – Command to Bank m
Notes 1–6 apply to all states listed in this table; the other referenced notes appear below and on next page
Current State
Any
Idle
Row
activating,active,
or precharging
Read
(auto precharge
disabled)
Write
(auto precharge
disabled)
Read
(with auto
precharge)
Write
(with auto
precharge)
CS#
RAS#
CAS#
WE#
H
L
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
H
X
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
X
H
X
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
X
H
X
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
Notes:
Command (Action)
DESELECT (NOP/continue previous operation)
NO OPERATION (NOP/continue previous operation)
Any command otherwise allowed to bank m
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE
Notes
7
7
7
7, 9
7, 10
7
3a, 7
3a, 7
3a,7
3a,7
1. This table applies when CKEn - 1 was HIGH and CKEn is HIGH and after tXSR has been met (if
the previous state was SELF REFRESH) or after tXP has been met (if the previous state was
power-down) or 200µs if the previous state was deep power-down).
2. This table describes alternate bank operation, except where noted (for example, the current state is for bank n and the commands shown are those allowed to be issued to bank m,
assuming that bank m is in such a state that given command is allowable). Exceptions are
covered in the notes below.
3. Current state definitions:
The bank has been precharged, and tRP has been met.
Row active: A row in the bank has been activated, and tRCD has been met. No data
bursts/accesses and no register accesses are in progress.
Read:
A READ burst has been initiated, with auto precharge disabled, and has
not yet terminated or been terminated.
Write:
A WRITE burst has been initiated, with auto precharge disabled, and
has not yet terminated or been terminated.
Idle:
3a. The READ with auto precharge enabled or WRITE with auto precharge enabled states
can each be broken into two parts: the access period and the precharge period. For read
with auto precharge, the precharge period is defined as if the same burst were executed
with auto precharge disabled and then followed with the earliest possible PRECHARGE
command that still accesses all of the data in the burst. For write with auto precharge, the
precharge period begins when tWR ends, with tWR measured as if auto precharge were disabled. The access period starts with registration of the command and ends where the precharge period (or tRP) begins.
PDF: 09005aef82091978 / Source: 09005aef8209195b
MT46H16M16LF__2.fm - Rev. H 6/08 EN
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256Mb: x16, x32 Mobile DDR SDRAM
Operations
This device supports concurrent auto precharge such that when a read with auto precharge
is enabled or a write with auto precharge is enabled, any command to other banks is supported, as long as that command does not interrupt the read or write data transfer already
in process. In either case, all other related limitations apply (that is, contention between
read data and write data must be avoided).
3b. The minimum delay from a READ or WRITE command with auto precharge enabled to a
command to a different bank is summarized below.
Minimum Delay
(with Concurrent Auto Precharge)
From Command
To Command
WRITE
(with auto precharge)
READ or
READ (with auto precharge)
WRITE or
WRITE (with auto precharge)
PRECHARGE
ACTIVE
READ or
READ (with auto precharge)
WRITE or
WRITE (with auto precharge)
PRECHARGE
ACTIVE
READ
(with auto precharge)
[1 + (BL/2)] tCK + tWTR
(BL/2) tCK
1 tCK
1 tCK
(BL/2) × tCK
[CLRU + (BL/2)] tCK
1 tCK
1 tCK
CLRU = CAS latency (CL) rounded up to the next integer; BL = burst length
4. AUTO REFRESH and LOAD MODE REGISTER commands may only be issued when all banks
are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank
represented by the current state only.
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with
auto precharge enabled and READs or WRITEs with auto precharge disabled.
8. Requires appropriate DM masking.
9. A WRITE command may be applied after the completion of the READ burst; otherwise, a
BURST TERMINATE must be used to end the READ burst prior to asserting a WRITE command.
10. A READ command may be applied after the completion of the WRITE burst; otherwise, a
BURST TERMINATE must be used to end the WRITE burst prior to asserting a READ
command.
PDF: 09005aef82091978 / Source: 09005aef8209195b
MT46H16M16LF__2.fm - Rev. H 6/08 EN
55
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
256Mb: x16, x32 Mobile DDR SDRAM
Electrical Specifications
Electrical Specifications
Absolute Maximum Ratings
Stresses greater than those listed in Table 12 may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
Table 12:
Absolute Maximum Ratings
Symbol
VDD
VDDQ
VIN, VOUT
TSTG
Table 13:
Parameter
Min
Max
Unit
VDD supply voltage relative to VSS
VDDQ supply voltage relative to VSS
Voltage on any pin relative to VSS
Storage temperature
–0.3
–0.3
–0.3
–55
2.7
2.7
2.7
+150
V
V
V
°C
Electrical Characteristics and Operating Conditions
Notes 1–5 on pages 52 and 53 apply to all parameters in this table; see other indicated notes on pages 63–65
VDD/VDDQ = 1.70–1.95V
Parameter/Condition
Supply voltage
I/O supply voltage
Address and command inputs
Input HIGH voltage
Input LOW voltage
Clock inputs (CK, CK#)
DC input voltage
DC input differential voltage
AC input differential voltage
AC differential crossing voltage
Data inputs
DC input HIGH voltage
AC input HIGH voltage
DC input LOW voltage
AC input LOW voltage
Data outputs
DC output HIGH voltage: Logic 1 (IOH = –0.1mA)
DC output LOW voltage: Logic 0 (IOL = 0.1mA)
Leakage current
Input leakage current
Any input 0V ≤ VIN ≤ VDD
(All other pins not under test = 0V)
Output leakage current
(DQ are disabled; 0V ≤ VOUT ≤ VDDQ)
Operating temperature
Commercial
Industrial
PDF: 09005aef82091978 / Source: 09005aef8209195b
MT46H16M16LF__2.fm - Rev. H 6/08 EN
Symbol
Min
Max
Unit
Notes
VDD
VDDQ
1.70
1.70
1.95
1.95
V
V
26, 29
26, 29
VIH
VIL
0.8 × VDDQ
–0.3
VDDQ + 0.3
0.2 × VDDQ
V
V
21, 28
21, 28
VIN
VID(DC)
VID(AC)
VIX
–0.3
0.4 × VDDQ
0.6 × VDDQ
0.4 × VDDQ
VDDQ + 0.3
VDDQ + 0.6
VDDQ + 0.6
0.6 × VDDQ
V
V
V
V
22
7,22
7,22
8, 22
VIH(DC)
VIH(AC)
VIL(DC)
VIL(AC)
0.7 × VDDQ
0.8 × VDDQ
–0.3
–0.3
VDDQ + 0.3
VDDQ + 0.3
0.3 × VDDQ
0.2 × VDDQ
V
V
V
V
21, 23, 28
21, 23, 28
21, 23, 28
21, 23, 28
VOH
VOL
0.9 × VDDQ
–
–
0.1 × VDDQ
V
V
27
27
II
–1
1
µA
IOZ
–5
5
µA
TA
TA
0
–40
+70
+85
°C
°C
56
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256Mb: x16, x32 Mobile DDR SDRAM
Electrical Specifications
Table 14:
Capacitance (x16, x32)
Note 41 on page 65 applies to all parameters in this table; notes appear on pages 63–65
Parameter
Delta input/output capacitance: DQ, DQS, DM
Delta input capacitance: command and address
Delta input capacitance: CK, CK#
Input/output capacitance: DQ, DQS, DM
Input capacitance: command and address
Input capacitance: CK, CK#
Input capacitance: CS#, CKE
PDF: 09005aef82091978 / Source: 09005aef8209195b
MT46H16M16LF__2.fm - Rev. H 6/08 EN
Symbol
Min
Max
Units
Notes
DCIO
DCCI1
DCI2
CIO
CI1
CI2
CI3
–
–
–
2.0
1.5
1.5
1.5
0.50
0.50
0.25
4.5
3.0
3.5
3.0
pF
pF
pF
pF
pF
pF
pF
17
57
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256Mb: x16, x32 Mobile DDR SDRAM
Electrical Specifications
Table 15:
IDD Specifications and Conditions (x16)
Notes: 1–5, 9, 11 apply to all parameters in this table; notes appear on pages 63–65; VDD/VDDQ = 1.70–1.95V
Max
Parameter/Condition
Symbol
-6
-75
Units
Notes
IDD0
Operating one bank active-precharge
RFC = RFC (MIN);
t
CK = tCK (MIN); CKE = HIGH; CS = HIGH between valid commands;
Address inputs are switching every two clock cycles; Data bus inputs are
stable
IDD2P
Precharge power-down standby current: All banks idle; CKE is
Standard
LOW; CS is HIGH, tCK = tCK (MIN); Address and control inputs are
switching; Data bus inputs are stable
IDD2P
Low
power
IDD2PS
Precharge power-down standby current with clock stopped: All
banks idle; CKE is LOW; CS is HIGH, CK = LOW, CK# = HIGH; Address and Standard
control inputs are switching; Data bus inputs are stable
60
55
mA
16
300
300
µA
36
220
220
300
300
220
220
IDD2N
25
20
mA
IDD2NS
5
5
mA
IDD3P
5
5
mA
IDD3PS
3
3
mA
IDD3N
25
20
mA
16
IDD3NS
10
10
mA
16
IDD4R
100
95
mA
16
IDD4W
100
100
mA
16
IDD5
65
60
mA
IDD5a
IDD8
3
10
3
10
mA
µA
current:t
t
IDD2PS
36
µA
36
36
Low
power
Precharge non-power-down standby current: All banks idle; CKE =
HIGH; CS = HIGH; tCK = tCK (MIN); Address and control inputs are
switching; Data bus inputs are stable
Precharge non-power-down standby current with clock
stopped: All banks idle; CKE = HIGH; CS = HIGH; CK = LOW; CK# =
HIGH; Address and control inputs are switching; Data bus inputs are
stable
Active power-down standby current: One bank active; CKE = LOW;
CS = HIGH; tCK = tCK (MIN); Address and control inputs are switching;
Data bus inputs are stable
Active power-down standby current with clock stopped: One
bank active; CKE = LOW; CS = HIGH; CK = LOW; CK# = HIGH; Address
and control inputs are switching; Data bus inputs are stable
Active non-power-down standby current: One bank active;
CKE = HIGH; CS = HIGH; tCK = tCK (MIN); Address and control inputs are
switching; Data bus inputs are stable
Active non-power-down standby current with clock stopped:
One bank active; CKE = HIGH; CS = HIGH; CK = LOW; CK# = HIGH;
Address and control inputs are switching; Data bus inputs are stable
Operating burst read: One bank active; BL = 4; CL = 3; tCK = tCK
(MIN); Continuous read bursts; IOUT = 0mA; Address inputs are
switching every two clock cycles; 50 percent data changing each burst
Operating burst write: One bank active; BL = 4; tCK= tCK (MIN);
Continuous write bursts; Address inputs are switching; 50 percent data
changing each burst
tRFC = tRFC
Auto refresh current: Burst refresh; CKE = HIGH;
Address and control inputs are switching; Data bus
(MIN)
t
inputs are stable
RFC = tREFI
Deep power-down current: Address and control
inputs are stable; Data bus inputs are stable
PDF: 09005aef82091978 / Source: 09005aef8209195b
MT46H16M16LF__2.fm - Rev. H 6/08 EN
58
20
36, 38
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©2005 Micron Technology, Inc. All rights reserved.
256Mb: x16, x32 Mobile DDR SDRAM
Electrical Specifications
Table 16:
IDD Specifications and Conditions (x32)
Notes: 1–5, 9, 11 apply to all parameters in this table; notes appear on pages 63–65; VDD/VDDQ = 1.70–1.95V
Max
Parameter/Condition
Operating one bank active-precharge current: JEDEC-standard
t
RFC = tRFC (MIN); tCK = tCK (MIN); CKE = HIGH; CS = option
HIGH between valid commands; Address inputs are Reduced page-size
switching every two clock cycles; Data bus inputs
option
are stable
Precharge power-down standby current: All banks idle; CKE is LOW;
CS is HIGH, tCK = tCK (MIN); Address and control inputs are switching;
Data bus inputs are stable
Symbol
-6
-75
Units
Notes
IDD0
80
65
mA
16, 36
IDD0
70
55
mA
16, 35
IDD2P
300
300
µA
36
220
220
300
300
220
220
IDD2N
25
20
mA
IDD2NS
5
5
mA
IDD3P
5
5
mA
IDD3PS
3
3
mA
IDD3N
25
20
mA
16
IDD3NS
10
10
mA
16
IDD4R
135
115
mA
16
IDD4W
160
140
mA
16, 36
IDD4W
140
120
mA
16, 35
IDD5
IDD5a
65
3
60
3
mA
mA
20
IDD8
10
10
µA
36, 38
Standard
IDD2P
36
Low
power
Precharge power-down standby current with clock stopped: All
banks idle; CKE is LOW; CS is HIGH, CK = LOW, CK# = HIGH; Address and
control inputs are switching; Data bus inputs are stable
IDD2PS
µA
36
Standard
IDD2PS
36
Low
power
Precharge non-power-down standby current: All banks idle; CKE =
HIGH; CS = HIGH; tCK = tCK (MIN); Address and control inputs are
switching; Data bus inputs are stable
Precharge non-power-down standby current with clock stopped:
All banks idle; CKE = HIGH; CS = HIGH; CK = LOW; CK# = HIGH; Address
and control inputs are switching; Data bus inputs are stable
Active power-down standby current: One bank active; CKE = LOW;
CS = HIGH; tCK = tCK (MIN); Address and control inputs are switching;
Data bus inputs are stable
Active power-down standby current with clock stopped: One
bank active; CKE = LOW; CS = HIGH; CK = LOW; CK# = HIGH; Address and
control inputs are switching; Data bus inputs are stable
Active non-power-down standby current: One bank active; CKE =
HIGH; CS = HIGH; tCK = tCK (MIN); Address and control inputs are
switching; Data bus inputs are stable
Active non-power-down standby current with clock stopped: One
bank active; CKE = HIGH; CS = HIGH; CK = LOW; CK# = HIGH; Address and
control inputs are switching; Data bus inputs are stable
Operating burst read: One bank active; BL = 4; CL = 3; tCK = tCK (MIN);
IOUT = 0mA; Address inputs are switching every two clock cycles; 50
percent data changing each burst
Operating burst WRITE: One bank active; BL = 4; JEDEC-standard
tCK = tCK (MIN); Address inputs are switching; 50
option
percent data changing each burst
Reduced page-size
option
Auto refresh current: Burst refresh; CKE = HIGH; tRC = tRFC (MIN)
Address and control inputs are switching; Data bus tRC = tREFI
inputs are stable
Deep power-down current: Address and control inputs are stable;
Data bus inputs are stable
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MT46H16M16LF__2.fm - Rev. H 6/08 EN
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256Mb: x16, x32 Mobile DDR SDRAM
Electrical Specifications
IDD6 Specifications and Conditions (x16, x32)
Table 17:
Notes: 1–5, 9, 10, 36, and 39 apply to all parameters in this table; notes appear on pages 63–65;
VDD/VDDQ = 1.70–1.95V
Parameter/Condition
Symbol
Low IDD6
Option “L”
Standard IDD6
Option
Units
IDD6a
IDD6b
IDD6c
IDD6d
IDD6a
IDD6b
IDD6c
IDD6d
IDD6a
IDD6b
IDD6c
IDD6d
IDD6a
IDD6b
IDD6c
IDD6d
IDD6a
IDD6b
IDD6c
IDD6d
220
175
140
125
200
150
130
115
185
140
120
115
175
125
115
110
170
120
110
105
300
210
190
180
275
180
160
150
265
160
140
140
255
150
130
125
250
140
120
115
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
t
Self refresh current: CKE = LOW; CK Full array, 85°C
= tCK (MIN); Address and control inputs Full array, 70°C
are stable; Data bus input are stable
Full array, 45°C
Full array 15°C
Half array, 85°C
Half array, 70°C
Half array, 45°C
Half array, 15°C
1/4 array, 85°C
1/4 array, 70°C
1/4 array, 45°C
1/4 array, 15°C
1/8 array, 85°C
1/8 array, 70°C
1/8 array, 45°C
1/8 array, 15°C
1/16 array, 85°C
1/16 array, 70°C
1/16 array, 45°C
1/16 array, 15°C
Figure 36:
Typical Self Refresh Current vs. Temperature (x16, x32)
150
Full Array
Half Array
125
1/4 Array
Current (µA)
1/8 Array
1/16 Array
100
75
50
25
0
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
90
Temperature (°C)
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MT46H16M16LF__2.fm - Rev. H 6/08 EN
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256Mb: x16, x32 Mobile DDR SDRAM
Electrical Specifications
Table 18:
Electrical Characteristics and Recommended AC Operating Conditions
Notes: 1–6, 22 apply to all parameters in this table; notes appear on pages 63–65; VDD/VDDQ = 1.70–1.95V
-6
Parameter
Access window of DQ from CK/CK#
CK high-level width
CK low-level width
Clock cycle time
Symbol
CL = 3
CL = 2
CL = 3
CL = 2
Minimum tCKE HIGH/LOW time
Auto precharge write recovery + precharge time
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
CL = 3
Access window of DQS from CK/CK#
CL = 2
DQS input HIGH pulse width
DQS input LOW pulse width
DQS–DQ skew, DQS to last DQ valid, per group, per
access
WRITE command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Data valid output window (DVW)
Half clock period
Data-out High-Z window from CK/CK#
CL = 3
CL = 2
Data-out Low-Z window from CK/CK#
Address and control input hold time (fast slew rate)
Address and control input setup time (fast slew rate)
Address and control input hold time (slow slew rate)
Address and control input setup time (slow slew rate)
Address and control input pulse width
LOAD MODE REGISTER command cycle time
DQ–DQS hold, DQS to first DQ to go non-valid, per access
Data hold skew factor
ACTIVE-to-PRECHARGE command
ACTIVE-to-ACTIVE or ACTIVE-to-AUTO REFRESH
command period
ACTIVE-to-READ or WRITE delay
Refresh period
Average periodic refresh interval (x16)
Average periodic refresh interval (x32)
AUTO REFRESH command period
PRECHARGE command period
PDF: 09005aef82091978 / Source: 09005aef8209195b
MT46H16M16LF__2.fm - Rev. H 6/08 EN
t
AC(3)
AC(2)
t
CH
t
CL
t
CK(3)
t
CK(2)
t
CKE
tDAL
t
DH
tDS
tDIPW
tDQSCK(3)
tDQSCK(2)
tDQSH
tDQSL
tDQSQ
t
tDQSS
tDSS
tDSH
n/a
tHP
tHZ(3)
tHZ(2)
tLZ
tIH
F
tIS
F
tIH
S
tIS
S
t
IPW
tMRD
tQH
tQHS
tRAS
t
RC
tRCD
tREF
tREFI
t
REFI
tRFC
tRP
61
-75
Min
Max
Min
Max
Units
2.0
2.0
0.45
0.45
6
12
1
–
0.5
0.5
1.8
2.0
2.0
0.35
0.35
–
5.0
6.5
0.55
0.55
–
–
–
–
–
–
–
5.0
6.5
0.6
0.6
0.5
2.0
2.0
0.45
0.45
7.5
12
1
–
0.75
0.75
1.8
2.0
2.0
0.4
0.4
–
6.0
6.5
0.55
0.55
–
–
–
–
–
–
–
6.0
6.5
0.6
0.6
0.6
ns
0.75
1.25
0.75
1.25
0.2
–
0.2
–
0.2
–
0.2
–
tQH - tDQSQ
tQH - tDQSQ
tCH,
tCH,
–
–
tCL
tCL
–
5.0
–
6.0
–
6.5
–
6.5
1.0
–
1.0
–
1.1
–
1.3
–
1.1
–
1.3
–
1.2
–
1.5
–
1.2
–
1.5
–
2.6
–
2.6
–
2
–
2
–
tHP
tHP
–
–
- tQHS
- tQHS
0.65
–
0.75
42
70,000
45
70,000
60
–
75
–
18
–
–
–
70
18
–
64
7.8
15.6
–
–
22.5
–
–
–
70
22.5
–
64
7.8
15.6
–
–
Notes
t
CK
CK
ns
t
24
t
CK
ns
ns
ns
ns
32
19,23,31
19,23,31
33
tCK
tCK
ns
18, 19
tCK
tCK
tCK
ns
ns
18
24
ns
ns
ns
ns
ns
ns
ns
ns
tCK
ns
12, 30
12, 30
11
11
11
11
33
18, 19
ns
ns
ns
25
ns
ms
µs
µs
ns
ns
37
37
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256Mb: x16, x32 Mobile DDR SDRAM
Electrical Specifications
Table 18:
Electrical Characteristics and Recommended AC Operating Conditions (Continued)
Notes: 1–6, 22 apply to all parameters in this table; notes appear on pages 63–65; VDD/VDDQ = 1.70–1.95V
-6
Parameter
Symbol
DQS read preamble
t
DQS read postamble
ACTIVE bank a to ACTIVE bank b command
DQS write preamble
DQS write preamble setup time
DQS write postamble
WRITE recovery time
Internal WRITE to READ command delay
Exit power-down to first valid command
Exit SELF REFRESH to first valid command
PDF: 09005aef82091978 / Source: 09005aef8209195b
MT46H16M16LF__2.fm - Rev. H 6/08 EN
CL = 2
CL = 3
RPRE(2)
RPRE(3)
t
RPST
t
RRD
t
WPRE
t
WPRES
tWPST
tWR
tWTR
tXP
tXSR
t
62
Min
0.5
0.9
0.4
12
0.25
0
0.4
12
1
1
120
-75
Max
1.1
1.1
0.6
–
–
–
0.6
–
–
–
–
Min
0.5
0.9
0.4
15
0.25
0
0.4
15
1
1
120
Max
1.1
1.1
0.6
–
–
–
0.6
–
–
–
–
Units
Notes
t
CK
t
CK
ns
t
CK
ns
tCK
ns
tCK
tCK
ns
14, 15
13
40
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Notes
Notes
1. All voltages referenced to VSS.
2. All parameters assume proper device initialization.
3. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted
at nominal supply voltage levels, but the related specifications and device operation
are guaranteed for the full voltage range specified.
4. Outputs measured with equivalent load; transmission line delay is assumed to be very
small:
Z0 = 50
Z0 = 50
I/O
I/O
5pF
20pF
Full-drive strength
Quarter-drive strength
Z0 = 50
Z0 = 50
I/O
I/O
10pF
2.5pF
One-half-drive strength
One-eighth-drive strength
5. Timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment,
but input timing is still referenced to VDDQ/2 (or to the crossing point for CK/CK#).
The output timing reference voltage level is VDDQ/2.
6. All AC timings assume an input slew rate of 1V/ns.
7. VID is the magnitude of the difference between the input level on CK and the input
level on CK#.
8. The value of VIX is expected to equal VDDQ/2 of the transmitting device and must
track variations in the DC level of the same.
9. IDD is dependent on output loading and cycle rates. Specified values are obtained
with minimum cycle time at CL = 3 for -6 and CL = 3 for -75 with the outputs open.
10. Enables on-chip refresh and address counters.
11. Fast command/address input slew rate ≥1 V/ns. Slow command/address input slew
rate ≥0.5 V/ns. If the slew rate is less than 0.5 V/ns, timing must be derated: tIS has an
additional 50ps per each 100 mV/ns reduction in slew rate from the 0.5 V/ns. tIH
remains constant. If the slew rate exceeds 4.5 V/ns, functionality is uncertain.
12. tHZ and tLZ transitions occur in the same access time windows as data valid transitions. These parameters are not referenced to a specific voltage level but specify when
the device output is no longer driving (HZ) or begins driving (LZ).
13. The maximum limit for this parameter is not a device limit. The device will operate
with a greater value for this parameter, but system performance (bus turnaround) will
degrade accordingly.
14. This is not a device limit. The device will operate with a negative value, but system
performance (bus turnaround) will degrade accordingly.
15. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no
WRITEs were previously in progress on the bus. If a previous WRITE was in progress,
DQS could be HIGH during this time, depending on tDQSS.
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MT46H16M16LF__2.fm - Rev. H 6/08 EN
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Notes
16. MIN (tRC or tRFC) for IDD measurements is the smallest multiple of tCK that meets
the minimum absolute value for the respective parameter.
17. The I/O capacitance per DQS and DQ byte/group will not differ by more than this
maximum amount for any given device.
18. The data valid window is derived by achieving other specifications: tHP (tCK/2),
t
DQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates in direct proportion to the clock duty cycle, and a practical data valid window can be derived. The
clock is allowed a maximum duty cycle variation of 45/55. Functionality is uncertain
when operating beyond a 45/55 ratio.
19. Referenced to each output group: for x16, LDQS with DQ0–DQ7; and UDQS with
DQ8–DQ15. For x32, DQS0 with DQ0–DQ7; DQS1 with DQ8–DQ15; DQS2 with DQ16–
DQ23; and DQS3 with DQ24–DQ31.
20. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH
during REFRESH command period (tRFC [MIN]) else CKE is LOW (for example,
during standby).
21. To maintain a valid level, the transitioning edge of the input must:
a. Sustain a constant slew rate from the current AC level through to the target AC
level, VIL(AC) or VIH(AC).
b. Reach at least the target AC level.
c. After the AC target level is reached, continue to maintain at least the target DC
level, VIL(DC) or VIH(DC).
22. CK and CK# input slew rate must be ≥1 V/ns (2 V/ns if measured differentially).
23. DQ and DM input slew rates must not deviate from DQS by more than 10 percent. If
the DQ/DM/DQS slew rate is less than 0.5 V/ns, timing must be derated: 50ps must
be added to tDS and tDH for each 100 mV/ns reduction in slew rate. If slew rate
exceeds 4 V/ns, functionality is uncertain.
24. tHP (MIN) is the lesser of tCL minimum and tCH minimum actually applied to the
device CK and CK# inputs, collectively.
25. READs and WRITEs with auto precharge are not allowed to be issued until tRAS (MIN)
can be satisfied prior to the internal PRECHARGE command being issued.
26. Any positive glitch must be less than 1/3 of the clock cycle and not more than +200mV
or 2.0V, whichever is less. Any negative glitch must be less than 1/3 of the clock cycle
and not exceed either –150mV or 1.6V, whichever is more positive.
27. The voltage levels used are derived from a minimum VDD level and the referenced
test load. In practice, the voltage levels obtained from a properly terminated bus
will provide significantly different voltage values.
28. VIH overshoot: VIH (MAX) = VDDQ + 1.0V for a pulse width ≤3ns, and the pulse width
cannot be greater than 1/3 of the cycle rate. VIL undershoot: VIL (MIN) = –1.0V for a
pulse width ≤3ns, and the pulse width cannot be greater than 1/3 of the cycle rate.
29. VDD and VDDQ must track each other, and VDDQ must be less than or equal to VDD.
30. tHZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition.
31. The transition times for input signals (CAS#, CKE, CS#, DM, DQ, DQS, RAS#, WE#,
and addresses) are measured between VIL(DC) and VIH(AC) for rising input signals and
between VIH(DC) and VIL(AC) for falling input signals.
32. tDAL = (tWR/tCK) + (tRP/tCK): for each term, if not already an integer, round to the
next higher integer.
33. These parameters guarantee device timing, but are not tested on each device.
34. Clock must be toggled a minimum of two times during this period.
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MT46H16M16LF__2.fm - Rev. H 6/08 EN
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Notes
35. Reduced page-size option (A12). See page 1.
36. Current may be slightly higher for up to 500ms when entering this operating mode.
37. The maximum tREFI value applies to both A11 and A12 row size ordering options.
38. Deep power-down current is nominal value at 25°C. The parameter is not tested.
39. The values for IDD6 85°C are 100 percent tested. Values for 70°C, 45°C, and 15°C are
sampled only.
40. At least one clock cycle is required during tWR time when in auto-precharge mode.
41. This parameter is sampled. VDD/VDDQ = 1.70–1.95V, f = 100 MHz, TA = 25°C,
VOUT (DC) = VDDQ/2, VOUT (peak-to-peak) = 0.2V.
DM input is grouped with I/O pins, reflecting the fact that they are matched in loading.
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MT46H16M16LF__2.fm - Rev. H 6/08 EN
65
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Timing Diagrams
Timing Diagrams
Figure 37:
Data Output Timing – tDQSQ, tQH, and Data Valid Window (x16)
T1
CK#
CK
T2
tHP5
tHP5
T2n
T3
tHP5
tHP5
tDQSQ3
tDQSQ3
tQH4
tQH4
T3n
tHP5
T4
tHP5
tDQSQ3
tDQSQ3
LDQS1
tQH4
Lower Byte
DQ (Last data valid)2
DQ2
DQ2
DQ2
DQ2
DQ2
DQ2
DQ (First data no longer valid)2
tQH4
valid)2
T2
T2n
T3
T3n
DQ (First data no longer valid)2
T2
T2n
T3
T3n
DQ0–DQ7 and LDQS, collectively6
T2
T2n
T3
T3n
Data valid
window
Data valid
window
Data valid
window
DQ (Last data
Data valid
window
tDQSQ3
tDQSQ3
tDQSQ3
tDQSQ3
UDQS1
tQH4
tQH4
tQH4
Upper Byte
DQ (Last data valid)7
DQ7
DQ7
DQ7
DQ7
DQ7
DQ7
DQ (First data no longer valid)7
tQH4
DQ (Last data valid)7
T2
T2n
DQ (First data no longer valid)7
T2
T2n
DQ8–DQ15 and UDQS, collectively6
T2
T2n
T3
T3n
Data valid
window
Data valid
window
Data valid
window
Data valid
window
Notes:
T3
T3
T3n
T3n
1. DQ transitioning after DQS transitions defines the tDQSQ window. LDQS defines the lower
byte, and UDQS defines the upper byte.
2. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7.
3. tDQSQ is derived at each DQS clock edge and is not cumulative over time and begins with
DQS transition and ends with the last valid DQ transition.
4. tQH is derived from tHP: tQH = tHP - tQHS.
5. tHP is the lesser of tCL or tCH clock transition collectively when a bank is active.
6. The data valid window is derived for each DQS transition and is defined as tQH - tDQSQ.
7. DQ8, DQ9, DQ10, DQ11, DQ12, DQ13, DQ14, or DQ15.
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MT46H16M16LF__2.fm - Rev. H 6/08 EN
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Timing Diagrams
Figure 38:
Data Output Timing – tDQSQ, tQH, and Data Valid Window (x32)
T1
CK#
CK
T2
tHP5
tHP5
T2n
tHP5
T3
tHP5
tDQSQ3
tDQSQ3
tQH4
tQH4
T3n
tHP5
T4
tHP5
tDQSQ3
tDQSQ3
DQM0/DQM1/DQM2/DQM3
T2
T2n
T3
T3n
DQ (First data no longer valid)2
T2
T2n
T3
T3n
DQ and DQS collectively6
T2
T2n
T3
T3n
Data valid
window
Data valid
window
Data valid
window
Notes:
Byte 3
tQH4
DQ (Last data valid)2
Data valid
window
Byte 2
tQH4
Byte 1
Byte 0
DQ (Last data valid)2
DQ2
DQ2
DQ2
DQ2
DQ2
DQ2
DQ (First data no longer valid)2
DQ transitioning after DQS transitions defines the tDQSQ window.
Byte 0 is DQ[7:0]; byte 1 is DQ[15:8]; byte 2 is DQ[23:16]; byte 3 is DQ[31:24].
tDQSQ is derived at each DQS clock edge and is not cumulative over time and begins with
DQS transition and ends with the last valid DQ transition.
4. tQH is derived from tHP: tQH = tHP - tQHS.
5. tHP is the lesser of tCL or tCH clock transition collectively when a bank is active.
6. The data valid window is derived for each DQS transition and is tQH - tDQSQ.
1.
2.
3.
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MT46H16M16LF__2.fm - Rev. H 6/08 EN
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256Mb: x16, x32 Mobile DDR SDRAM
Timing Diagrams
Figure 39:
Data Output Timing – tAC and tDQSCK
T0
T1
T2
READ
NOP
NOP
T3
T2n
T3n
T4
T4n
T5
T5n
T6
CK#
CK
Command
NOP
NOP
NOP
NOP
CL = 3
tDQSCK
(MAX)
tDQSCK
(MAX)
tRPRE
tRPST
DQS or LDQS/UDQS1
tAC (MAX)
All DQ values, collectively2
T2
T2n
T3
T3n
T4
T4n
T5
T5n
tHZ (MAX)
Notes:
Figure 40:
1.
2.
3.
4.
DQ transitioning after DQS transition define tDQSQ window.
All DQ must transition by tDQSQ after DQS transitions, regardless of tAC.
tAC is the DQ output window relative to CK and is the long-term component of DQ skew.
Shown with CL = 3.
Data Input Timing
T03
T1
T1n
T2
T2n
T3
CK#
CK
tDQSS
tDSH1 tDSS2
tDSH1 tDSS2
DQS4
tDQSL tDQSH tWPST
tWPRES tWPRE
DIN
b
DQ5
DM6
tDS
tDH
Transitioning data
Notes:
Don’t Care
(MIN) generally occurs during tDQSS (MIN).
(MIN) generally occurs during tDQSS (MAX).
WRITE command issued at T0.
For x16, LDQS controls the lower byte, and UDQS controls the upper byte. For x32, DQS0
controls DQ[7:0], DQS1 controls DQ[15:8], DQS2 controls DQ[23:16], and DQS3 controls
DQ[31:24].
5. For x16, LDM controls the lower byte, and UDM controls the upper byte. For x32, DM0 controls DQ[7:0], DM1 controls DQ[15:8]5, DM2 controls DQ[23:16], and DM3 controls
DQ[31:24].
1.
2.
3.
4.
PDF: 09005aef82091978 / Source: 09005aef8209195b
MT46H16M16LF__2.fm - Rev. H 6/08 EN
tDSH
tDSS
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Timing Diagrams
Figure 41:
Initialize and Load Mode Registers
((
))
VDD
((
))
VDDQ
T1
T0
CK#
((
))
((
))
CK
LVCMOS
High level
tCH
tCL
((
))
((
))
CKE
tIS
Command1
Ta0
((
))
((
))
NOP2
Tb0
Tc0
Tf0
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
tIH
NOP
((
))
((
))
PRE
tCK
((
))
((
))
AR
AR
((
))
((
))
DM
((
))
((
))
((
))
((
))
((
))
((
))
Addresses
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
LMR
All banks
((
))
((
))
tIS
((
))
((
))
tIH
((
))
((
))
LMR
((
))
((
))
tIS
Bank address
(BA0, BA1)
Te0
((
))
((
))
((
))
((
))
A10
Td0
((
))
((
))
((
))
((
))
((
))
((
))
NOP3
((
))
((
))
((
))
((
))
CODE
((
))
((
))
RA
((
))
((
))
((
))
((
))
CODE
((
))
((
))
RA
((
))
((
))
((
))
((
))
BA0 = L,
BA1 = H
((
))
((
))
BA
((
))
((
))
tIH
CODE
tIS
ACT
tIH
CODE
tIS
((
))
((
))
tIH
BA0 = L,
BA1 = L
DQS
((
))
High-Z
((
))
((
))
((
))
((
))
((
))
((
))
DQ
((
))
High-Z
((
))
((
))
((
))
((
))
((
))
((
))
T = 200µs
tRP4
tRFC4
tRFC4
tMRD4
tMRD4
Power-up: VDD and CK stable
Don’t Care
Load standard mode register
Load extended mode
register
Notes:
1. PRE = PRECHARGE command; LMR = LOAD MODE REGISTER command; AR = AUTO REFRESH
command; ACT = ACTIVE command; RA = row address; BA = bank address.
2. NOP or DESELECT commands are required for at least 200µs.
3. Other valid commands are possible.
4. NOP or DESELECT commands are required during this time.
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Timing Diagrams
Figure 42:
Power-Down Mode (Active or Precharge)
T0
T1
T2
CK#
CK
tCK
tIS
tCH
Command
Ta2
((
))
((
))
((
))
((
))
((
))
NOP
tIH
((
))
((
))
NOP
((
))
NOP( (
((
))
((
))
DQS
((
))
((
))
((
))
((
))
DQ
((
))
((
))
((
))
((
))
DM
((
))
((
))
((
))
((
))
VALID
VALID
))
((
))
((
))
Address
Tb1
tXP3
tIH
VALID1
tIS
Ta1
tIS
tIH
CKE
tIS
tCL
Ta0
((
))
((
))
VALID
Must not exceed refresh device limits
Enter
power-down
mode2
Notes:
Exit
power-down
mode3
Don’t Care
1. If this command is a PRECHARGE (or if the device is already in the idle state), then the
power-down mode shown is precharge power-down. If this command is an ACTIVE (or if at
least one row is already active), then the power-down mode shown is active power-down.
2. No column accesses are allowed to be in progress at the time power-down is entered.
3. There must be at least one clock pulse during tXP time.
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MT46H16M16LF__2.fm - Rev. H 6/08 EN
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Timing Diagrams
Figure 43:
Auto Refresh Mode
T0
T2
T1
T3
T4
CK#
CK
tIS
tIH
CKE
tCL
tIH
NOP2
PRE
NOP2
NOP2
AR
A0–A9,
A11, A121
All banks
A101
One bank
tIS
1
BA0, BA1
Ta0
Ta1
))
((
))
VALID
tIS
Command1
tCH
CK
((
))
((
))
))
((
))
((
))
((
))
))
((
))
NOP2, 3
AR6
((
))
((
))
Tb0
Tb1
Tb2
NOP2
ACT
VALID
NOP2, 3
((
))
((
))
((
))
((
))
RA
((
))
((
))
((
))
((
))
RA
((
))
((
))
((
))
((
))
BA
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
tIH
Bank(s)4
DQS5
DQ5
DM5
tRP
tRFC
tRFC6
Don’t Care
Notes:
1. PRE = PRECHARGE; ACT = ACTIVE; AR = AUTO REFRESH; RA = row address; BA = bank
address.
2. NOP commands are shown for ease of illustration; other valid commands may be possible at
these times. CKE must be active during clock positive transitions.
3. NOP or COMMAND INHIBIT are the only commands allowed until after tRFC time; CKE must
be active during clock positive transitions.
4. “Don’t Care” if A10 is HIGH at this point; A10 must be HIGH if more than one bank is active
(for example, must precharge all active banks).
5. DM, DQ, and DQS signals are all “Don’t Care”/High-Z for operations shown.
6. The second AUTO REFRESH is not required and is only shown as an example of two back-toback AUTO REFRESH commands.
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MT46H16M16LF__2.fm - Rev. H 6/08 EN
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256Mb: x16, x32 Mobile DDR SDRAM
Timing Diagrams
Figure 44:
Self Refresh Mode
T0
T1
CK#
CK1
tCH
tIS
tCL
tIS
CKE1
Command4
AR
((
))
((
))
((
))
((
))
NOP
((
))
((
))
((
))
((
))
((
))
((
))
DQS
((
))
((
))
((
))
((
))
DQ
((
))
((
))
((
))
((
))
DM
((
))
((
))
((
))
((
))
Address
Tb0
((
))
((
))
((
))
tIH
NOP
Ta1
tCK
tIS
tIH
tIS
Ta01
((
))
((
))
VALID
tIS
tIH
VALID
tXSR3
tRP2
Enter self refresh mode
Exit self refresh mode
Don’t Care
Notes:
1.
2.
3.
4.
5.
PDF: 09005aef82091978 / Source: 09005aef8209195b
MT46H16M16LF__2.fm - Rev. H 6/08 EN
Clock must be stable, cycling within specifications by Ta0, before exiting self refresh mode.
Device must be in the all banks idle state prior to entering self refresh mode.
NOPs or DESELECT is required for tXSR time with at least two clock pulses.
AR = AUTO REFRESH command.
CKE must remain LOW to remain in self refresh mode.
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Timing Diagrams
Figure 45:
CK#
Bank Read – Without Auto Precharge
T1
T0
T2
T3
T4
T5
NOP5
PRE7
T5n
T6
T6n
T7
T8
NOP6
ACT
CK
tIS
tIH
tIS
tIH
tCK
tCH
tCL
CKE
Command5
NOP6
NOP6
ACT
tIS
READ2
NOP6
tIH
A0–A9
RA
A11–Ai9
RA
Col n
RA
RA
tIS
tIH
All banks
A10
RA
RA
3
One bank
tIS
BA0, BA1
tIH
Bank x
Bank x4
Bank x
Bank x
tRCD
tRP
tRAS7
tRC
DM
CL = 2
Case 1: tAC (MIN) and tDQSCK (MIN)
tDQSCK
tRPRE
tRPST
(MIN)
DQS
tLZ
tAC
(MIN)
(MIN)
DOUT
n
DQ1
tLZ
DOUT
n+1
DOUT
n+2
DOUT
n+3
(MIN)
Case 2: tAC (MAX) and tDQSCK (MAX)
tRPRE
tDQSCK
tRPST
(MAX)
DQS
DOUT
n
DQ1
tAC
(MAX)
DOUT
n+1
DOUT
n+2
DOUT
n+3
tHZ
(MAX)
Transitioning data
Notes:
Don’t Care
1.
2.
3.
4.
5.
6.
DOUT n = data-out from column n.
BL = 4 in the case shown.
Disable auto precharge.
“Don’t Care” if A10 is HIGH at T5.
PRE = PRECHARGE, ACT = ACTIVE, RA = row address, and BA = bank address.
NOP commands are shown for ease of illustration; other commands may be valid at these
times.
7. The PRECHARGE command can only be applied at T5 if tRAS minimum is met.
PDF: 09005aef82091978 / Source: 09005aef8209195b
MT46H16M16LF__2.fm - Rev. H 6/08 EN
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Timing Diagrams
8. Refer to Figures 37 and 38 on pages 66–67 for DQS and DQ timing details.
Figure 46:
CK#
Bank Read – with Auto Precharge
T1
T0
T2
T3
T4
T5
T5n
T6
T6n
T7
T8
NOP6
ACT
CK
tIS
tCK
tIH
tCH
tCL
CKE
tIS
Command5
tIH
NOP6
NOP6
ACT
tIS
READ2
NOP6
NOP6
NOP6
tIH
A0–A9
RA
A11, A12
RA
A10
RA
Col n
RA
RA
3
RA
tIS
tIS
BA0, BA1
tIH
tIH
Bank x
Bank x
Bank x
tRCD
tRP
tRAS
tRC
DM
CL = 2
Case 1: tAC (MIN) and tDQSCK (MIN)
tDQSCK
tRPRE
tRPST
(MIN)
DQS
tLZ
(MIN)
tAC
(MIN)
DOUT
n
DQ1
tLZ
DOUT
n+1
DOUT
n+2
DOUT
n+3
(MIN)
Case 2: tAC (MAX) and tDQSCK (MAX)
tRPRE
tDQSCK
(MAX)
tRPST
DQS
DOUT
n
DQ1
tAC
(MAX)
DOUT
n+1
DOUT
n+2
DOUT
n+3
tHZ
(MAX)
Transitioning data
Notes:
1.
2.
3.
4.
5.
6.
PDF: 09005aef82091978 / Source: 09005aef8209195b
MT46H16M16LF__2.fm - Rev. H 6/08 EN
Don’t Care
DOUT n = data-out from column n.
BL = 4 in the case shown.
Enable auto precharge.
“Don’t Care” if A10 is HIGH at T5.
PRE = PRECHARGE; ACT = ACTIVE; RA = row address; BA = bank address.
NOP commands are shown for ease of illustration; other commands may be valid at these
times.
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256Mb: x16, x32 Mobile DDR SDRAM
Timing Diagrams
7. Refer to Figures 37 and 38 on pages 66–67 for DQS and DQ timing details.
Figure 47:
CK#
Bank Write – Without Auto Precharge
T1
T0
CK
T2
tCK
tIS tIH
tCH
T3
T4
WRITE2
NOP6
T4n
T5
T5n
T6
T7
T8
NOP6
NOP6
PRE
tCL
CKE
tIS
Command5
tIH
NOP6
ACT
NOP6
NOP6
tIS tIH
A0–A9
RA
A11, A12
RA
Col n
tIS
A10
RA
tIH
All banks
3
One bank
tIS tIH
Bank x
BA0, BA1
Bank x4
Bank x
tRCD
tWR
tRP
tRAS
tDQSS(NOM)
DQS
tDQSL tDQSH tWPST
tWPRES tWPRE
DOUT
b
DQ1
DM
tDS
tDH
Transitioning data
Notes:
Don’t Care
1. DIN n = data-in from column n; subsequent elements are provided in the programmed
order.
2. BL = 4 in the case shown.
3. Disable auto precharge.
4. “Don’t Care” if A10 is HIGH at T5.
5. PRE = PRECHARGE; ACT = ACTIVE; RA = row address; BA = bank address.
6. NOP commands are shown for ease of illustration; other commands may be valid at these
times.
7. tDSH is applicable during tDQSS (MIN) and is referenced from CK T4 or T5.
8. tDSS is applicable during tDQSS (MIN) and is referenced from CK T5 or T6.
PDF: 09005aef82091978 / Source: 09005aef8209195b
MT46H16M16LF__2.fm - Rev. H 6/08 EN
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256Mb: x16, x32 Mobile DDR SDRAM
Timing Diagrams
Figure 48:
CK#
Bank Write – with Auto Precharge
T1
T0
CK
T2
tCK
tIS tIH
tCH
T3
T4
WRITE2
NOP5
T4n
T5
T5n
T6
T7
T8
NOP5
NOP5
NOP5
tCL
CKE
tIS
Command4
tIH
NOP5
ACT
tIS
NOP5
NOP5
tIH
A0–A9
RA
A11, A12
RA
Col n
3
A10
RA
tIS
BA0, BA1
tIS
tIH
tIH
Bank x
Bank x
tWR
tRCD
tRP
tRAS
tDQSS (NOM)
DQS
tWPRES tWPRE
tDQSL tDQSH tWPST
DI
b
DQ1
DM
tDS
tDH
Transitioning data
Notes:
Don’t Care
1. DIN n = data-in from column n; subsequent elements are provided in the programmed
order.
2. BL = 4 in the case shown.
3. A10 = HIGH, enable auto precharge.
4. ACT = ACTIVE; RA = row address; BA = bank address.
5. NOP commands are shown for ease of illustration; other commands may be valid at these
times.
6. tDSH is applicable during tDQSS (MIN) and is referenced from CK T4 or T5.
7. tDSS is applicable during tDQSS (MIN) and is referenced from CK T5 or T6.
PDF: 09005aef82091978 / Source: 09005aef8209195b
MT46H16M16LF__2.fm - Rev. H 6/08 EN
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256Mb: x16, x32 Mobile DDR SDRAM
Timing Diagrams
Figure 49:
CK#
Write – DM Operation
T1
T0
T2
CK
tIS
tCK
tIH
T3
tCH
T4
T4n
T5
T5n
T6
T7
T8
tCL
CKE
tIS tIH
Command5
NOP6
ACT
tIS
NOP6
WRITE2
RA
A11, A12
RA
NOP6
PRE
Col n
tIS
RA
tIS
BA0, BA1
NOP6
tIH
A0–A9
A10
NOP6
NOP6
tIH
All banks
3
One bank
tIH
Bank x
Bank x4
Bank x
tWR
tRCD
tRP
tRAS
tDQSS (NOM)
DQS
tDQSL
tWPRES tWPRE
tDQSH tWPST
DOUT
b
DQ1
DM
tDS
tDH
Transitioning data
Notes:
Don’t Care
1. DIN n = data-in from column n; subsequent elements are provided in the programmed
order.
2. BL = 4 in the case shown.
3. Disable auto precharge.
4. “Don’t Care” if A10 is HIGH at T5.
5. PRE = PRECHARGE; ACT = ACTIVE; RA = row address; BA = bank address.
6. NOP commands are shown for ease of illustration; other commands may be valid at these
times.
t
7. DSH is applicable during tDQSS (MIN) and is referenced from CK T4 or T5.
8. tDSS is applicable during tDQSS (MIN) and is referenced from CK T5 or T6.
PDF: 09005aef82091978 / Source: 09005aef8209195b
MT46H16M16LF__2.fm - Rev. H 6/08 EN
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Package Dimensions
Package Dimensions
Figure 50:
60-Ball VFBGA Package
0.65 ±0.05
0.3 ±0.025
Seating
plane
A
0.1 A
60x Ø0.45
Dimensions apply
to solder balls
post-reflow. The
pre-reflow balls are
Ø0.42 on Ø0.4 SMD
ball pads.
Solder ball material:
SAC105 (98.5% Sn, 1% Ag, 0.5% Cu)
Substrate material: plastic laminate
Mold compound: epoxy novolac
8 ±0.1
9
8
7
3
2
Micron logo
to be lased
ball A1 ID
Ball A1 ID
4 ±0.05
1
A
B
C
3.6
4.5 ±0.05
D
E
7.2
9 ±0.1
F
G
H
J
0.8 TYP
K
0.8 TYP
6.4
Note:
PDF: 09005aef82091978 / Source: 09005aef8209195b
MT46H16M16LF__2.fm - Rev. H 6/08 EN
3.2
1.0 MAX
All dimensions are in millimeters.
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256Mb: x16, x32 Mobile DDR SDRAM
Package Dimensions
Figure 51:
90-Ball VFBGA Package
0.65 ±0.05
Seating
plane
A
0.1 A
90X 0.45
Dimensions apply
to solder balls postreflow. Pre-reflow
balls are Ø0.42 on
Ø0.4 SMD ball pads.
Solder ball material:
SAC105 (98.5% Sn, 1%Ag, 0.5% Cu)
8 ±0.1
Substrate material: plastic laminate
Mold compound: epoxy novolac
4 ±0.05
Ball A1 ID
9
8
7
3
2
Ball A1 ID
1
A
B
C
D
5.6
E
F
11.2
G
H
0.8 TYP
13 ±0.1
J
K
L
M
N
6.5 ±0.05
P
R
3.2
0.8 TYP
6.4
Note:
1.0 MAX
All dimensions are in millimeters.
®
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
[email protected] www.micron.com Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of
their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth
herein. Although considered final, these specifications are subject to change, as further product development and data
characterization sometimes occur.
PDF: 09005aef82091978 / Source: 09005aef8209195b
MT46H16M16LF__2.fm - Rev. H 6/08 EN
79
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.