Product Specification PE42556 Flip Chip UltraCMOS® SPDT RF Switch 9 kHz - 13500 MHz Product Description The PE42556 RF switch is designed for use in Test/ATE, cellular and other wireless applications. This broadband general purpose switch maintains excellent RF performance and linearity from 9 kHz through 13500 MHz. The PE42556 integrates on-board CMOS control logic driven by a single-pin, low voltage CMOS control input. It also has a logic select pin which enables changing the logic definition of the control pin. Additional features include a novel user defined logic table, enabled by the on-board CMOS circuitry. The PE42556 also exhibits excellent isolation of 26 dB at 13500 MHz, fast settling time, and is offered in a tiny Flip Chip package. The PE42556 is manufactured on Peregrine’s UltraCMOS® process, a patented variation of silicon-oninsulator (SOI) technology on a sapphire substrate, offering the performance of GaAs with the economy and integration of conventional CMOS. Features HaRP™ technology enhanced Eliminates gate lag No insertion loss or phase drift Fast settling time Next Gen 0.25 μm process technology Single-pin 3.3V CMOS logic control High isolation: 26 dB@ 13.5 GHz Low insertion loss: 1.7 dB @ 13.5 GHz P1dB: 33 dBm typical Return loss: 13 dB @ 13.5 GHz (typ) IIP3: +56 dBm typical High ESD: 4kV HBM Absorptive switch design Flip Chip packaging Figure 2. Die Photo (Bumps Up) Figure 1. Functional Diagram Flip Chip Packaging 71-0031 Document No. 70-0289-06 │ www.psemi.com ©2009-2012 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 10 PE42556 Product Specification Table 1. Electrical Specifications: Temp = 25°C, VDD = 3.3V Parameter Conditions Operation Frequency Min Typical 9 kHz Units 13500 MHz As shown 0.93 1.06 1.23 1.41 2.65 dB dB dB dB dB Insertion Loss 9 kHz - 10 MHz 10 - 3000 MHz 3000 - 7500 MHz 7500 - 10000 MHz 10000 - 13500 MHz Isolation – RF1 to RF2 9 kHz - 10 MHz 10 - 3000 MHz 3000 - 7500 MHz 7500 - 10000 MHz 10000 - 13500 MHz 76.5 43.5 30.0 24.0 15.5 88.5 46.0 31.5 25.5 17.5 dB dB dB dB dB Isolation – RFC to RF1 9 kHz - 10 MHz 10 - 3000 MHz 3000 - 7500 MHz 7500 - 10000 MHz 10000 - 13500 MHz 72.5 39.0 31.5 27.0 21.5 84.0 40.5 33.0 30.5 26.5 dB dB dB dB dB Isolation – RFC to RF2 9 kHz - 10 MHz 10 - 3000 MHz 3000 - 7500 MHz 7500 - 10000 MHz 10000 - 13500 MHz 75.5 39.5 31.5 27.5 21.0 87.0 41.0 33.0 30.5 26.0 dB dB dB dB dB Return Loss 9 kHz - 10 MHz 10 - 3000 MHz 3000 - 7500 MHz 7500 - 10000 MHz 10000 - 13500 MHz 22.5 22.0 17.0 16.0 13.0 dB dB dB dB dB Settling Time 50% CTRL to 0.05 dB final value (-40 to +85 °C) Rising Edge 50% CTRL to 0.05 dB final value (-40 to +85 °C) Falling Edge 8.5 9.5 10.0 13.5 µs µs Switching Time 50% CTRL to 90% or 10% of final value (-40 to +85 °C) 3.3 4.0 µs Input 1 dB Compression 1,2 13500 MHz 33 dBm Input IP3 1 13500 MHz 56 dBm Input IP2 1 13500 MHz 107.5 dBm Notes: 0.85 0.92 0.98 1.07 1.74 Max 1. Linearity and power performance are derated at lower frequencies (< 1 MHz) 2. Please refer to Maximum Operating Pin (50Ω) in Table 3 ©2009-2012 Peregrine Semiconductor Corp. All rights reserved. Page 2 of 10 Document No. 70-0289-06 │ UltraCMOS® RFIC Solutions PE42556 Product Specification Figure 3. Bump Configuration (Bumps Up) Table 4. Absolute Maximum Ratings Flip Chip Packaging Vdd CTRL Symbol VDD Parameter/Conditions Power supply voltage Voltage on any input except VI for CTRL and LS inputs Voltage on CTRL input VCTRL VLS Voltage on LS input TST Storage temperature range TOP Operating temperature range 9 kHz ≤ 1 MHz PIN5 (50Ω) 1 MHz ≤ 13.5 GHz ESD voltage (HBM)6 VESD ESD voltage (Machine Model) Vss 11 12 1 LS D-GND D-GND 10 13 2 GND DGND GND 9 14 3 RF2 RF1 4 8 GND RFC GND 7 6 5 Notes: Table 2. Bump Descriptions Bump No. Bump Name 1 VSS 2, 13, 14 D-GND 3, 5, 7, 9 GND Ground 4 RF2 RF Port 2 6 RFC RF Common 8 RF1 Description Negative supply voltage or GND connection (Note 3) Digital Ground -65 -40 Units V V V V °C °C dBm dBm V V 5. Please consult Figures 4 and 5 (low-frequency graphs) for recommended low-frequency operating power level. 6. Human Body Model (HBM, MIL_STD 883 Method 3015.7) Electrostatic Discharge (ESD) Precautions ® RF Port 1 LS 11 VDD Nominal 3.3V supply connection 12 CTRL CMOS logic level When handling this UltraCMOS device, observe the same precautions that you would use with other ESDsensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified. Latch-Up Avoidance Note: 3. Use VSS (bump 1, VSS = -VDD) to bypass and disable internal negative voltage generator. Connect VSS (bump 1) to GND (VSS = 0V) to enable internal negative voltage generator. Unlike conventional CMOS devices, UltraCMOS devices are immune to latch-up. Table 3. Operating Ranges Parameter -0.3 Max 4.0 VDD+ 0.3 4.0 4.0 150 85 Fig. 4,5 30 4000 300 Exceeding absolute maximum ratings may cause permanent damage. Operation should be restricted to the limits in the Operating Ranges table. Operation between operating range maximum and absolute maximum for extended periods may reduce reliability. Logic Select - Used to determine the definition for the CTRL pin (see Table 5) 10 Min -0.3 ® Table 5. Control Logic Truth Table Min Typ Max Units VDD Positive Power Supply Voltage 3.0 3.3 3.6 V VDD Negative Power Supply Voltage -3.6 -3.3 -3.0 V IDD Power Supply Current (Vss = -3.3V, VDD = 3.0 to 3.6V, -40 to +85 °C) 8.0 12.5 μA IDD Power Supply Current (Vss = 0V, VDD = 3.0 to 3.6V, -40 to +85 °C) 21.5 29.0 μA Spurious Performance ISS Negative Power Supply Current (Vss = -3.3V, VDD = 3.0 to 3.6V, -40 to +85 °C) -18.0 -24.0 μA The typical spurious performance of the PE42556 is -116 dBm when VSS = 0V (bump 1 = GND). If further improvement is desired, the internal negative voltage generator can be disabled by setting VSS = -VDD. Control Voltage Low 0.3xVDD V PIN RF Power In4 (50Ω): 9 kHz ≤ 1 MHz 1 MHz ≤ 13.5 GHz Fig. 4,5 30 dBm dBm Control Voltage High 0.7xVDD V Note: 4. Please consult Figures 4 and 5 (low-frequency graphs) for recommended low-frequency operating power level. Document No. 70-0289-06 │ www.psemi.com LS CTRL RFC-RF1 RFC-RF2 0 0 1 1 0 1 0 1 off on on off on off off on Logic Select (LS) The Logic Select feature is used to determine the definition for the CTRL pin. Switching Frequency The PE42556 has a maximum 25 kHz switching rate when the internal negative voltage generator is used (bump1 = GND). The rate at which the PE42556 can be switched is only limited to the switching time (Table 1) if an external negative supply is provided (bump1 = VSS). ©2009-2012 Peregrine Semiconductor Corp. All rights reserved. Page 3 of 10 PE42556 Product Specification Low Frequency Power Handling: ZL = 50Ω Figure 4 provides guidelines of how to adjust the Vdd and Input Power to the PE42556 device. The upper limit curve represents the maximum Input Power vs Vdd recommended for this part at low frequencies only. Please consult Table 3 for the 1 MHz ≤ 13.5 GHz range. Figure 5 shows how the power limit in Figure 4 will increase with frequency. As the frequency increases, the contours and Maximum Power Limit Curve will increase with the increase in power handling shown on the curve. Figure 4. Maximum Operating Power Limit vs. Vdd and Input Power @ 9 kHz Figure 5. Operating Power Offset vs. Frequency (Normalized to 9 kHz) Power Handling Scaling with Frequency Upper Power Limit 30 8 6 25 Operating Power Offset (dB) Input Power (dBm) 4 2 0 -2 -4 -6 -8 20 15 10 5 -10 -12 0 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 Vdd (V) 1 10 100 1000 Freq (kHz) To allow for sustained operation under any load VSWR condition, max power should be kept 6dB lower than max power in 50 Ohm. Power Handling Examples Example 1: Maximum power handling at 100 kHz, Z = 50 ohms, VSWR 1:1, and Vdd = 3V The power handling offset for 100 kHz from Fig. 5 is 7 dB The max power handling at Vdd = 3V is 5.5 dB from Fig. 4 Derate power under mismatch conditions Total maximum power handling for this example is 7 dB + 5.5 dB = 12.5 dBm ©2009-2012 Peregrine Semiconductor Corp. All rights reserved. Page 4 of 10 Document No. 70-0289-06 │ UltraCMOS® RFIC Solutions PE42556 Product Specification Figure 6. Evaluation Board Layouts Evaluation Kit Peregrine Specification 101/0402 The SPDT switch EK Board was designed to ease customer evaluation of Peregrine's PE42556 (dual use with PE42554). The RF Common port is connected through a 50 ohm transmission line via the top SMA connector, J1. RF1 and RF2 are connected through 50 ohm transmission lines via SMA connectors J3, and J2, respectively. A through 50 ohm transmission line is available via SMA connectors J4 and J5. This transmission line can be used to estimate the loss of the PCB over the environmental conditions being evaluated. The board is constructed of a four metal layers with a total thickness of 62 mils. The top and bottom layers are ROGERS RO4003 material with an 8 mil core and Er = 3.55. The middle layers provide ground for the transmission lines. The RF transmission lines were designed using a coplanar waveguide with ground plane model using a trace width of 15 mils, and trace gaps of 10 mils. X Figure 7. Evaluation Board Schematic Peregrine Specification 102/0478 J9 HEADER, 12 PIN 1 CTL GND 2 3 LS GND 4 5 NC GND 6 7 VDD GND 8 9 VSS GND 10 11 GND GND 12 General Comments -Transmission lines connected to J1, J2, and J3 should have exactly the same electrical length. The path from J2 to J3 including the distance through the part should have the same length as J4 and J5 and be in parallel to J4 to J5. NOTES: 2 J1 6 10 LS VSS CTL VDD 1 12 11 1. USE 101-0402-02 PCB U1 PE42554 RF1 RFC RF2 2 J4 1 Document No. 70-0289-06 │ www.psemi.com J3 1 4 2 2 3 5 7 9 13 14 G0 G1 G2 G4 G5 G6 G7 1 2 8 J2 1 2 J5 1 ©2009-2012 Peregrine Semiconductor Corp. All rights reserved. Page 5 of 10 PE42556 Product Specification Performance Plots: Temperature = 25°C, VDD = 3.3V unless otherwise indicated Figure 8. Nominal Insertion Loss: RF1, RF2 Figure 9. Insertion Loss: RFX @ 3.3V Figure 10. Insertion Loss: RFX @ 25°C Figure 11. Isolation: Active Port to Isolated Port @ 3.3V Figure 12. Isolation: Active Port to Isolated Port @ 25°C Figure 13. Isolation: RFC to Isolated Port @ 3.3V ©2009-2012 Peregrine Semiconductor Corp. All rights reserved. Page 6 of 10 Document No. 70-0289-06 │ UltraCMOS® RFIC Solutions PE42556 Product Specification Performance Plots: Temperature = 25 °C, VDD = 3.3 V unless otherwise indicated Figure 14. Isolation: RFC to Isolated Port @ 25°C Figure 15. Return Loss at Active Port @ 3.3V Figure 16. Return Loss at Active Port @ 25°C Figure 17. IIP3: Third Order Distortion from IIP3: Third Order Distortion from 9kHz - 14 GHz 9 kHz - 14 GHz 70 Linearity [dBm] 60 50 40 Nominal Performance 30 20 10 9 10 0. 0E +9 10 .0 E+ 1. 0E +9 6 10 0. 0E +6 10 .0 E+ 1. 0E +6 3 10 0. 0E +3 10 .0 E+ 1. 0E +3 0 Frequency [Hz] Document No. 70-0289-06 │ www.psemi.com ©2009-2012 Peregrine Semiconductor Corp. All rights reserved. Page 7 of 10 PE42556 Product Specification Table 6. Mechanical Specifications Parameter Typical Minimum Die Size, Drawn (x,y) Maximum 996 x 1896 Die Size, Singulated (x,y) Wafer Thickness Units Test Conditions μm As drawn Including excess sapphire, max. tolerance = -20/+50 μm 1080 x 1980 1100 x 2000 1150 x 2050 μm 180 200 220 µm Wafer Size 150 mm Ball Pitch 400 μm Ball Height 72.25 85 Ball Diameter 97.75 μm 110 UBM Diameter 85 90 Typical μm 95 μm RoHS compliant lead-free solder balls Solder ball composition: 95.5%Sn/3.5%Ag/ 1.0%Cu Table 7. Bump Coordinates Bump # Bump Name 1 Figure 18. Pad Layout (Bumps Up) Bump Center (µm) X Y Vdd CTRL Vss VSS 400 850 11 12 1 2 DGND 400 450 LS D-GND D-GND 3 GND4 400 50 10 13 2 4 RF2 400 -350 GND DGND GND 5 GND3 400 -750 9 14 3 6 RFC 0 -750 RF1 RF2 7 GND1 -400 -750 8 4 8 RF1 -400 -350 GND RFC GND 9 GND2 -400 50 7 6 5 10 LS -400 450 11 VDD -400 850 12 CTRL 0 850 13 DGND 0 450 14 DGND 0 50 2000 μm -20/+50 μm 1100 μm -20/+50 μm Singulated Die size: 1.1 X 2.0 mm (400 µm ball pitch) All bump locations originate from the die center and refer to the center of the bump. Ball pitch is 400 µm. ©2009-2012 Peregrine Semiconductor Corp. All rights reserved. Page 8 of 10 Document No. 70-0289-06 │ UltraCMOS® RFIC Solutions PE42556 Product Specification Figure 19. Tape and Reel Specifications 4.00 ± .05 (.157 ± .002) 1.50 + .10 (.059 + .004) 2.00 ± .05 (.079 ±.002) 4.00 ± .05 (.157 ± .002) Bump 1 .229 ± .02 (.009 ± .0008) LOGO Pin #1 1.75 ± .10 (.069 ± .004) 3.50 ± .05 (.138 ± .002) Bo 8.00 +.30 -.10 (.315 +.012 - .004) 2.1± .05 (.083 ± .002) Ao 1.2 ± .05 (.047 ± .002) AO = 1.2 BO = 2.1 KO = 0.45 Tape Feed Direction KO .45 ± .05 (.018 ± .002) Note: Bumped die are oriented active side down Maximum cavity angle 5o Drawing not drawn to scale, pocket hole diameter 0.6 ± 0.05 mm Table 8. Ordering Information Order Code Package Specification Shipping Method PE42556DI Die on cut Tape and Reel 81-0012 Loose or cut tape PE42556DI-Z Die on full Tape and Reel 81-0012 1,000 Dice / Reel PE42556DBI Die in waffle pack 81-0015 204 Dice / Waffle pack EK42556-01 Evaluation Kit Document No. 70-0289-06 │ www.psemi.com 1/ box ©2009-2012 Peregrine Semiconductor Corp. All rights reserved. Page 9 of 10 PE42556 Product Specification Sales Contact and Information For Sales and contact information please visit www.psemi.com. Advance Information: The product is in a formative or design stage. The datasheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification: The datasheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification: The datasheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a CNF (Customer Notification Form). The information in this datasheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user’s own risk. ©2009-2012 Peregrine Semiconductor Corp. All rights reserved. Page 10 of 10 No patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party. Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, UltraCMOS and UTSi are registered trademarks and HaRP, MultiSwitch and DuNE are trademarks of Peregrine Semiconductor Corp. Document No. 70-0289-06 │ UltraCMOS® RFIC Solutions