RT8015B 3A, 2MHz, Synchronous Step-Down Converter General Description Features The RT8015B is a high efficiency synchronous, step down DC/DC converter. Its input voltage range is from 2.6V to 5.5V and provides an adjustable regulated output voltage from 0.8V to 5V while delivering up to 3A of output current. z z z z z z z z Applications z z The RT8015B is operated in forced continuous PWM Mode which minimizes ripple voltage and reduces the noise and RF interference. The 100% duty cycle in Low Dropout Operation further maximize battery life. The RT8015B is available in the WDFN-10L 3x3 and SOP8 (Exposed Pad) packages. Ordering Information RT8015B Package Type QW : WDFN-10L 3x3 SP : SOP-8 (Exposed Pad-Option 2) Lead Plating System G : Green (Halogen Free and Pb Free) Note : Low RDS(ON) Internal Switches : 110mΩ Ω Programmable Frequency : 300kHz to 2MHz No Schottky Diode Required 0.8V Reference Allows for Low Output Voltage Forced Continuous Mode Operation Low Dropout Operation : 100% Duty Cycle Power Good Output Voltage Indicator RoHS Compliant and Halogen Free z z z z Portable Instruments Battery-Powered Equipment Notebook Computers Distributed Power Systems IP Phones Digital Cameras Pin Configurations (TOP VIEW) SHDN/RT GND LX LX PGND 1 2 3 4 5 10 9 8 7 11 9 The internal synchronous low on resistance power switches increase efficiency and eliminate the need for an external Schottky diode. The switching frequency is set by an external resistor. The 100% duty cycle provides low dropout operation extending battery life in portable systems. Current mode operation with external compensation allows the transient response to be optimized over a wide range of loads and output capacitors. z High Efficiency : Up to 95% WDFN-10L 3x3 8 SHDN/RT GND 2 LX PGND 3 4 GND 9 RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. ` Suitable for use in SnPb or Pb-free soldering processes. COMP 7 FB 6 VDD 5 PVDD Richtek products are : ` COMP FB PGOOD VDD PVDD SOP-8 (Exposed Pad) Marking Information For marking information, contact our sales representative directly or through a Richtek distributor located in your area. DS8015B-04 March 2011 www.richtek.com 1 RT8015B Typical Application Circuit RT8015B VIN 5V 6 PVDD CIN 22µF R3 1 R4 100k 7 VDD 8 ROSC 332k L1 2.2µH VOUT 2.5V/3A CF 22pF R1 510k COUT 22µF x 2 FB 9 C1 0.1µF PGOOD LX 3, 4 PGOOD 1 SHDN/RT COMP 10 GND PGND RCOMP CCOMP 1nF 27k R2 240k 2 5 Note : Using all Ceramic Capacitors Table 1. Recommended Component Selection VOUT (V) R1 (kΩ) R2 (kΩ) RCOMP (kΩ) CCOMP (nF) L1 (μH) COUT (μF) 3.3 750 240 30 1 2.2 22 x 2 2.5 510 240 27 1 2.2 22 x 2 1.8 300 240 22 1 2.2 22 x 2 1.5 210 240 18 1 2.2 22 x 2 1.2 120 240 15 1 1.0 22 x 2 1.0 60 240 13 1 1.0 22 x 2 Functional Pin Description Pin No. WDFN SOP-8 -10L 3x3 (Exposed Pad) Pin Name 1 1 SHDN/RT 2 2 GND 3, 4 3 LX 5 4 PGND 6 5 PVDD 7 6 8 -- 9 7 10 8 11 -- -- 9 www.richtek.com 2 Pin Function Oscillator Resistor Input. Connecting a resistor to ground from this pin sets the switching frequency. Forcing this pin to VDD causes the device to be shut down. Signal Ground. All small signal components and compensation components should connect to this ground, which in turn connects to PGND at one point. Internal Power MOSFET Switches Output. Connect this pin to the inductor. Power Ground. Connect this pin close to the negative terminal of CIN and COUT. Power Input Supply. Decouple this pin to PGND with a capacitor. Signal Input Supply. Decouple this pin to GND with a capacitor. Normally VDD is equal to PVDD. Power Good Indicator. This pin is open drain logic output that is PGOOD pulled to ground when the output voltage is not within ±12.5% of regulation point. Feedback Pin. This pin receives the feedback voltage from a FB resistive divider connected across the output. Error Amplifier Compensation Point. The current comparator COMP threshold increases with this control voltage. Connect external compensation elements to this pin to stabilize the control loop. No Internal Connection. The exposed pad must be soldered to a (Exposed Pad) large PCB and connected to GND for maximum power dissipation. The exposed pad must be soldered to a large PCB and connected to GND GND for maximum power dissipation. VDD DS8015B-04 March 2011 RT8015B Function Block Diagram SHDN/RT SD PVDD ISEN Slope Com OSC COMP 0.8V Output Clamp EA FB OC Limit Driver Int-SS LX 0.9V Control Logic 0.7V NISEN PGND NMOS I Limit POR 0.2V PGOOD V REF OTP GND VDD Layout Guide Place the input and output capacitors as close to the IC as possible. GND VIN R3 C1 R1 RT8015B Bottom Layer R4 GND CF COUT CIN R2 PVDD VDD PGOOD FB COMP 6 5 7 4 8 3 9 2 10 1 LX should be connected to Inductor by wide and short trace, keep sensitive L1 components away from this trace VOUT PGND LX LX GND SHDN/RT ROSC RCOMP CCOMP VOUT GND Place the feedback and compensation components as close to the IC as possible. DS8015B-04 March 2011 www.richtek.com 3 RT8015B Operation Main Control Loop Slope Compensation and Inductor Peak Current The RT8015B is a monolithic, constant-frequency, current mode step-down DC/DC converter. During normal operation, the internal top power switch (P-Channel MOSFET) is turned on at the beginning of each clock cycle. Current in the inductor increases until the peak inductor current reach the value defined by the voltage on the COMP pin. The error amplifier adjusts the voltage on the COMP pin by comparing the feedback signal from a resistor divider on the FB pin with an internal 0.8V reference. When the load current increases, it causes a reduction in the feedback voltage relative to the reference. The error amplifier raises the COMP voltage until the average inductor current matches the new load current. When the top power MOSFET shuts off, the synchronous power switch (N-MOSFET) turns on until either the bottom current limit is reached or the beginning of the next clock cycle. Slope compensation provides stability in constant frequency architectures by preventing sub-harmonic oscillations at duty cycles greater than 50%. It is accomplished internally by adding a compensating ramp to the inductor current signal. Normally, the maximum inductor peak current is reduced when slope compensation is added. In the RT8015B, however, separated inductor current signals are used to monitor over current condition. This keeps the maximum output current relatively constant regardless of duty cycle. The operating frequency is set by an external resistor connected between the RT pin and ground. The practical switching frequency can range from 300kHz to 2MHz. Short Circuit Protection When the output is shorted to ground, the inductor current decays very slowly during a single switching cycle. A current runaway detector is used to monitor inductor current. As current increasing beyond the control of current loop, switching cycles will be skipped to prevent current runaway from occurring. Dropout Operation When the input supply voltage decreases toward the output voltage, the duty cycle increases toward the maximum on-time. Further reduction of the supply voltage forces the main switch to remain on for more than one cycle eventually reaching 100% duty cycle. The output voltage will then be determined by the input voltage minus the voltage drop across the internal P-Channel MOSFET and the inductor. Low Supply Operation The RT8015B is designed to operate down to an input supply voltage of 2.6V. One important consideration at low input supply voltages is that the R DS(ON) of the P-Channel and N-Channel power switches increases. The user should calculate the power dissipation when the RT8015B is used at 100% duty cycle with low input voltages to ensure that thermal limits are not exceeded. www.richtek.com 4 DS8015B-04 March 2011 RT8015B Absolute Maximum Ratings z z z z z z z z z z (Note 1) Supply Input Voltage, VDD, PVDD ---------------------------------------------------------------------------- −0.3V to 6V LX Pin Switch Voltage -------------------------------------------------------------------------------------------- −0.3V to (PVDD + 0.3V) <200ns --------------------------------------------------------------------------------------------------------------- −5V to 7.5V Other I/O Pin Voltages ------------------------------------------------------------------------------------------- −0.3V to (VDD + 0.3V) LX Pin Switch Current -------------------------------------------------------------------------------------------- 4A Power Dissipation, PD @ TA = 25°C SOP-8 (Exposed Pad) ------------------------------------------------------------------------------------------- 1.333W WDFN-10L 3x3 ----------------------------------------------------------------------------------------------------- 1.429W Package Thermal Resistance (Note 2) SOP-8 (Exposed Pad), θJA ------------------------------------------------------------------------------------- 75°C/W SOP-8 (Exposed Pad), θJC ------------------------------------------------------------------------------------- 15°C/W WDFN-10L 3x3, θJA ----------------------------------------------------------------------------------------------- 70°C/W WDFN-10L 3x3, θJC ----------------------------------------------------------------------------------------------- 8.2°C/W Junction Temperature --------------------------------------------------------------------------------------------- 150°C Lead Temperature (Soldering, 10 sec.) ----------------------------------------------------------------------- 260°C Storage Temperature Range ------------------------------------------------------------------------------------ −65°C to 150°C ESD Susceptibility (Note 3) HBM (Human Body Mode) -------------------------------------------------------------------------------------- 2kV MM (Machine Mode) ---------------------------------------------------------------------------------------------- 200V Recommended Operating Conditions z z z (Note 4) Supply Input Voltage ---------------------------------------------------------------------------------------------- 2.6V to 5.5V Junction Temperature Range ------------------------------------------------------------------------------------ −40°C to 125°C Ambient Temperature Range ------------------------------------------------------------------------------------ −40°C to 85°C Electrical Characteristics (VDD = 3.3V, TA = 25°C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit Input Voltage Range VDD 2.6 -- 5.5 V Feedback Reference Voltage VREF 0.784 0.8 0.816 V Feedback Leakage Current IFB -- 0.1 0.4 μA Active , VFB = 0.78V, Not Switching -- 460 -- μA Shutdown -- -- 1 μA Output Voltage Line Regulation VIN = 2.7V to 5.5V -- 0.03 -- %/V Output Voltage Load Regulation Measured in Servo Loop, VCOMP = 0.2V to 0.7V (Note 5) −0.2 ±0.02 0.2 % DC Bias Current Error Amplifier Transconductance gm -- 800 -- μs Current Sense Transresistance RT -- 0.4 -- Ω -- -- 1 μA Switching Leakage Current SHDN/RT = VIN = 5.5V To be continued DS8015B-04 March 2011 www.richtek.com 5 RT8015B Parameter Symbol Switching Frequency Test Conditions Min Typ Max Unit ROSC = 332k 0.8 1 1.2 MHz Switching Frequency 0.3 -- 2 MHz Switch On Resistance, High RPMOS ISW = 0.5A -- 110 160 mΩ Switch On Resistance, Low RNMOS ISW = 0.5A -- 110 170 mΩ Power Good Range -- ±12.5 ±15 % Power Good Pull-Down Resistance -- -- 120 Ω 3.2 3.8 -- A VDD Rising -- 2.4 -- V VDD Falling -- 2.3 -- V Peak Current Limit Under Voltage Lockout Threshold ILIM Shutdown Threshold -- VIN − 0.7 VIN − 0.4 V Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. θJA is measured in natural convection at TA = 25°C on a high-effective thermal conductivity four-layer test board of JEDEC 51-7 thermal measurement standard. The measurement case position of θJC is on the exposed pad of the packages. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. The specifications over the -40°C to 85°C operation ambient temperature range are assured by design, characterization and correlation with statistical process controls. www.richtek.com 6 DS8015B-04 March 2011 RT8015B Typical Operating Characteristics Efficiency vs. Load Current Output Voltage vs. Load Current 100 2.492 90 2.488 2.484 Output Voltage (V) Efficiency (%) 80 VIN = 5.5V 70 60 VIN = 5V 50 VIN = 4.5V 40 30 2.480 2.476 2.472 2.468 2.464 2.460 VOUT = 2.5V VIN = 5V 20 2.456 0.01 0.1 1 10 0.0 0.5 1.0 2.0 2.5 Frequency vs. Temperature Peak Current Limit vs. Input Voltage 1.08 5.0 4.5 Current Limit (A) 1.06 1.04 1.02 1.00 4.0 3.5 3.0 2.5 VOUT = 2.5V VIN = 5V, VOUT = 2.5V, IOUT = 0A 2.0 0.98 -50 -25 0 25 50 75 100 125 3.5 3.75 4 4.25 Temperature (°C) 4.5 4.75 5 5.25 5.5 Input Voltage (V) Quiescent Current vs. Input Voltage Quiescent Current vs. Temperature 450 450 Quiescent Current (uA) 440 Quiescent Current (uA) 3.0 Load Current (A) Load Current (A) Frequency (MHz) 1.5 430 420 410 400 390 380 370 440 430 420 410 400 390 VIN = 5V 380 360 2.5 3 3.5 4 4.5 Input Voltage (V) DS8015B-04 March 2011 5 5.5 -50 -25 0 25 50 75 100 125 Temperature (°C) www.richtek.com 7 RT8015B Output Voltage vs. Temperature UVP 3.34 VIN = 5V, VOUT = 1.05V Output Voltage (V) 3.32 VOUT (1V/Div) VLX (5V/Div) 3.30 3.28 ILX (5A/Div) 3.26 3.24 VIN = 5V PGOOD (5V/Div) 3.22 -50 -25 0 25 50 75 100 Time (4μs/Div) 125 Temperature (°C) Output Ripple Load Transient Response VIN = 5V, VOUT = 2.5V IOUT = 0A to 3A VLX (5V/Div) VOUT_ac (100mV/Div) VOUT_ac (10mV/Div) ILX (2A/Div) I LOAD (1A/Div) Time (100μs/Div) Time (400ns/Div) Start up with No Load Start up with Heavy Load VIN (5V/Div) VIN (5V/Div) VLX (5V/Div) VLX (5V/Div) VOUT (1V/Div) PGOOD (5V/Div) VOUT (1V/Div) PGOOD (5V/Div) VIN = 5V, VOUT = 10.5V, IOUT = 0A Time (400μs/Div) www.richtek.com 8 VIN = 5V, VOUT = 2.5V IOUT = 3A VIN = 5V, VOUT = 1.05V, IOUT = 3A Time (400μs/Div) DS8015B-04 March 2011 RT8015B Application Information The basic RT8015B application circuit is shown in Typical Application Circuit. External component selection is determined by the maximum load current and begins with the selection of the inductor value and operating frequency followed by CIN and COUT. Power Good Output The output voltage is set by an external resistive divider according to the following equation : The power good output is an open-drain output and requires a pull up resistor. When the output voltage is 12.5% above or 12.5% below its set voltage, PGOOD will be pulled low. It is held low until the output voltage returns to within the allowed tolerances once more. In soft start, PGOOD is actively held low and is allowed to transition high until soft start finished over and the output voltage reaches 87.5% of its set voltage. VOUT = VREF × ⎛⎜1 + R1 ⎞⎟ ⎝ R2 ⎠ Operating Frequency Output Voltage Programming where VREF equals to 0.8V typical. The resistive divider allows the FB pin to sense a fraction of the output voltage as shown in Figure 1. V OUT R1 FB RT8015B R2 GND Figure 1. Setting the Output Voltage Soft-Start The RT8015B contains an internal soft-start clamp that gradually raises the clamp on the COMP pin. The full current range becomes available on COMP after 2048 switching cycles as shown in Figure 2. Selection of the operating frequency is a tradeoff between efficiency and component size. High frequency operation allows the use of smaller inductor and capacitor values. Operation at lower frequency improves efficiency by reducing internal gate charge and switching losses but requires larger inductance and/or capacitance to maintain low output ripple voltage. The operating frequency of the RT8015B is determined by an external resistor that is connected between the RT pin and ground. The value of the resistor sets the ramp current that is used to charge and discharge an internal timing capacitor within the oscillator. The RT resistor value can be determined by examining the frequency vs. RT curve. Although frequencies as high as 2MHz are possible, the minimum on-time of the RT8015B imposes a minimum limit on the operating duty cycle. The minimum on-time is typically 110ns. Therefore, the minimum duty cycle is equal to 100 x 110ns x f(Hz). 2.5 RT = 152k for 2MHz VIN (2V/Div) Frequency (MHz) 2 VOUT (500mV/Div) ILX (1A/Div) VIN = 5V, VOUT = 1.05V, IOUT = 2A 1.5 RT = 330k for 1MHz 1 0.5 Time (1ms/Div) Figure 2. Soft-Start 0 0 200 400 600 800 1000 ROSC ٛ) (kΩ) OSC (k Figure 3 DS8015B-04 March 2011 www.richtek.com 9 RT8015B Inductor Selection For a given input and output voltage, the inductor value and operating frequency determine the ripple current. The ripple current ΔIL increases with higher VIN and decreases with higher inductance. ⎡V ⎤⎡ V ⎤ ΔIL = ⎢ OUT ⎥ ⎢1 − OUT ⎥ f L × V IN ⎣ ⎦⎣ ⎦ Having a lower ripple current reduces the ESR losses in the output capacitors and the output voltage ripple. Highest efficiency operation is achieved at low frequency with small ripple current. This, however, requires a large inductor. A reasonable starting point for selecting the ripple current is ΔI = 0.4(IMAX). The largest ripple current occurs at the highest VIN. To guarantee that the ripple current stays below a specified maximum, the inductor value should be chosen according to the following equation : ⎡ VOUT ⎤ ⎡ VOUT ⎤ L=⎢ 1− ⎥ ⎢ ⎥ ⎣ f × ΔIL(MAX) ⎦ ⎣ VIN(MAX) ⎦ Inductor Core Selection Once the value for L is known, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite or mollypermalloy cores. Actual core loss is independent of core size for a fixed inductor value but it is very dependent on the inductance selected. As the inductance increases, core losses decrease. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates “hard”, which means that inductance collapses abruptly when the peak design current is exceeded. This result in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! Different core materials and shapes will change the size/ current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are www.richtek.com 10 small and don't radiate energy but generally cost more than powdered iron core inductors with similar characteristics. The choice of which style inductor to use mainly depends on the price vs. size requirements and any radiated field/EMI requirements. CIN and COUT Selection The input capacitance, C IN, is needed to filter the trapezoidal current at the source of the top MOSFET. To prevent large ripple voltage, a low ESR input capacitor sized for the maximum RMS current should be used. RMS current is given by : V IRMS = IOUT(MAX) OUT VIN VIN −1 VOUT This formula has a maximum at VIN = 2VOUT, where I RMS = I OUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. The selection of COUT is determined by the effective series resistance (ESR) that is required to minimize voltage ripple and load step transients, as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. Loop stability can be checked by viewing the load transient response as described in a later section. The output ripple, ΔVOUT, is determined by : ⎡ 1 ⎤ ΔVOUT ≤ ΔIL ⎢ESR + ⎥ 8fC OUT ⎦ ⎣ The output ripple is highest at maximum input voltage since ΔIL increases with input voltage. Multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirements. Dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. Special polymer capacitors offer very low ESR but have lower capacitance density than other types. Tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. Aluminum electrolytic capacitors have significantly higher ESR but can be used in cost sensitive DS8015B-04 March 2011 RT8015B applications provided that consideration is given to ripple current ratings and long term reliability. Ceramic capacitors have excellent low ESR characteristics but can have a high voltage coefficient and audible piezoelectric effects. The high Q of ceramic capacitors with trace inductance can also lead to significant ringing. Using Ceramic Input and Output Capacitors Higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. Their high ripple current, high voltage rating and low ESR make them ideal for switching regulator applications. However, care must be taken when these capacitors are used at the input and output. When a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, VIN. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at VIN large enough to damage the part. Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to ΔILOAD(ESR), where ESR is the effective series resistance of C OUT. ΔILOAD also begins to charge or discharge COUT generating a feedback error signal used by the regulator to return VOUT to its steady state value. During this recovery time, VOUT can be monitored for overshoot or ringing that would indicate a stability problem. The COMP pin external components and output capacitor shown in Typical Application Circuit will provide adequate compensation for most applications. Efficiency Considerations The efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Efficiency can be expressed as : are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses: VDD quiescent current and I2R losses. The VDD quiescent current loss dominates the efficiency loss at very low load currents whereas the I2R loss dominates the efficiency loss at medium to high load currents. In a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the actual power lost is of no consequence. 1. The VDD quiescent current is due to two components : the DC bias current as given in the electrical characteristics and the internal main switch and synchronous switch gate charge currents. The gate charge current results from switching the gate capacitance of the internal power MOSFET switches. Each time the gate is switched from high to low to high again, a packet of charge ΔQ moves from VDD to ground. The resulting ΔQ/Δt is the current out of VDD that is typically larger than the DC bias current. In continuous mode, IGATECHG = f(QT+QB) where QT and QB are the gate charges of the internal top and bottom switches. Both the DC bias and gate charge losses are proportional to VDD and thus their effects will be more pronounced at higher supply voltages. 2. I2R losses are calculated from the resistances of the internal switches, RSW and external inductor RL. In continuous mode, the average output current flowing through inductor L is “chopped” between the main switch and the synchronous switch. Thus, the series resistance looking into the LX pin is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (D) as follows : RSW = RDS(ON)TOP x D + RDS(ON)BOT x (1"D) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics curves. Thus, to obtain I2R losses, simply add RSW to RL and multiply the result by the square of the average output current. Other losses including CIN and COUT ESR dissipative losses and inductor core losses generally account for less than 2% of the total loss. Efficiency = 100% − (L1+ L2+ L3+ ...) where L1, L2, etc. DS8015B-04 March 2011 www.richtek.com 11 RT8015B RT8015B has cycle by cycle current limiting control. The current limit circuit employs a “peak” current sensing algorithm. If the magnitude of the current sense signal is above the current limit threshold, the controller will turn off high side MOSFET and turn on low side MOSFET. The maximum power dissipation depends on the operating ambient temperature for fixed T J(MAX) and thermal resistance, θJA. For the RT8015B packages, the derating curves in Figure 4 allow the designer to see the effect of rising ambient temperature on the maximum power dissipation. Maximum Power Dissipation (W) Current Limit Under Voltage Protection (UVP) The output voltage can be continuously monitored for under voltage protection. When the output voltage is less than 25% of its set voltage threshold, the under voltage protection circuit will be triggered to terminate switching operation and the controller will be latched unless VDD POR is detected again. During soft-start, the UVP will be blanked until soft-start finish. Thermal Considerations For continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and ambient temperature. The maximum power dissipation can be calculated by the following formula : PD(MAX) = (TJ(MAX) − TA) / θJA PD(MAX) = (125°C − 25°C) / (75°C/W) = 1.333W for SOP-8 (Exposed Pad) package PD(MAX) = (125°C − 25°C) / (70°C/W) = 1.429W for WDFN-10L 3x3 package www.richtek.com 12 Four-Layer PCB WDFN-10L 3x3 SOP-8 (Exposed Pad) 0 25 50 75 100 125 Ambient Temperature (°C) Figure 4. Derating Curves for RT8015B Package Layout Considerations Follow the PCB layout guidelines for optimal performance of RT8015B. ` A ground plane is recommended. If a ground plane layer is not used, the signal and power grounds should be segregated with all small-signal components returning to the GND pin at one point that is then connected to the PGND pin close to the IC. The exposed pad should be connected to GND. ` Connect the terminal of the input capacitor(s), CIN, as close as possible to the PVDD pin. This capacitor provides the AC current into the internal power MOSFETs. ` LX node is with high frequency voltage swing and should be kept within small area. Keep all sensitive small-signal nodes away from the LX node to prevent stray capacitive noise pick-up. ` Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of powercomponents. You can connect the copper areas to any DC net (PVDD, VDD, VOUT, PGND, GND, or any other DC rail in your system). where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and θJA is the junction to ambient thermal resistance. For recommended operating condition specifications of the RT8015B, the maximum junction temperature is 125°C and TA is the ambient temperature. The junction to ambient thermal resistance, θJA, is layout dependent. For SOP-8 (Exposed Pad) packages, the thermal resistance, θJA, is 75°C/W on a standard JEDEC 51-7 four-layer thermal test board. For WDFN-10L 3x3 packages, the thermal resistance, θJA, is 70°C/W on a standard JEDEC 51-7 four-layer thermal test board. The maximum power dissipation at TA = 25°C can be calculated by the following formulas : 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 DS8015B-04 March 2011 RT8015B ` Connect the FB pin directly to the feedback resistors. The resistor divider must be connected between VOUT and GND. Figure 5 Figure 6 DS8015B-04 March 2011 www.richtek.com 13 RT8015B Recommended component selection for Typical Application Table 1. Inductors Component Inductance (μH) DCR (mΩ) Series Supplier TAIYO YUDEN NR 8040 2 9 Current Rating (mA) 7800 Dimensions (mm) 8x8x4 Table 2. Capacitors for CIN and COUT Component Supplier TDK TDK Panasonic Panasonic TAIYO YUDEN TAIYO YUDEN TAIYO YUDEN www.richtek.com 14 Part No. C3225X5R0J226M C2012X5R0J106M ECJ4YB0J226M ECJ4YB1A106M LMK325BJ226ML JMK316BJ226ML JMK212BJ106ML Capacitance (μF) 22 10 22 10 22 22 10 Case Size 1210 0805 1210 1210 1210 1206 0805 DS8015B-04 March 2011 RT8015B Outline Dimension D2 D L E E2 1 SEE DETAIL A 2 e A A1 1 2 1 b DETAIL A Pin #1 ID and Tie Bar Mark Options A3 Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 D 2.950 3.050 0.116 0.120 D2 2.300 2.650 0.091 0.104 E 2.950 3.050 0.116 0.120 E2 1.500 1.750 0.059 0.069 e L 0.500 0.350 0.020 0.450 0.014 0.018 W-Type 10L DFN 3x3 Package DS8015B-04 March 2011 www.richtek.com 15 RT8015B H A M EXPOSED THERMAL PAD (Bottom of Package) Y J X B F C I D Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 4.801 5.004 0.189 0.197 B 3.810 4.000 0.150 0.157 C 1.346 1.753 0.053 0.069 D 0.330 0.510 0.013 0.020 F 1.194 1.346 0.047 0.053 H 0.170 0.254 0.007 0.010 I 0.000 0.152 0.000 0.006 J 5.791 6.200 0.228 0.244 M 0.406 1.270 0.016 0.050 X 2.000 2.300 0.079 0.091 Y 2.000 2.300 0.079 0.091 X 2.100 2.500 0.083 0.098 Y 3.000 3.500 0.118 0.138 Option 1 Option 2 8-Lead SOP (Exposed Pad) Plastic Package Richtek Technology Corporation Richtek Technology Corporation Headquarter Taipei Office (Marketing) 5F, No. 20, Taiyuen Street, Chupei City 5F, No. 95, Minchiuan Road, Hsintien City Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)86672399 Fax: (8862)86672377 Email: [email protected] Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek. www.richtek.com 16 DS8015B-04 March 2011