RICHTEK RT8803A_11

RT8803A
2/3-Phase PWM Controller for High-Density Power Supply
General Description
Features
The RT8803A is a 2/3-phase synchronous buck controller
specifically designed to power Intel®/ AMD next generation
microprocessors. It implements an internal 8-bit DAC that is
identified by VID code of microprocessor directly. RT8803A
generates VID table that conform to Intel® VRD10.x and
VRD11 core power with 6.25mV increments and 0.5%
accuracy.
z
5V Power Supply
z
2/3-Phase Power Conversion with Automatic Phase
Selection
8-bit VID Interface, Supporting Intel VRD11/VRD10.x
and AMD K8, K8_M2 CPUs
VR_HOT and VR_FAN Indication
Precision Core Voltage Regulation
Power Stage Thermal Balance by DCR Current
Sensing
Adjustable Soft-start
Over-Voltage Protection
Adjustable Frequency and Typical at 300kHz per
Phase
Power Good Indication
32-Lead VQFN Package
RoHS Compliant and 100% Lead (Pb)-Free
z
z
z
z
Applications
z
z
z
Intel®/AMD New generation microprocessor for Desktop
PC and Motherboard
Low Output Voltage, High power density DC-DC
Converters
Voltage Regulator Modules
Pin Configurations
`
Suitable for use in SnPb or Pb-free soldering processes.
VID4
VID5
VID6
29
28
27
26
25
24
2
23
FBRTN
FB
COMP
3
22
SS
VR_FAN
6
VR_HOT
8
4
21
GND
5
20
19
7
18
33
17
TSEN
9
10
11
12
13
14
15
16
ISN23
ments of IPC/JEDEC J-STD-020.
30
ISN1
RoHS compliant and compatible with the current require-
31
1
IMAX
`
32
VTT/EN
VR_Ready
ADJ
Richtek products are :
VID3
Note :
VID2
(TOP VIEW)
Lead Plating System
P : Pb Free
G : Green (Halogen Free and Pb Free)
VID1
Package Type
QV : VQFN-32L 5x5 (V-Type)
z
OFS
RT8803A
z
VID0
Ordering Information
z
RT
Other features include over current protection, programmable
soft start, over voltage protection, and output offset setting.
RT8803A comes to a small footprint package with
VQFN-32L 5x5.
z
VID_SEL
methods. As sub-milli-ohm-grade inductors are widely used
in modern motherboards, slight offset and linearity mismatch
will cause considerable current shift between phases. This
technique ensures good current balance at mass production.
z
DVD
RT8803A adopts innovative time-sharing DCR current sensing
technique to sense phase currents for phase current balance,
load line setting and over current protection. Using a common
GM to sense all phase currents eliminates offset and linearity
variation between GMs in conventional current sensing
z
VID7
VDD
PWM3
PWM2
PWM1
ISP1
ISP2
ISP3
VQFN-32L 5x5
DS8803A-06 April 2011
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1
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2
For AMD
PGOOD
VDDIO
VTT/EN
For Intel
VR_FAN
VTT
VR_HOT
Enable
R3
1.1k
VR_Ready
R4 R5 R6
10k 10k 10k
2
360
R22
R10 0
R9
NC
R8
NC
0.1uF
CPU_VSS
BTX_5V
ISP3 17
ISP1 19
18
ISP2
R7
BTX_5V
75k
R21
ISN1 15
ISN23
C2
3 12 9
OFS
7
FBRTN
8
TSEN
1
PWM1
R2 10k
C1
0.1uF
GND
360
R20
R17 0
16
PWM3 22
R18
75k
R16
1.5k
R15 C6
15k 2.2nF
PWM2
BTX_12V
R1 10
RT
BTX_5V
VID7
GND
For K8_M2
IMAX
RT8803A
SS
For K8
VID_SEL
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7
VDD
DVD
C7
470pF
C5
5.6pF
6 5 4 20 21
COMP
VDDIO
32
31
30
29
28
27
26
25
24
23
10
13 11 14
C4
56nF
FB
VID0
VID1
VID2
VID3
VID4
VID5
VID6
For Intel
For AMD
R12
300
ADJ
VID_SEL
BTX_5V
C3
56nF
R11
300
R13 R14
12k 8.2k
R33
R23
360
C8
1uF
R19
R24
360
C92
1uF
R25
NC
100
VCORE1
VCORE23
R26
360
C10
1uF
CPU_VCC
C25
0.1uF
C19
1N4148
VIN
C27
C30
1uF
IPS06N03LA
IPD09N03LA
4.7uF
C28
IPS06N03LA
IPD09N03LA
4.7uF
C21
IPS06N03LA
1200uF 4.7uF
C26
C23
1uF
4.7uF
C14
IPD09N03LA
C20
C16
1uF
1200uF 4.7uF
1
BOOT
3
8
NC
UGATE
7
4 VCC
PHASE
RT9619
5
LGATE
2
VIN
PGND
6
R31
10
BTX_12V
C18
0.1uF
1N4148
VIN
1
BOOT
3
8
NC
UGATE
7
4 VCC
PHASE
RT9619
5
LGATE
2
VIN
PGND
6
R29
10
BTX_12V
C11
0.1uF
1N4148
C13
1200uF 4.7uF
C12
VIN
1
BOOT
3
8
NC
UGATE
7
4 VCC
PHASE
RT9619
5
LGATE
2
PWM
PGND
6
R27
10
BTX_12V
BTX_12V
Q8
Q7
4.7uF
C29
Q5
Q4
4.7uF
C22
Q2
Q1
C15
4.7uF
Q9
Q6
Q3
R32
2.2
C31
3.3nF
R30
2.2
C24
3.3nF
R28
2.2
C17
3.3nF
2k
RT1 10k
NTC
L3
280nH
VCORE23
L2
280nH
VCORE23 VCC
L1
280nH
RT2
NTC
C42 to C59
10uF x 18
C32 to C41
560uF x 10
VSS
VCORE1
RT8803A
Typical Application Circuit
DS8803A-06 April 2011
RT8803A
Functional Pin Description
OFS (Pin 12)
VTT/EN (Pin 1)
The pin is defined for load line offset setting.
The pin is defined as the chip enable, and the VTT is
applied for internal VID pull high power and power sequence
monitoring.
ADJ (Pin 13)
Current sense output for active droop adjusting. Connect
a resistor from this pin to GND to set the load droop.
VR_Ready (Pin 2)
Power good open-drain output.
IMAX (Pin 14)
The pin is defined to set threshold of over current.
FBRTN (Pin 3)
Feedback return pin. VID DAC and error amplifier reference
for remote sensing of the output voltage.
ISN1 (Pin 15)
Current sense negative input pin for channel 1 current
sensing.
FB (Pin 4)
Inverting input pin of the internal error amplifier.
ISN23 (Pin 16)
COMP (Pin 5)
Current sense negative input pins for channel 2 and
channel 4 current sensing.
Output pin of the error amplifier and input pin of the PWM
comparator.
ISP1 (Pin 19), ISP2 (Pin 18), ISP3 (Pin 17)
SS (Pin 6)
Current sense positive input pins for individual converter
channel current sensing.
Connect this SS pin to GND with a capacitor to set the
soft-start time interval.
PWM1 (Pin 20), PWM2 (Pin 21), PWM3 (Pin 22)
The pin is defined to signal VR thermal information for
external VR thermal dissipation scheme triggering.
PWM outputs for each driven channel. Connect these pins
to the PWM input of the MOSFET driver. For systems
which using 2/3/4 channels, pull PWM 3/4/5 pins up to
high.
VR_HOT (Pin 8)
VDD (Pin 23)
The pin is defined to signal VR thermal information for
external VR thermal dissipation scheme triggering.
IC power supply. Connect this pin to a 5V supply.
VR_FAN (Pin 7)
Temperature detect pin for VR_HOT and VR_FAN.
VID7 (Pin 24), VID6 (Pin 25), VID5 (Pin 26), VID4 (Pin
27), VID3 (Pin 28), VID2 (Pin 29), VID1 (Pin 30),
VID0 (Pin 31), VID_SEL (32)
DVD (Pin 10)
DAC voltage identification inputs for VRD10.x / VRD11 /
K8 / K8_M2 . These pins are internally pulled up to VTT.
TSEN (Pin 9)
Programmable power UVLO detection input. Trip threshold
is 1V at VDVD rising.
RT (Pin 11)
The pin is defined to set internal switching operation
frequency. Connect this pin to GND with a resistor RRT to
set the frequency FSW.
FSW =
4.463 e 9
RRT + 3500
DS8803A-06 April 2011
VIDSEL
VTT
GND
VDD
VDD
VID [7]
X
X
NC
GND
Table
VR11
VR10.x
K8
K8_M2
GND [Exposed pad (33)]
The exposed pad must be soldered to a large PCB and
connected to GND for maximum power dissipation.
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3
RT8803A
Function Block Diagram
VDD
SS
VR_Ready
VTT/EN
DVD
Oscillator
&
Ramp
Generator
Power On
Reset
Soft Start
& PGOOD
RT
COMP
FB
OFS
-
DAC
Clamp
EA
+
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VID_SEL
Pulse
Width
Modulator
& Output
Buffer
Current
Processing
SUM/N
& OCP
Detection
PWM1
PWM2
PWM3
IMAX
FBRTN
Mux
ISN1
ISN23
-
CSA
+
TSEN
VR_FAN
Temperature
Processing
Droop Tune
& Hi-I
Detection
Sample
& Hold
Mux
ISP2
ISP3
VR_HOT
ADJ
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4
ISP1
Mux
GND
DS8803A-06 April 2011
RT8803A
Table 1. Output Voltage Program (VRD10.x + VID6)
Pin Name
Nominal Output Voltage DACOUT
VID4
VID3
VID2
VID1
VID0
VID5
VID6
0
1
0
1
0
1
1
1.60000V
0
1
0
1
0
1
0
1.59375V
0
1
0
1
1
0
1
1.58750V
0
1
0
1
1
0
0
1.58125V
0
1
0
1
1
1
1
1.57500V
0
1
0
1
1
1
0
1.56875V
0
1
1
0
0
0
1
1.56250V
0
1
1
0
0
0
0
1.55625V
0
1
1
0
0
1
1
1.55000V
0
1
1
0
0
1
0
1.54375V
0
1
1
0
1
0
1
1.53750V
0
1
1
0
1
0
0
1.53125V
0
1
1
0
1
1
1
1.52500V
0
1
1
0
1
1
0
1.51875V
0
1
1
1
0
0
1
1.51250V
0
1
1
1
0
0
0
1.50625V
0
1
1
1
0
1
1
1.50000V
0
1
1
1
0
1
0
1.49375V
0
1
1
1
1
0
1
1.48750V
0
1
1
1
1
0
0
1.48125V
0
1
1
1
1
1
1
1.47500V
0
1
1
1
1
1
0
1.46875V
1
0
0
0
0
0
1
1.46250V
1
0
0
0
0
0
0
1.45625V
1
0
0
0
0
1
1
1.45000V
1
0
0
0
0
1
0
1.44375V
1
0
0
0
1
0
1
1.43750V
1
0
0
0
1
0
0
1.43125V
1
0
0
0
1
1
1
1.42500V
1
0
0
0
1
1
0
1.41875V
1
0
0
1
0
0
1
1.41250V
1
0
0
1
0
0
0
1.40625V
1
0
0
1
0
1
1
1.40000V
1
0
0
1
0
1
0
1.39375V
1
0
0
1
1
0
1
1.38750V
1
0
0
1
1
0
0
1.38125V
1
0
0
1
1
1
1
1.37500V
1
0
0
1
1
1
0
1.36875V
1
0
1
0
0
0
1
1.36250V
To be continued
DS8803A-06 April 2011
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5
RT8803A
Table 1. Output Voltage Program (VRD10.x + VID6)
Pin Name
Nominal Output Voltage DACOUT
VID4
VID3
VID2
VID1
VID0
VID5
VID6
1
0
1
0
0
0
0
1.35625V
1
0
1
0
0
1
1
1.35000V
1
0
1
0
0
1
0
1.34375V
1
0
1
0
1
0
1
1.33750V
1
0
1
0
1
0
0
1.33125V
1
0
1
0
1
1
1
1.32500V
1
0
1
0
1
1
0
1.31875V
1
0
1
1
0
0
1
1.31250V
1
0
1
1
0
0
0
1.30625V
1
0
1
1
0
1
1
1.30000V
1
0
1
1
0
1
0
1.29375V
1
0
1
1
1
0
1
1.28750V
1
0
1
1
1
0
0
1.28125V
1
0
1
1
1
1
1
1.27500V
1
0
1
1
1
1
0
1.26875V
1
1
0
0
0
0
1
1.26250V
1
1
0
0
0
0
0
1.25625V
1
1
0
0
0
1
1
1.25000V
1
1
0
0
0
1
0
1.24375V
1
1
0
0
1
0
1
1.23750V
1
1
0
0
1
0
0
1.23125V
1
1
0
0
1
1
1
1.22500V
1
1
0
0
1
1
0
1.21875V
1
1
0
1
0
0
1
1.21250V
1
1
0
1
0
0
0
1.20625V
1
1
0
1
0
1
1
1.20000V
1
1
0
1
0
1
0
1.19375V
1
1
0
1
1
0
1
1.18750V
1
1
0
1
1
0
0
1.18125V
1
1
0
1
1
1
1
1.17500V
1
1
0
1
1
1
0
1.16875V
1
1
1
0
0
0
1
1.16250V
1
1
1
0
0
0
0
1,15625V
1
1
1
0
0
1
1
1.15000V
1
1
1
0
0
1
0
1.14375V
1
1
1
0
1
0
1
1.13750V
1
1
1
0
1
0
0
1.13125V
1
1
1
0
1
1
1
1.12500V
1
1
1
0
1
1
0
1.11875V
To be continued
www.richtek.com
6
DS8803A-06 April 2011
RT8803A
Table 1. Output Voltage Program (VRD10.x + VID6)
Pin Name
Nominal Output Voltage DACOUT
VID4
VID3
VID2
VID1
VID0
VID5
VID6
1
1
1
1
0
0
1
1.11250V
1
1
1
1
0
0
0
1.10625V
1
1
1
1
0
1
1
1.10000V
1
1
1
1
0
1
0
1.09375V
1
1
1
1
1
0
1
OFF
1
1
1
1
1
0
0
OFF
1
1
1
1
1
1
1
OFF
1
1
1
1
1
1
0
OFF
0
0
0
0
0
0
1
1.08750V
0
0
0
0
0
0
0
1.08125V
0
0
0
0
0
1
1
1.07500V
0
0
0
0
0
1
0
1.06875V
0
0
0
0
1
0
1
1.06250V
0
0
0
0
1
0
0
1.05625V
0
0
0
0
1
1
1
1.05000V
0
0
0
0
1
1
0
1.04375V
0
0
0
1
0
0
1
1.03750V
0
0
0
1
0
0
0
1.03125V
0
0
0
1
0
1
1
1.02500V
0
0
0
1
0
1
0
1.01875V
0
0
0
1
1
0
1
1.01250V
0
0
0
1
1
0
0
1.00625V
0
0
0
1
1
1
1
1.00000V
0
0
0
1
1
1
0
0.99375V
0
0
1
0
0
0
1
0.98750V
0
0
1
0
0
0
0
0.98125V
0
0
1
0
0
1
1
0.97500V
0
0
1
0
0
1
0
0.96875V
0
0
1
0
1
0
1
0.96250V
0
0
1
0
1
0
0
0.95625V
0
0
1
0
1
1
1
0.95000V
0
0
1
0
1
1
0
0.94375V
0
0
1
1
0
0
1
0.93750V
0
0
1
1
0
0
0
0.93125V
0
0
1
1
0
1
1
0.92500V
0
0
1
1
0
1
0
0.91875V
0
0
1
1
1
0
1
0.91250V
0
0
1
1
1
0
0
0.90625V
0
0
1
1
1
1
1
0.90000V
To be continued
DS8803A-06 April 2011
www.richtek.com
7
RT8803A
Table 1. Output Voltage Program (VRD10.x + VID6)
Pin Name
Nominal Output Voltage DACOUT
VID4
VID3
VID2
VID1
VID0
VID5
VID6
0
0
1
1
1
1
0
0.89375V
0
1
0
0
0
0
1
0.88750V
0
1
0
0
0
0
0
0.88125V
0
1
0
0
0
1
1
0.87500V
0
1
0
0
0
1
0
0.86875V
0
1
0
0
1
0
1
0.86250V
0
1
0
0
1
0
0
0.85625V
0
1
0
0
1
1
1
0.85000V
0
1
0
0
1
1
0
0.84375V
0
1
0
1
0
0
1
0.83750V
0
1
0
1
0
0
0
0.83125V
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8
DS8803A-06 April 2011
RT8803A
Table 2. Output Voltage Program (VRD11)
Pin Name
Nominal Output Voltage DACOUT
Pin Name
Nominal Output Voltage DACOUT
OFF
HEX
27
1.36875V
01
OFF
28
1.36250V
02
1.60000V
29
1.35625V
03
1.59375V
2A
1.35000V
04
1.58750V
2B
1.34375V
05
1.58125V
2C
1.33750V
06
1.57500V
2D
1.33125V
07
1.56875V
2E
1.32500V
08
1.56250V
2F
1.31875V
09
1.55625V
30
1.31250V
0A
1.55000V
31
1.30625V
0B
1.54375V
32
1.30000V
0C
1.53750V
33
1.29375V
0D
1.53125V
34
1.28750V
0E
1.52500V
35
1.28125V
0F
1.51875V
36
1.27500V
10
1.51250V
37
1.26875V
11
1.50625V
38
1.26250V
12
1.50000V
39
1.25625V
13
1.49375V
3A
1.25000V
14
1.48750V
3B
1.24375V
15
1.48125V
3C
1.23750V
16
1.47500V
3D
1.23125V
17
1.46875V
3E
1.22500V
18
1.46250V
3F
1.21875V
HEX
00
19
1.45625V
40
1.21250V
1A
1.45000V
41
1.20625V
1B
1.44375V
42
1.20000V
1C
1.43750V
43
1.19375V
1D
1.43125V
44
1.18750V
1E
1.42500V
45
1.18125V
1F
1.41875V
46
1.17500V
20
1.41250V
47
1.16875V
21
1.40625V
48
1.16250V
22
1.40000V
49
1.15625V
23
1.39375V
4A
1.15000V
24
1.38750V
4B
1.14375V
25
1.38125V
4C
1.13750V
26
1.37500V
4D
1.13125V
To be continued
DS8803A-06 April 2011
www.richtek.com
9
RT8803A
Table 2. Output Voltage Program (VRD11)
Pin Name
HEX
4E
4F
Nominal Output Voltage DACOUT
Pin Name
Nominal Output Voltage DACOUT
1.12500V
HEX
75
0.88125V
1.11875V
76
0.87500V
50
1.11250V
77
0.86875V
51
1.10625V
78
0.86250V
52
1.10000V
79
0.85625V
53
1.09375V
7A
0.85000V
54
1.08750V
7B
0.84375V
55
1.08125V
7C
0.83750V
56
1.07500V
7D
0.83125V
57
1.06875V
7E
0.82500V
58
1.06250V
7F
0.81875V
59
1.05625V
80
0.81250V
5A
1.05000V
81
0.80625V
5B
1.04375V
82
0.80000V
5C
1.03750V
83
0.79375V
5D
1.03125V
84
0.78750V
5E
1.02500V
85
0.78125V
5F
1.01875V
86
0.77500V
60
1.01250V
87
0.76875V
61
1.00625V
88
0.76250V
62
1.00000V
89
0.75625V
63
0.99375V
8A
0.75000V
64
0.98750V
8B
0.74375V
65
0.98125V
8C
0.73750V
66
0.97500V
8D
0.73125V
67
0.96875V
8E
0.72500V
68
0.96250V
8F
0.71875V
69
0.95625V
90
0.71250V
6A
0.95000V
91
0.70625V
6B
0.94375V
92
0.70000V
6C
0.93750V
93
0.69375V
6D
0.93125V
94
0.68750V
6E
0.92500V
95
0.68125V
6F
0.91875V
96
0.67500V
70
0.91250V
97
0.66875V
71
0.90625V
98
0.66250V
72
0.90000V
99
0.65625V
73
0.89375V
9A
0.65000V
74
0.88750V
9B
0.64375V
To be continued
www.richtek.com
10
DS8803A-06 April 2011
RT8803A
Table 2. Output Voltage Program (VRD11)
Pin Name
HEX
9C
9D
Nominal Output Voltage DACOUT
Pin Name
Nominal Output Voltage DACOUT
0.63750V
HEX
C3
X
0.63125V
C4
X
9E
0.62500V
C5
X
9F
0.61875V
C6
X
A0
0.61250V
C7
X
A1
0.60625V
C8
X
A2
0.60000V
C9
X
A3
0.59375V
CA
X
A4
0.58750V
CB
X
A5
0.58125V
CC
X
A6
0.57500V
CD
X
A7
0.56875V
CE
X
A8
0.56250V
CF
X
A9
0.55625V
D0
X
AA
0.55000V
D1
X
AB
0.54375V
D2
X
AC
0.53750V
D3
X
AD
0.53125V
D4
X
AE
0.52500V
D5
X
AF
0.51875V
D6
X
B0
0.51250V
D7
X
B1
0.50625V
D8
X
B2
0.50000V
D9
X
B3
X
DA
X
B4
X
DB
X
B5
X
DC
X
B6
X
DD
X
B7
X
DE
X
B8
X
DF
X
B9
X
E0
X
BA
X
E1
X
BB
X
E2
X
BC
X
E3
X
BD
X
E4
X
BE
X
E5
X
BF
X
E6
X
C0
X
E7
X
C1
X
E8
X
C2
X
E9
X
To be continued
DS8803A-06 April 2011
www.richtek.com
11
RT8803A
Table 2. Output Voltage Program (VRD11)
Pin Name
Nominal Output Voltage DACOUT
HEX
EA
X
EB
X
EC
X
ED
X
EE
X
EF
X
F0
X
F1
X
F2
X
F3
X
F4
X
F5
X
F6
X
F7
X
F8
X
F9
X
FA
X
FB
X
FC
X
FD
X
FE
OFF
FF
OFF
Note: (1) 0 : Connected to GND
(2) 1 : Open
(3) X : Don't Care
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12
DS8803A-06 April 2011
RT8803A
Table 3. Output Voltage Program (K8)
VID4
VID3
VID2
VID1
VID0
Nominal Output Voltage DACOUT
0
0
0
0
0
1.550
0
0
0
0
1
1.525
0
0
0
1
0
1.500
0
0
0
1
1
1.475
0
0
1
0
0
1.450
0
0
1
0
1
1.425
0
0
1
1
0
1.400
0
0
1
1
1
1.375
0
1
0
0
0
1.350
0
1
0
0
1
1.325
0
1
0
1
0
1.200
0
1
0
1
1
1.275
0
1
1
0
0
1.250
0
1
1
0
1
1.225
0
1
1
1
0
1.200
0
1
1
1
1
1.175
1
0
0
0
0
1.150
1
0
0
0
1
1.125
1
0
0
1
0
1.100
1
0
0
1
1
1.075
1
0
1
0
0
1.050
1
0
1
0
1
1.025
1
0
1
1
0
1.000
1
0
1
1
1
0.975
1
1
0
0
0
0.950
1
1
0
0
1
0.925
1
1
0
1
0
0.900
1
1
0
1
1
0.875
1
1
1
0
0
0.850
1
1
1
0
1
0.825
1
1
1
1
0
0.800
1
1
1
1
1
Shutdown
Note: (1) 0 : Connected to GND
(2) 1 : Open
DS8803A-06 April 2011
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13
RT8803A
Table 4. Output Voltage Program (K8_M2)
Pin Name
Nominal Output Voltage DACOUT
VID5
VID4
VID3
VID2
VID1
VID0
0
0
0
0
0
0
1.5500
0
0
0
0
0
1
1.5250
0
0
0
0
1
0
1.5000
0
0
0
0
1
1
1.4750
0
0
0
1
0
0
1.4500
0
0
0
1
0
1
1.4250
0
0
0
1
1
0
1.4000
0
0
0
1
1
1
1.3750
0
0
1
0
0
0
1.3500
0
0
1
0
0
1
1.3250
0
0
1
0
1
0
1.3000
0
0
1
0
1
1
1.2750
0
0
1
1
0
0
1.2500
0
0
1
1
0
1
1.2250
0
0
1
1
1
0
1.2000
0
0
1
1
1
1
1.1750
0
1
0
0
0
0
1.1500
0
1
0
0
0
1
1.1250
0
1
0
0
1
0
1.1000
0
1
0
0
1
1
1.0750
0
1
0
1
0
0
1.0500
0
1
0
1
0
1
1.0250
0
1
0
1
1
0
1.0000
0
1
0
1
1
1
0.9750
0
1
1
0
0
0
0.9500
0
1
1
0
0
1
0.9250
0
1
1
0
1
0
0.9000
0
1
1
0
1
1
0.8750
0
1
1
1
0
0
0.8500
0
1
1
1
0
1
0.8250
0
1
1
1
1
0
0.8000
0
1
1
1
1
1
0.7750
1
0
0
0
0
0
0.7625
1
0
0
0
0
1
0.7500
To be continued
www.richtek.com
14
DS8803A-06 April 2011
RT8803A
Table 4. Output Voltage Program (K8_M2)
Pin Name
Nominal Output Voltage DACOUT
VID5
VID4
VID3
VID2
VID1
VID0
1
0
0
0
1
0
0.7375
1
0
0
0
1
1
0.7250
1
0
0
1
0
0
0.7125
1
0
0
1
0
1
0.7000
1
0
0
1
1
0
0.6875
1
0
0
1
1
1
0.6750
1
0
1
0
0
0
0.6625
1
0
1
0
0
1
0.6500
1
0
1
0
1
0
0.6375
1
0
1
0
1
1
0.6250
1
0
1
1
0
0
0.6125
1
0
1
1
0
1
0.6000
1
0
1
1
1
0
0.5875
1
0
1
1
1
1
0.5750
1
1
0
0
0
0
0.5625
1
1
0
0
0
1
0.5500
1
1
0
0
1
0
0.5375
1
1
0
0
1
1
0.5250
1
1
0
1
0
0
0.5125
1
1
0
1
0
1
0.5000
1
1
0
1
1
0
0.4875
1
1
0
1
1
1
0.4750
1
1
1
0
0
0
0.4625
1
1
1
0
0
1
0.4500
1
1
1
0
1
0
0.4375
1
1
1
0
1
1
0.4250
1
1
1
1
0
0
0.4125
1
1
1
1
0
1
0.4000
1
1
1
1
1
0
0.3875
1
1
1
1
1
1
0.3750
Note: (1) 0 : Connected to GND
(2) 1 : Open
(3) The voltage above are load independent for desktop and server platforms. For mobile platforms the voltage above
correspond to zero load current.
DS8803A-06 April 2011
www.richtek.com
15
RT8803A
Absolute Maximum Ratings
z
z
z
z
z
z
z
z
(Note 1)
Supply Voltage, VDD -----------------------------------------------------------------------------------------Input, Output or I/O Voltage -------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C
VQFN−32L 5x5 -----------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2)
VQFN-32L 5x5, θJA ------------------------------------------------------------------------------------------Junction Temperature ---------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) -----------------------------------------------------------------Storage Temperature Range -------------------------------------------------------------------------------ESD Susceptibility (Note 3)
HBM (Human Body Mode) ---------------------------------------------------------------------------------MM (Machine Mode) -----------------------------------------------------------------------------------------
Recommended Operating Conditions
z
z
z
7V
GND-0.3V to VDD+0.3V
2.778W
36°C/W
150°C
260°C
−65°C to 150°C
2kV
200V
(Note 4)
Supply Voltage, VDD ------------------------------------------------------------------------------------------ 5V ± 10%
Junction Temperature Range ------------------------------------------------------------------------------- −40°C to 125°C
Ambient Temperature Range ------------------------------------------------------------------------------- −40°C to 85°C
Electrical Characteristics
(VDD = 5V, TA = 25° C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
--
12
16
mA
4.0
4.2
4.5
V
0.2
0.5
--
V
0.9
1.0
1.1
V
--
60
--
mV
0.75
0.85
0.95
--
0.1
--
180
200
220
kHz
50
--
400
kHz
--
1.9
--
V
0.7
1.0
--
V
62
67
72
%
0.9
1.0
1.1
V
VD D Supply Current
Nominal Supply Current
IDD
PWM 1,2,3 Open
POR Threshold
VDDRTH
VDD Rising
Hysteresis
VDDHYS
Power-On Reset
V DVD Threshold
V TT Threshold
Trip (Low to High)
VDVDTH
Hysteresis
VDVDHYS
Trip (Low to High)
VTTTH
Hysteresis
VTTHYS
Enable
Enable
V
Oscillator
Free Running Frequency
fOSC
Frequency Adjustable Range
fOSC_ADJ
Ramp Amplitude
ΔVOSC
Ramp Valley
VRV
Maximum On-Time of Each Channel
RT Pin Voltage
RRT = 20kΩ
RRT = 20kΩ
Three Phase Operation
VRT
RRT = 20kΩ
To be continued
www.richtek.com
16
DS8803A-06 April 2011
RT8803A
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
VDAC ≥ 1V
−0.5
--
0.5
%
1V ≥ VDAC ≥ 0.8V
−5
--
5
mV
VDAC < 0.8V
−8
--
8
mV
Reference and DAC
DACOUT Voltage Accuracy
ΔV DAC
DAC (VID0-VID125) Input Low
VILDAC
--
--
1/2VTT − 0.2
V
DAC (VID0-VID125) Input High
VIHDAC
1/2VTT + 0.2
--
--
V
12
15
18
kΩ
0.9
1.0
1.1
V
--
65
--
dB
--
10
--
MHz
--
8
--
V/μs
100
--
--
μA
150
--
--
μA
100
150
200
mV
0.9
1.0
1.1
V
--
--
0.2
V
V ID Pull-up Resistance
OFS Pin Voltage
VOFS
ROFS = 100kΩ
Error Amplifier
DC Gain
Gain-Bandwidth Product
GBW
Slew Rate
SR
COMP = 10pF
Current Sense GM Amplifier
CSN Full Scale Source Current
IISPFSS
CSN Current for OCP
Protection
Over-Voltage Trip (FB-DACOUT)
ΔOVT
IMAX Voltage
VIMAX
RIMAX = 20k
VPGOODL
IPGOOD = 4mA
Power Good
Output Low Voltage
Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. θ JA is measured in the natural convection at T A = 25°C on a low effective thermal conductivity test board of
JEDEC 51-3 thermal measurement standard.
Note 3. Devices are ESD sensitive. Handling precaution recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
DS8803A-06 April 2011
www.richtek.com
17
RT8803A
Typical Operating Characteristics
Frequency vs. RRT
GM
700
450
400
600
Positive Duty (ns)
Frequency (kHz)
350
500
400
300
200
300
250
PHASE 3
PHASE 1
PHASE 2
200
150
100
100
50
0
0
0
10
20
30
40
50
60
70
80
90
100
0
25
50
75
(kΩ)
RRT (k
ٛ)
Output Voltage vs. Temperature
125
150
175
200
Frequency vs. Temperature
1.264
322
1.262
320
318
1.26
Frequency (kHz)
Output Voltage (V)
100
ISN (uA)
1.258
1.256
1.254
1.252
316
314
312
310
308
1.25
306
1.248
304
-20
0
20
40
60
80
100
-20
20
40
60
Temperature (°C)
Power On from DVD
Power Off from DVD
DVD
(1V/Div)
DVD
(1V/Div)
SS
(1V/Div)
VOUT
(1V/Div)
SS
(1V/Div)
80
100
VOUT
(1V/Div)
PHASE 3
(10V/Div)
PHASE 3
(10V/Div)
Time (1ms/Div)
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18
0
Temperature (°C)
Time (1μs/Div)
DS8803A-06 April 2011
RT8803A
Power On from VCC12
Power Off from VCC12
VCC12
(10V/Div)
SS
(1V/Div)
VCC12
(10V/Div)
SS
(1V/Div)
VOUT
(1V/Div)
VOUT
(1V/Div)
PHASE 3
(10V/Div)
PHASE 3
(10V/Div)
Time (1ms/Div)
Time (1ms/Div)
Power On from VCC5
Power Off from VCC5
VCC5
(5V/Div)
SS
(1V/Div)
VCC5
(5V/Div)
SS
(1V/Div)
VOUT
(1V/Div)
VOUT
(1V/Div)
PHASE 3
(10V/Div)
PHASE 3
(10V/Div)
Time (1ms/Div)
Time (25ms/Div)
Power On with OCP
Output Short Circuit
VR_Ready
(1V/Div)
VR_Ready
(1V/Div)
SS
(2V/Div)
SS
(2V/Div)
VOUT
1V/Div)
VOUT
(1V/Div)
PWM
(5V/Div)
PWM
(5V/Div)
Time (500μs/Div)
DS8803A-06 April 2011
Time (1ms/Div)
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19
RT8803A
VOUT Overshoot
VOUT Droop
VOUT
(20mV/Div)
VOUT
(20mV/Div)
IOUT
(40A/Div)
IOUT
(40A/Div)
Time (2μs/Div)
Time (2μs/Div)
Dynamic VID
Dynamic VID
VOUT
(200mV/Div)
VOUT
(200mV/Div)
VID0
(500mV/Div)
VID0
(500mV/Div)
Time (50μs/Div)
Time (50μs/Div)
OVP
VR_Ready
(1V/Div)
SS
(2V/Div)
FB
(1V/Div)
PWM
(5V/Div)
Time (10μs/Div)
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20
DS8803A-06 April 2011
RT8803A
Applications Information
RT8803A is a multi-phase DC/DC controller specifically
designed to deliver high quality power for next generation
CPU. RT8803A controls a special power-on sequence &
monitors the thermal condition of VR module to meet the
VRD11 requirement. Phase currents are sensed by
innovative time-sharing DCR current sensing technique
for channel current balance, droop tuning, and over current
protection. Using one common GM amplifier for current
sensing eliminates offset errors and linearity variation
between GMs. As sub-milli-ohm-grade inductors are
widely used in modern mother boards, slight mismatch
of GM amplifiers offset and linearity results in considerable
current shift between phases. The time-sharing DCR
current sensing technique is extremely important to
guarantee phase current balance in mass production.
Converter Initialization, Phase Selection, and
Power Good Function
The RT8803A initiates only after 3 pins are ready: VDD
pin power on reset (POR), VTT/EN pin enabled, and DVD
pin is higher than 1V. VDD POR is to make sure RT8803A
is powered by a voltage for normal work. The rising
threshold voltage of VDD POR is 4.2V typically. At VDD
POR, RT8803A checks PWM3, PWM4 and PWM5 status
to determine phase number of operation. Pull high PWM3
for two-phase operation; pull high PWM4 for three-phase
operation; pull high PWM5 for four-phase operation. The
unused current sense pins should be connected to GND
or left floating.
VTT/EN acts as a chip enable pin and receives signal from
FSB or other power management IC.
DVD is to make sure that ATX12V is ready for drivers to
work normally. Connect a voltage divider from ATX12V to
DVD pin as shown in the Typical Application Circuit. Make
sure that DVD pin voltage is below its threshold voltage
before drivers are ready and above its threshold voltage
for minimum ATX12V during normal operation.
with Intel®VRD11 specification as shown in Figure 1. A
time-variant internal current source charges the capacitor
connected to SS pin. SS voltage ramps up piecewise
linearly and locks VID_DAC output with a specified voltage
drop. Consequently, VCORE is built up according to
VID_DAC output and meet Intel® VRD11 requirement.
VR_READY output is pulled high by external resistor when
VCORE reaches VID_DAC output with 1~2ms delay. An
SS capacitor about 47nF is recommend for VRD11
compliance.
VDD POR, DVD, and VTT/EN ready
SS
VCORE
1.1V
VR_Ready
VID on the fly
1~2ms
1~2ms
1~2ms
1~2ms
1~2ms
Figure 1. Timming Diagram During Soft Start Interval
Voltage Control
CPU VCORE voltage is Kelvin sensed by FB and FBRTN
pins and precisely regulated to VID_DAC output by internal
high gain Error Amplifier (EA). The sensed signal is also
used for power good and over voltage function. The typical
OVP trip point is 170mV above VID_DAC output. RT8803A
pulls PWM outputs low and latches up upon OVP trip to
prevent damaging the CPU. It can only restart by resetting
one of VDD, DVD, or VTT/EN pin.
RT8803A supports Intel VRD10.x, VRD11, AMD K8 and
AMD K8_M2 VID specification.
The change of VID_DAC output at VID on the fly is also
smoothed by capacitor connected to SS pin.
Consequently, Vcore shifts to its new position smoothly
as shown in Figure 2.
If any one of VDD, VTT/EN, and DVD is not ready, RT8803A
keeps its PWM outputs high impedance and the
companion drivers turn off both upper and lower
MOSFETs. After VDD, VTT/EN, and DVD are ready,
RT8803A initiates its soft start cycle that is compliant
DS8803A-06 April 2011
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21
RT8803A
Consequently, the sensing current IX is proportional to
inductor current ILX and is expressed as :
I × DCRx
I X = LX
R CSNX
The sensed current IX is used for current balance and droop
tuning as described as followed. Since all phases share
one common GM, GM offset and linearity variation effect
is eliminated in practical applications. As sub-milli-ohmgrade inductors are widely used in modern mother boards,
slight mismatch of GM amplifiers offset and linearity results
in considerable current shift between phases. The timesharing DCR current sensing technical is extremely
important to guarantee phase current balance in mass
production.
PWM3
VCORE
VID7
Figure 2. Vcore Response at VID on the Fly
DCR Current Sensing
RT8803A adopts an innovative time-sharing DCR current
sensing technique to sense the phase currents for phase
current balance (phase thermal balance) and load line
regulation as shown in Figure 3. Current sensing amplifier
GM samples and holds voltages VCx across the current
sensing capacitor Cx by turns in a switching cycle.
According to the Basic Circuit Theory, if
Lx = Rx × Cx then VCx = I × DCRx
LX
DCRx
Phase Current Balance
The sampled and held phase current IX are summed and
averaged to get the averaged current IX . Each phase
current IX then is compared with the averaged current.
The difference between I X and IX is injected to
corresponding PWM comparator. If phase current IX is
smaller than the averaged current , RT8803A increases
the duty cycle of corresponding phase to increase the
phase current accordingly and vice versa.
T1
L1
DCR1
R1
C1
+ VC1 -
T2
T3
IX = ILX x DCRX/RCSNX
IX
S/H CKT
L3
DCR3
R3
C3
+ VC3 -
ISP1
+
CSA
-
T1
ISN1
T1
RCSN1
ISP3
CSA: Current Sense Amplifier
T3
T3
ISN23
RCSN3
L2
DCR2
R2
C2
+ VC2 -
ISP2
T2
T2
ISN23
RCSN2
Figure 3
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22
DS8803A-06 April 2011
RT8803A
IOFS
4
If
LX
= (R X //RPX ) × Cx then
DCRx
VCx =
RFB1
VCORE
+
EA
COMP
VADJ
4IX
+
-
DAC
RADJ
RPX
× ILX × DCRx
Rx + RPX
With other phase kept unchanged, this phase would share
(RPX+Rx)/RPX times current than other phases. Figure 6
and 7 show different current ratio setting for the power
stage when Phase 3 is programmed 2 times current than
other phases. Figure 8 and 9 compare the above current
ratio setting results.
Figure 4. Load Line and Offset Function
LX
Output Voltage Offset Function
DCRx
®
VCORE = VDAC − VADJ +
Rx
+
VCx
-
Cx
RPX
+
To meet Intel requirement of initial offset of load line,
RT8803A provides programmable initial offset function.
External resistor ROFS and voltage source at OFS pin
V
generate offset current IOFS = OFS
R OFS
, where VOFS is 1V typical. One quarter of IOFS flows
through RFB1 as shown in Figure 4. Error amplifier would
hold the inverting pin equal to VDAC - VADJ. Thus output
voltage is subtracted from VDAC - VADJ for a constant offset
voltage.
RFB1
VCORE = VDAC − VADJ −
4 × R OFS
A positive output voltage offset is possible by connecting
ROFS to VDD instead of to GND. Please note that when
ROFS is connected to VDD, VOFS is VDD − 2V typically and
half of IOFS flows through RFB1. VCORE is rewritten as :
ILX
VOUT
T
Figure 5
RFB1
R OFS
Current Ratio Setting
Current ratio adjustment is possible as described below.
It is important for achieving thermal balance in practical
application where thermal conditions between phases are
not identical. Figure 5 shows the application circuit of GM
for current ratio requirement. According to Basic Circuit
Theory
RPX
Rx + RPX
VCx =
× ILX × DCRx
SRx × RPX × Cx
+1
Rx + RPX
DS8803A-06 April 2011
Figure 6. GM3 Setting for current ratio function
Figure 7. GM1~2 Setting for current ratio function
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23
RT8803A
Current Ratio Function
Load Line without dead zone at light loads
35
1.31
IL3
1.3
25
1.29
20
1.28
V CORE (V)
I L (A)
30
IL2
IL1
15
w/o Dead Zone Compensation
RCSN open
1.27
1.26
10
RCSN2 = 82k
w/i Dead Zone Compensation
1.25
5
1.24
0
0
15
30
45
60
75
90
1.23
0
5
10
I OUT (A)
15
20
25
I OUT (A)
Figure 8
Figure 10
Current Balance Function
35
ILX
Lx
DCRx
Rx
Cx
30
I L (A)
25
+ VCx -
20
IL3
+
-
15
GMx
Ix
IL2
10
VOUT
RCSN
RCSN2
IL1
5
Figure 11. Application circuit of GM
0
0
20
40
60
80
100
120
I OUT (A)
Referring to Figure 11, IX is expressed as :
Figure 9
IX =
Dead Zone Elimination
RT8803A samples and holds inductor current at 50%
period by time-sharing sourcing a current IX to RCSN. At
light load condition when inductor current is not balance,
voltage VCx across the sensing capacitor would be
negative. It needs a negative IX to sense the voltage.
However, RT8803A CANNOT provide a negative IX and
consequently cannot sense negative inductor current. This
results in dead zone of load line performance as shown in
Figure 10. Therefore a technique as shown in Figure 11 is
required to eliminate the dead zone of load line at light
load condition.
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24
ILX_66% × DCRx ILX_66% × DCRx
VOUT
+
+
R CSN2
R CSN2
R CSN
(1)
where ILX_50% is the of inductor current at 50% period. To
make sure RT8803A could sense the inductor current,
right hand side of Equation (1) should always be positive:
ILX_66% × DCRx ILX_66% × DCRx
VOUT
+
+
≥0
R CSN2
R CSN2
R CSN
(2)
Since RCSN >> DCRx in practical application, Equation (2)
could be simplified as :
ILX_66% × DCRx
VOUT
≥
R CSN2
R CSN
DS8803A-06 April 2011
RT8803A
For example, assuming the negative inductor current is
ILX_50% = −5A at no load, then for
RCSN 330Ω, RADJ = 160Ω, VOUT = 1.300V
1.3V ≥ − 5A × 1mΩ
R CSN2
330Ω
If RADJ is connected as in Figure 14, RADJ = R1 + (R2//
R NTC), which is a negative temperature correlated
resistance. By properly selecting R1 and R2, the positive
temperature coefficient of DCR can be canceled by the
negative temperature coefficient of RADJ. Thus the load
line will be thermally compensated.
RCSN2 ≤ 85.8kΩ
ADJ
Choose RCSN2 = 82kΩ
R1
Figure 10 shows that dead zone of load line at light load
is eliminated by applying this technique.
RADJ
RNTC
VR_HOT & VR_FAN Setting
R2
VCC
5V
Figure 14. RADJ Connection for Thernal Compensation
0.39 x VCC
+
CMP
-
Q1
0.33 x VCC
+
CMP
-
Q2
R1
TSEN
VTSEN
RNTC
0.28 x VCC
+
CMP
-
Q3
Figure 12
VTSEN
VTSEN is inversely proportional
to Temperature.
0.39 x VCC
0.33 x VCC
0.28 x VCC
VR_FAN
VR_HOT
Temperature
Over Current Protection
Phase current OCP
RT8803A uses an external resistor RIMAX connected to
IMAX pin to generate a reference current IIMAX for over
current protection :
V
IIMAX = IMAX
RIMAX
where VIMAX is typical 1.0V . OCP comparator compares
each sensed phase current IX with this reference current
as shown in Figure 15. Equivalently, the maximum phase
current ILX(MAX) is calculated as below:
1
1I
X(MAX) = IIMAX
2
3
V
I X(MAX) = 3 IIMAX = 3 × IMAX
2 RIMAX
2
R
R
V
ILX(MAX) = I X × CSNX = 3 × IMAX × CSNX
RLX
R
2
DCR X
IMAX
OCP Comparator
Figure 13. VR_HOT and VR_FAN Signal vs TSEN Voltage
Load Line Setting and Thermal Compensation
+
1/3 IX
-
1/2 IIMAX
Figure 15. Over Current Comparator
VADJ = Sum(IX) x RADJ = (DCR x RADJ / RCSN) x IOUT
= LL x IOUT
VOUT = VDAC − VADJ = VDAC − LL x IOUT
LL = DCR(PTC) x RADJ(NTC) / RCSN
DCR is the inductor DCR which is a PTC resistance.
DS8803A-06 April 2011
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25
RT8803A
Error Amplifier Characteristic
4.7k
For fast response of converter to meet stringent output
current transient response, RT8803A provides large slew
rate capability and high gain-bandwidth performance.
B 4.7k
EA
+
A
VREF
EA Falling Slew Rate
Figure 18. Gain-Bandwidth Measurement by signal A
divided by signal B
Design Procedure Suggestion
VFB
a. Output filter pole and zero (Inductor, output capacitor
value & ESR).
b. Error amplifier compensation & saw-tooth wave
amplitude (compensation network).
VCOMP
CH1:(500mV/Div)
CH2:(2V/Div)
c. Kelvin sense for VCORE.
Current Loop Setting
Time (250ns/Div)
Figure 16. EA Rising Transient with 10pF Loading ;
Slew Rate = 10V/μs
EA Rising Slew Rate
a. GM amplifier S/H current (current sense component
DCR, ISPX and ISNX pin external resistor value).
b. Over-current protection trip point (RIMAX resistor).
VRM Load Line Setting
a. Droop amplitude (ADJ pin resistor).
b. No load offset (RCSN)
VFB
c. DAC offset voltage setting (OFS pin & compensation
network resistor).
d. Temperature coefficient compensation(TSEN external
resister & thermistor, resistor between ADJ and GND.)
Power Sequence & SS
VCOMP
CH1:(500mV/Div)
CH2:(2V/Div)
DVD pin external resistor and SS pin capacitor.
PCB Layout
Time (250ns/Div)
Figure 17. EA Falling Transient with 10pF Loading ;
Slew Rate = 8V/μs
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26
a.Kelvin sense for current sense GM amplifier input.
b.Refer to layout guide for other items.
DS8803A-06 April 2011
RT8803A
Outline Dimension
D2
D
SEE DETAIL A
L
1
E
E2
e
b
1
1
2
2
A
A1
A3
DETAIL A
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
0.800
1.000
0.031
0.039
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.180
0.300
0.007
0.012
D
4.950
5.050
0.195
0.199
D2
3.400
3.750
0.134
0.148
E
4.950
5.050
0.195
0.199
E2
3.400
3.750
0.134
0.148
e
L
0.500
0.350
0.020
0.450
0.014
0.018
V-Type 32L QFN 5x5 Package
Richtek Technology Corporation
Richtek Technology Corporation
Headquarter
Taipei Office (Marketing)
5F, No. 20, Taiyuen Street, Chupei City
5F, No. 95, Minchiuan Road, Hsintien City
Hsinchu, Taiwan, R.O.C.
Taipei County, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Tel: (8862)86672399 Fax: (8862)86672377
Email: [email protected]
Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit
design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be
guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.
DS8803A-06 April 2011
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27