TAOS DS90UB913QSQE/NOPB

DS90UB913Q, DS90UB914Q
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SNLS420B – JULY 2012 – REVISED APRIL 2013
DS90UB913Q/DS90UB914Q 10-100MHz 10/12- Bit DC-Balanced FPD-Link III Serializer and
Deserializer with Bidirectional Control Channel
Check for Samples: DS90UB913Q, DS90UB914Q
FEATURES
DESCRIPTION
•
•
•
The DS90UB913Q/DS90UB914Q chipset offers a
FPD-Link III interface with a high-speed forward
channel and a bidirectional control channel for data
transmission over a single differential pair. The
DS90UB913Q/914Q chipsets incorporate differential
signaling on both the high-speed forward channel and
bidirectional control channel data paths. The
Serializer/ Deserializer pair is targeted for
connections between imagers and video processors
in an ECU (Electronic Control Unit). This chipset is
ideally suited for driving video data requiring up to 12
bit pixel depth plus two synchronization signals along
with bidirectional control channel bus.
1
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
10 MHz to 100 MHz Input Pixel Clock Support
Single Differential Pair Interconnect
Programmable Data Payload:
– 10 bit Payload up to 100Mhz
– 12 bit Payload up to 75MHz
Continuous Low Latency Bidirectional Control
Interface Channel with I2C [email protected]
2:1 Multiplexer to Choose Between Two Input
Imagers
Embedded Clock With DC Balanced Coding to
Support AC-Coupled Interconnects
Capable of Driving up to 25 Meters Shielded
Twisted-pair
Receive Equalizer Automatically Adapts for
Changes in Cable Loss
4 Dedicated General Purpose Input (GPI)/
Output (GPO)
LOCK Output Reporting Pin and AT-SPEED
BIST Diagnosis Feature to Validate Link
Integrity
1.8V, 2.8V or 3.3V Compatible Parallel Inputs
on Serializer
Single Power Supply at 1.8V
ISO 10605 and IEC 61000-4-2 ESD Compliant
Automotive Grade Product: AEC-Q100 Grade 2
Qualified
Temperature Range −40°C to +105°C
Small Serializer Footprint (5mm x 5mm)
EMI/EMC Mitigation - Deserializer
– Programmable Spread Spectrum (SSCG)
Outputs.
– Receiver Staggered Outputs
There is a multiplexer at the Deserializer to choose
between two input imagers. The Deserializer can
have only one active input imager. The primary video
transport converts 10/12 bit data over a single highspeed serial stream, along with a separate low
latency bidirectional control channel transport that
accepts control information from an I2C port and is
independent of video blanking period.
Using TI’s embedded clock technology allows
transparent full-duplex communication over a single
differential pair, carrying asymmetrical bidirectional
control channel information in both directions. This
single serial stream simplifies transferring a wide data
bus over PCB traces and cable by eliminating the
skew problems between parallel data and clock
paths. This significantly saves system cost by
narrowing data paths that in turn reduce PCB layers,
cable width, and connector size and pins. In addition,
the Deserializer inputs provide adaptive equalization
to compensate for loss from the media over longer
distances. Internal DC balanced encoding/decoding is
used to support AC-Coupled interconnects. The
Serializer is offered in a 32-pin WQFN package and
the Deserializer is offered in a 48-pin WQFN
package.
APPLICATIONS
•
•
Front or Rear View Camera for Collision
Mitigation
Surround View for Parking Assistance
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012–2013, Texas Instruments Incorporated
DS90UB913Q, DS90UB914Q
SNLS420B – JULY 2012 – REVISED APRIL 2013
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Typical Application Diagram
Parallel
Data In
10 or 12
Parallel
Data Out
10 or 12
FPD-Link III
2
Megapixel
Imager/Sensor
2
HSYNC,
VSYNC
DS90UB913Q
Bidirectional
Control Bus
DS90UB914Q
Bidirectional
Control Channel
4
GPO
2
DSP, FPGA/
µ-Processor/
ECU
HSYNC,
VSYNC
4
GPIO
2
Deserializer
Serializer
Bidirectional
Control Bus
Figure 1. Typical Application Circuit
Block Diagrams
RIN0+ RT
RT
GPO[3:0]
PCLK
10
or
12
ROUT
HSYNC
VSYNC
4
GPIO[3:0]
RIN1+
Clock
Gen
PLL
2:1
RIN0-
DOUT-
Output Latch
DOUT+
Decoder
RT
Deserializer
RT
Adaptive Eq.
Serializer
4
Encoder
DIN
HSYNC
VSYNC
Input Latch
10 or
12
PCLK
LOCK
Clock
Gen
CDR
PASS
RIN1-
Encoder
Encoder
ID[x]
MODE
SEL
Decoder
SCL
FIFO
SDA
I2C Controller
OEN
MODE
I2C
Controller
Timing and
Control
PDB
BISTEN
FIFO
Timing and
Control
Decoder
PDB
SDA
SCL
IDx[0]
IDx[1]
DS90UB914Q - DESERIALIZER
DS90UB913Q - SERIALIZER
Figure 2. Block Diagram
DS90UB913Q
Serializer
DS90UB914Q
Deserializer
FPD-Link III
Camera Data
DOUT+
10 or 12
Image
Sensor
DATA
HSYNC
DIN[11:0] or
DIN[9:0]
HSYNC,
VSYNC
VSYNC
Pixel Clock
4
PCLK
DOUT-
Camera Data
10 or 12
RIN+
RIN-
ROUT[11:0]
or
ROUT[9:0]
HSYNC,
VSYNC
Bi-Directional
Control Channel
PCLK
GPO[3:0]
GPIO[3:0]
GPO[3:0]
SDA
Camera Unit
SCL
DATA
HSYNC
VSYNC
Pixel Clock
4
GPIO[3:0]
SDA
SDA
SCL
SCL
ECU Module
Microcontroller
SDA
SCL
Figure 3. Application Block Diagram
2
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DS90UB913Q, DS90UB914Q
20
16
15
14
VDDCML
VDDD
13
DOUT+
DIN[8]
12
DOUT-
DIN[9]
11
VDDT
10
VDDPLL
9
PDB
DIN[7]
1
2
3
4
5
6
7
8
VSYNC
PCLK
SCL
SDA
ID[x]
RES
MODE
DIN[11]
DS90UB913Q
32-Pin WQFN
(Top View)
HSYNC
DIN[10]
DAP = GND
32
26
GPO[0]
DIN[6]
27
GPO[1]
28
17
29
18
30
19
GPO[2]/
CLKOUT
DIN[1]
21
GPO[3]/
CLKIN
DIN[2]
22
DIN[0]
DIN[3]
23
25
24
31
VDDIO
DIN[4]
SNLS420B – JULY 2012 – REVISED APRIL 2013
DIN[5]
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Serializer - DS90UB913Q — Top View
DS90UB913Q SERIALIZER PIN DESCRIPTIONS
Pin Name
Pin No.
I/O, Type
Description
LVCMOS PARALLEL INTERFACE
DIN[0:11]
19,20,21,22,
23,24,26,27,
29,30,31,32
Inputs,
LVCMOS
w/ pull down
Parallel Data Inputs.
HSYNC
1
Inputs,
LVCMOS
w/ pull down
Horizontal SYNC Input
VSYNC
2
Inputs,
LVCMOS
w/ pull down
Vertical SYNC Input
PCLK
3
Input, LVCMOS Pixel Clock Input Pin. Strobe edge set by TRFB control register.
w/ pull down
GENERAL PURPOSE OUTPUT (GPO)
GPO[1:0]
GPO[2]/CLKOUT
16,15
Output,
LVCMOS
General-purpose output pins can be configured as outputs; used to control and
respond to various commands. GPO[0:1] can be configured to be the outputs for input
signals coming from GPIO[0:1] pins on the Deserializer or can be configured to be
outputs of the local register on the Serializer.
17
Output,
LVCMOS
GPO2 pin can be configured to be the output for input signal coming from the GPIO2
pin on the Deserializer or can be configured to be the output of the local register on
the Serializer. It can also be configured to be the output clock pin when the
DS90UB913Q device is used in the External Oscillator mode. See Applications
Information for a detailed description of the DS90UB913/914Q chipsets working with
the external oscillator.
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: DS90UB913Q DS90UB914Q
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DS90UB913Q SERIALIZER PIN DESCRIPTIONS (continued)
Pin Name
Pin No.
I/O, Type
Description
18
Input/Output,
LVCMOS
GPO3 can be configured to be the output for input signals coming from the GPIO3 pin
on the Deserializer or can be configured to be the output of the local register setting
on the Serializer. It can also be configured to be the input clock pin when the
DS90UB913Q Serializer is working with an external oscillator. See Applications
Information section for a detailed description of the DS90UB913/914Q chipsets
working with an external oscillator.
GPO[3]/CLKIN
BIDIRECTIONAL CONTROL BUS - I2C COMPATIBLE
SCL
4
Input/Output,
Open Drain
Clock line for the bidirectional control bus communication
SCL requires an external pull-up resistor to VDDIO.
SDA
5
Input/Output,
Open Drain
Data line for the bidirectional control bus communication
SDA requires an external pull-up resistor to VDDIO.
MODE
8
ID[x]
6
Device mode select
Input, LVCMOS Resistor to Ground and 10 kΩ pull-up to 1.8V rail. MODE pin on the Serializer can be
w/ pull down
used to select whether the system is running off the PCLK from the imager or an
external oscillator. See details in Table 5
Input, analog
Device ID Address Select
The ID[x] pin on the Serializer is used to assign the I2C device address. Resistor to
Ground and 10 kΩ pull-up to 1.8V rail. See Table 7
CONTROL AND CONFIGURATION
PDB
9
Power down Mode Input Pin.
PDB = H, Serializer is enabled and is ON.
Input, LVCMOS
PDB = L, Serailizer is in Power Down mode. When the Serializer is in Power Down,
w/ pull down
the PLL is shutdown, and IDD is minimized. Programmed control register data are
NOT retained and reset to default values
RES
7
Input, LVCMOS Reserved.
w/ pull down
This pin MUST be tied LOW.
FPD–Link III INTERFACE
Input/Output,
CML
Non-inverting differential output, bidirectional control channel input. The interconnect
must be AC Coupled with a 100 nF capacitor.
12
Input/Output,
CML
Inverting differential output, bidirectional control channel input. The interconnect must
be AC Coupled with a 100 nF capacitor.
VDDPLL
10
Power, Analog
PLL Power, 1.8V ±5%
VDDT
11
Power, Analog
Tx Analog Power, 1.8V ±5%
VDDCML
14
Power, Analog
CML & Bidirectional Channel Driver Power, 1.8V ±5%
VDDD
28
Power, Digital
Digital Power, 1.8V ±5%
Power, Digital
Power for I/O stage. The single-ended inputs and SDA, SCL are powered from VDDIO.
VDDIO can be connected to a 1.8V ±5% or 2.8±10% or 3.3V ±10%
Ground, DAP
DAP must be grounded. DAP is the large metal contact at the bottom side, located at
the center of the WQFN package. Connected to the ground plane (GND) with at least
9 vias.
DOUT+
13
DOUTPOWER AND GROUND
VDDIO
VSS
4
25
DAP
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DS90UB913Q, DS90UB914Q
VDDR
IDx[0]
IDx[1]
RIN1-
RIN1+
VDDCML1
PDB
VDDIO1
GPIO[0]
GPIO[1]
GPIO[2]
GPIO[3]
35
34
33
32
31
30
29
28
27
26
25
SNLS420B – JULY 2012 – REVISED APRIL 2013
36
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24
ROUT[0]
23
ROUT[1]
MODE
37
CMLOUTP
38
CMLOUTN
39
22
ROUT[2]
VDDCML0
40
21
ROUT[3]
RIN0+
41
20
VDDIO2
19
ROUT[4]
18
ROUT[5]
RIN0-
42
RES
43
DAP = GND
DS90UB914Q
48-Pin WQFN
(Top View)
RES
44
17
VDDD
VDDPLL
45
16
ROUT[6]
SEL
46
15
ROUT[7]
9
VSYNC
12
8
PCLK
ROUT[10]
7
VDDIO3
11
6
10
5
OEN
BISTEN
HSYNC
4
OSS_SEL
ROUT[11]
3
VDDSSCG
ROUT[9]
2
13
SCL
14
48
1
47
LOCK
SDA
PASS
ROUT[8]
Deserializer - DS90UB914Q — Top View
DS90UB914Q Deserializer Pin Descriptions
Pin Name
Pin No.
I/O, Type
Description
LVCMOS PARALLEL INTERFACE
ROUT[11:0]
11,12,13,14,
15,16,18,19,
21,22,23,24
Outputs,
LVCMOS
Parallel Data Outputs.
HSYNC
10
Output,
LVCMOS
Horizontal SYNC Output.
VSYNC
9
Output,
LVCMOS
Vertical SYNC Output.
PCLK
8
Output,
LVCMOS
Pixel Clock Output Pin.
Strobe edge set by RRFB control register.
GENERAL PURPOSE INPUT/OUTPUT (GPIO)
GPI0[1:0]
GPIO[3:2]
27,28
Digital
Input/Output,
LVCMOS
General-purpose input/output pins can be used to control and respond to various
commands. They may be configured to be the input signals for the corresponding
GPOs on the serializer or they may be configured to be outputs to follow local register
settings.
25,26
Digital
Input/Output
LVCMOS
General purpose input/output pins GPO[2:3] can be configured to be input signals for
GPOs on the Serializer. In addition they can also be configured to be outputs to follow
the local register settings. When the SerDes chipsets are working with an external
oscillator, these pins can be configured only to be outputs to follow the local register
settings.
BIDIRECTIONAL CONTROL BUS - I2C COMPATIBLE
SCL
2
Input/Output,
Open Drain
Clock line for the bidirectional control bus communication
SCL requires an external pull-up resistor to VDDIO.
SDA
1
Input/Output,
Open Drain
Data line for bidirectional control bus communication
SDA requires an external pull-up resistor to VDDIO.
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DS90UB914Q Deserializer Pin Descriptions (continued)
Pin Name
Pin No.
MODE
37
IDx[0:1]
I/O, Type
Description
Device mode select pin
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. The MODE pin on the Deserializer
can be used to configure the Serializer and Deserializer to work in different input
PCLK range. See details in Table 2.
12– bit low frequency mode – (10- 50 MHz operation):
In this mode, the Serializer and Deserializer can accept up to 12 bits DATA+2 SYNC.
Input PCLK range is from 10MHz to 50MHz.
Input, LVCMOS
12– bit high frequency mode – (15-75 MHz operation): In this mode, the Serializer
w/ pull up
and Deserializer can accept up to 12 bits DATA + 2 SYNC. Input PCLK range is from
15MHz to 75MHz.
10–bit mode– (20–100 MHz operation):
In this mode, the Serializer and Deserializer can accept up to 10 bits DATA + 2
SYNC. Input PCLK frequency can range from20 MHz to 100MHz.
Please refer to Table 6 in the Applications Information section on how to configure the
MODE pin on the Deserializer.
35,34
Input, analog
The IDx[0] and IDx[1] pins on the Deserializer are used to assign the I2C device
address. Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 8
Input pin to select the Slave Device Address.
Input is connect to external resistor divider to set programmable Device ID address
CONTROL AND CONFIGURATION
Power down Mode Input Pin.
PDB = H, Deserializer is enabled and is ON.
Input, LVCMOS
PDB = L, Deserializer is in Sleep (power down mode). When the Deserializer is in
w/ pull down
Sleep, programmed control register data are NOT retained and reset to default
values.
PDB
30
LOCK
48
Output,
LVCMOS
BISTEN
6
Input
LVCMOS w/
pulldown
PASS
47
Output,
LVCOMS
OEN
5
Input
LVCMOS w/
pulldown
Output Enable Input
Refer to Table 9
OSS_SEL
4
Input
LVCMOS w/
pulldown
Output Sleep State Select Pin
Refer to Table 9
SEL
46
Input
LVCMOS w/
pulldown
MUX Select line
SEL = L, RIN0+/- input. This selects input A as the active channel on the Deserializer.
SEL = H, RIN1+/- input. This selects input B as the active channel on the
Deserializer.
LOCK Status Output Pin.
LOCK = H, PLL is Locked, outputs are active
LOCK = L, PLL is unlocked, ROUT and PCLK output states are controlled by
OSS_SEL control register. May be used as Link Status.
BIST Enable pin
BISTEN=H, BIST Mode Enabled
BISTEN=L, BIST Mode is disabled
PASS Output Pin for BIST mode.
PASS = H, ERROR FREE Transmission
PASS = L, one or more errors were detected in the received payload.
See Built In Self Test section for more information. Leave Open if unused. Route to
test point (pad) recommended.
FPD–Link III INTERFACE
RIN0+
41
Input/Output,
CML
Non-Inverting Differential input, bidirectional control channel. The IO must be AC
coupled with a 100 nF capacitor
RIN0-
42
Input/Output,
CML
Inverting Differential input, bidirectional control channel. The IO must be AC coupled
with a 100 nF capacitor
RIN1+
32
Input/Output,
CML
Non-Inverting Differential input, bidirectional control channel. The IO must be AC
coupled with a 100 nF capacitor
RIN1-
33
Input/Output,
CML
Inverting Differential input, bidirectional control channel. The IO must be AC coupled
with a 100 nF capacitor
RES
43,44
—
CMLOUTP/N
38,39
Reserved. This pin must always be tied low
Route to test point or leave open if unused
POWER AND GROUND
VDDIO1/2/3
6
29, 20, 7
Power, Digital
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LVCMOS I/O Buffer Power, The single-ended outputs and control input are powered
from VDDIO. VDDIO can be connected to a 1.8V ±5% or 3.3V ±10%
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SNLS420B – JULY 2012 – REVISED APRIL 2013
DS90UB914Q Deserializer Pin Descriptions (continued)
Pin Name
Pin No.
I/O, Type
17
Power, Digital
Digital Core Power, 1.8V ±5%
VDDSSCG
3
Power, Analog
SSCG PLL Power, 1.8V ±5%
VDDR
36
Power, Analog
Rx Analog Power, 1.8V ±5%
40,31
Power, Analog
CML and Bidirectional control channel Drive Power, 1.8V±5%
45
Power, Analog
PLL Power, 1.8V ±5%
DAP
Ground, DAP
DAP must be grounded. DAP is the large metal contact at the bottom side, located at
the center of the WQFN package. Connected to the ground plane (GND) with at least
16 vias.
VDDD
VDDCML0/1
VDDPLL
VSS
Description
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2)
Supply Voltage – VDDn (1.8V)
−0.3V to +2.5V
Supply Voltage – VDDIO
−0.3V to +4.0V
−0.3V to + (VDDIO + 0.3V)
LVCMOS Input Voltage I/O Voltage
−0.3V to +(VDD + 0.3V)
CML Driver I/O Voltage (VDD)
−0.3V to (VDD + 0.3V)
CML Receiver I/O Voltage (VDD)
Junction Temperature
+150°C
Storage Temperature
−65°C to +150°C
Maximum Package Power Dissipation Capacity Package
1/θJA °C/W above +25°
Package Derating:
DS90UB913Q 32 Lead WQFN
θJA(based on 16 thermal vias)
θJC(based on 16 thermal vias)
6.9 °C/W
DS90UB914Q 48 Lead WQFN
θJA(based on 16 thermal vias)
26.9 °C/W
θJC(based on 16 thermal vias)
4.4 °C/W
38.4 °C/W
ESD Rating (IEC 61000-4-2)
RD = 330Ω, CS = 150pF
Air Discharge
(DOUT+, DOUT-, RIN+, RIN-)
≥±25 kV
Contact Discharge
(DOUT+, DOUT-, RIN+, RIN-)
≥±7 kV
ESD Rating (ISO10605)
RD = 330Ω, CS = 150/330pF
ESD Rating (ISO10605)
RD = 2KΩ, CS = 150/330pF
Air Discharge
(DOUT+, DOUT-, RIN+, RIN-)
≥±15 kV
Contact Discharge
(DOUT+, DOUT-, RIN+, RIN-)
≥±8 kV
ESD Rating (HBM)
≥±8 kV
≥±1 kV
ESD Rating (CDM)
≥±250 V
ESD Rating (MM)
For soldering specifications:
(1)
(2)
see product folder at www.ti.com and www.ti.com/lit/an/snoa549c/snoa549c.pdf
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional; the device should not be operated beyond such conditions.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
Copyright © 2012–2013, Texas Instruments Incorporated
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Recommended Operating Conditions
Min
Nom
Max
Units
Supply Voltage (VDDn)
1.71
1.8
1.89
V
LVCMOS Supply Voltage (VDDIO)
OR
1.71
1.8
1.89
V
LVCMOS Supply Voltage (VDDIO)
OR
3.0
3.3
3.6
V
LVCMOS Supply Voltage (VDDIO) Only
Serializer
2.52
2.8
3.08
V
VDDn (1.8V)
25
mVp-p
VDDIO (1.8V)
25
mVp-p
VDDIO (3.3V)
50
mVp-p
Supply Noise (1)
Operating Free Air
Temperature (TA)
-40
PCLK Clock Frequency
(1)
+25
+105
°C
100
MHz
10
Supply noise testing was done with minimum capacitors (as shown on Figure 44 Figure 46) on the PCB. A sinusoidal signal is AC
coupled to the VDDn (1.8V) supply with amplitude = 25 mVp-p measured at the device VDDn pins. Bit error rate testing of input to the
Ser and output of the Des with 10 meter cable shows no error when the noise frequency on the Ser is less than 1 MHz. The Des on the
other hand shows no error when the noise frequency is less than 750 kHz.
Electrical Characteristics (1) (2) (3)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
LVCMOS DC SPECIFICATIONS 3.3V I/O (SER INPUTS, DES OUTPUTS, GPI, GPO, CONTROL INPUTS AND OUTPUTS)
VIH
High Level Input
Voltage
VIN = 3.0V to 3.6V
2.0
VIN
V
VIL
Low Level Input
Voltage
VIN = 3.0V to 3.6V
GND
0.8
V
IIN
Input Current
VIN = 0V or 3.6V
VIN = 3.0V to 3.6V
-20
+20
µA
VOH
High Level Output
Voltage
VDDIO = 3.0V to 3.6V
IOH = −4 mA
2.4
VDDIO
V
VOL
Low Level Output
Voltage
VDDIO = 3.0V to 3.6V
IOL = +4 mA
GND
0.4
V
IOS
Output Short Circuit
Current
VOUT = 0V
IOZ
TRI-STATE® Output
Current
PDB = 0V,
VOUT = 0V or VDD
±1
Serializer
GPO Outputs
-15
Deserializer
LVCMOS Outputs
-35
LVCMOS Outputs
mA
-20
+20
µA
LVCMOS DC SPECIFICATIONS 1.8V I/O (SER INPUTS, DES OUTPUTS, GPI, GPO, CONTROL INPUTS AND OUTPUTS)
VIH
High Level Input
Voltage
VIN = 1.71V to 1.89V
VIL
Low Level Input
Voltage
IIN
VOH
(1)
(2)
(3)
8
0.65 VIN
VIN
VIN = 1.71V to 1.89V
GND
0.35 VIN
Input Current
VIN = 0V or 1.89V
VIN = 1.71V to 1.89V
-20
High Level Output
Voltage
VDDIO = 1.71V to 1.89V
IOH = −4 mA
V
VDDIO 0.45
±1
+20
µA
VDDIO
V
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
Typical values represent most likely parametric norms at 1.8V or 3.3V, TA = +25°C, and at the Recommended Operation Conditions at
the time of product characterization and are not specified.
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SNLS420B – JULY 2012 – REVISED APRIL 2013
Electrical Characteristics(1)(2)(3) (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
GND
VOL
Low Level Output
Voltage
VDDIO = 1.71V to 1.89V Deserializer
IOL = +4 mA
LVCMOS Outputs
IOS
Output Short Circuit
Current
VOUT = 0V
IOZ
TRI-STATE® Output
Current
PDB = 0V,
VOUT = 0V or VDD
Typ
Serializer
GPO Outputs
-11
Deserializer
LVCMOS Outputs
-17
LVCMOS Outputs
Max
Units
0.45
V
mA
-20
+20
µA
LVCMOS DC SPECIFICATIONS 2.8V I/O (SER INPUTS, GPI, GPO, CONTROL INPUTS AND OUTPUTS)
VIH
High Level Input
Voltage
VIN = 2.52V to 3.08V
VIL
Low Level Input
Voltage
IIN
0.7 VIN
VIN
VIN = 2.52V to 3.08V
GND
0.3 VIN
Input Current
VIN = 0V or 3.08V
VIN = 2.52V to 3.08V
-20
VOH
High Level Output
Voltage
VDDIO = 2.52V to 3.08V
IOH = −4 mA
VOL
Low Level Output
Voltage
VDDIO =2.52V to 3.08V
IOL = +4 mA
Deserializer
LVCMOS Outputs
IOS
Output Short Circuit
Current
VOUT = 0V
Serializer
GPO Outputs
-11
Deserializer
LVCMOS Outputs
-20
IOZ
TRI-STATE® Output
Current
PDB = 0V,
VOUT = 0V or VDD
V
LVCMOS Outputs
±1
+20
µA
VDDIO - 0.4
VDDIO
V
GND
0.4
V
mA
-20
+20
µA
340
412
mV
1
50
mV
CML DRIVER DC SPECIFICATIONS (DOUT+, DOUT-)
|VOD|
Output Differential
Voltage
RL = 100Ω (Figure 8)
ΔVOD
Output Differential
Voltage Unbalance
RL = 100Ω
VOS
Output Differential
Offset Voltage
RL = 100Ω (Figure 8)
ΔVOS
Offset Voltage
Unbalance
RL = 100Ω
IOS
Output Short Circuit
Current
DOUT+/- = 0V
RT
Differential Internal
Differential across DOUT+ and DOUTTermination Resistance
268
VDD VOD/2
1
V
50
-26
mV
mA
80
100
120
Ω
-20
1
+20
µA
80
100
120
Ω
CML RECEIVER DC SPECIFICATIONS (RIN0+,RIN0–,RIN1+,RIN1– )
Input Current
IIN
RT
VIN = VDD or 0V,
VDD = 1.89V
Differential Internal
Differential across RIN+ and RINTermination Resistance
CML RECEIVER AC SPECIFICATIONS (RIN0+,RIN0–,RIN1+,RIN1– )
|Vswing|
Minimum allowable
swing for 1010
pattern (4)
Line Rate = 1.4Gbps (Figure 10)
135
mV
CMLMONITOR OUTPUT DRIVER SPECIFICATIONS(CMLOUTP, CMLOUTN)
Ew
Differntial Output Eye
Opening
EH
Differential Output Eye
Height
RL = 100Ω
Jitter Frequency>f/40 (Figure 19)
0.45
UI
200
mV
SER/DES SUPPLY CURRENT *DIGITAL, PLL, AND ANALOG VDD
(4)
Specification is ensured by characterization and is not tested in production.
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Electrical Characteristics(1)(2)(3) (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
IDDT
Parameter
Serializer (Tx)
VDDn Supply Current
(includes load current)
Conditions
RL = 100Ω
WORST CASE pattern
(Figure 5)
RL = 100Ω
RANDOM PRBS-7
pattern
IDDIOT
IDDTZ
IDDIOTZ
10
Serializer (Tx)
VDDIO Supply Current
(includes load current)
Serializer (Tx) Supply
Current Power-down
Serializer (Tx) VDDIO
Supply Current Powerdown
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RL = 100Ω
WORST CASE pattern
(Figure 5)
PDB = 0V; All other
LVCMOS Inputs = 0V
PDB = 0V; All other
LVCMOS Inputs = 0V
Min
Typ
Max
Units
VDDn=1.89V
VDDIO=3.6V
f = 100 MHz, 10
bit mode
Default Registers
61
80
mA
VDDn=1.89V
VDDIO=3.6V
f = 75 MHz, 12 bit
high frequency
mode
Default Registers
61
80
VDDn=1.89V
VDDIO=3.6V
f = 50 MHz, 12 bit
low frequency
mode
Default Registers
61
VDDn=1.89V
VDDIO=3.6V
f = 100 MHz, 10
bit mode
Default Registers
54
VDDn=1.89V
VDDIO=3.6V
f = 75 MHz, 12 bit
high frequency
mode
Default Registers
54
VDD=1.89V
VDDIO=3.6V
f = 50 MHz, 12 bit
low frequency
mode
Default Registers
54
VDDIO=1.89V
f = 75 MHz, 12 bit
high frequency
mode
Default Registers
1.5
VDDIO=3.6V
f = 75 MHz, 12 bit
high frequency
mode Default
Registers
5
8
VDDIO=1.89V
Default Registers
300
900
µA
VDDIO=3.6V
Default Registers
300
900
µA
VDDIO=1.89V
Default Registers
15
100
µA
VDDIO=3.6V
Default Registers
15
100
µA
mA
80
mA
3
mA
Copyright © 2012–2013, Texas Instruments Incorporated
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SNLS420B – JULY 2012 – REVISED APRIL 2013
Electrical Characteristics(1)(2)(3) (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
IDDIOR
Parameter
Deserializer (Rx) Total
Supply Current
(includes load current)
Conditions
VDDIO=1.89V
CL=8pF
Worst Case Pattern
VDDIO=1.89V
CL=8pF
Random Pattern
VDDIO=3.6V
CL=8pF
Worst Case Pattern
VDDIO=3.6V
CL=8pF
Random Pattern
VDDIO=1.89V
CL=4pF
Worst Case Pattern
VDDIO=1.89V
CL=4pF
Random Pattern
VDDIO=3.6V
CL=4pF
Worst Case Pattern
VDDIO=3.6V
CL=4pF
Random Pattern
Min
Typ
Max
f=100MHz, 10–bit
mode
22
42
f=75MHz, 12–bit
high freq mode
19
39
f=50MHz, 12–bit
low freq mode
21
32
f=100MHz, 10–bit
mode
15
f=75MHz, 12–bit
high freq mode
12
f=50MHz, 12–bit
low freq mode
14
f=100MHz, 10–bit
mode
42
55
f=75MHz, 12–bit
high freq mode
37
50
f=50MHz, 12–bit
low freq mode
25
38
f=100MHz, 10–bit
mode
35
f=75MHz, 12–bit
high freq mode
30
f=50MHz, 12–bit
low freq mode
18
f=100MHz, 10–bit
mode
15
f=75MHz, 12–bit
high freq mode
11
f=50MHz, 12–bit
low freq mode
16
f=100MHz, 10–bit
mode
8
f=75MHz, 12–bit
high freq mode
4
f=50MHz, 12–bit
low freq mode
9
f=100MHz, 10–bit
mode
36
f=75MHz, 12–bit
high freq mode
29
f=50MHz, 12–bit
low freq mode
20
f=100MHz, 10–bit
mode
29
f=75MHz, 12–bit
high freq mode
22
f=50MHz, 12–bit
low freq mode
13
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Units
mA
mA
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mA
mA
mA
mA
mA
mA
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Electrical Characteristics(1)(2)(3) (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
IDDR
Parameter
Conditions
Deserializer (Rx) VDDn VDDn=1.89V
Supply Current
CL=4pF
(includes load current) Worst Case Pattern
VDDn=1.89V
CL=4pF
Random Pattern
IDDRZ
Deserializer (Rx)
Supply Current Powerdown
IDDIORZ
PBB=0V
All other LVCMOS
Inputs=0V
Min
Typ
Max
f=100MHz,
10–bit mode
64
110
f=75MHz,
12–bit high freq
mode
67
114
f=50MHz,
12–bit low freq
mode
63
96
f=100MHz,
10–bit mode
57
f=75MHz,
12–bit high freq
mode
60
f=50MHz,
12–bit low freq
mode
56
VDDIO=1.89V
Default Registers
42
Units
mA
400
µA
PBB=0V
All other LVCMOS
Inputs=0V
VDDIO=3.6V
Default Registers
42
400
PDB = 0V
All other LVCMOS
Inputs = 0V
VDDIO = 1.89V
8
40
VDDIO = 3.6V
360
800
Min
Typ
Max
Units
10
T
50
ns
12–bit high frequency mode
13.33
T
66.66
ns
12–bit low frequency mode
20
T
100
ns
Deserializer (Rx) VDD
Supply Current Powerdown
µA
Recommended Serializer Timing for PCLK (1)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
tTCP
Parameter
Transmit Clock Period
Conditions
Pin/Freq
10–bit Mode
tTCIH
Transmit Clock Input High
Time
0.4T
0.5T
0.6T
ns
tTCIL
Transmit Clock Input Low
Time
0.4T
0.5T
0.6T
ns
tCLKT
PCLK Input Transition
Time
(Figure 11)
20MHz–100 MHz, 10 bit mode
0.5T
2.5T
0.3T
ns
15MHz -75MHz, 12 bit high
frequency mode
0.5T
2.5T
0.3T
ns
10MHz-50MHz, 12 bit low
frequency mode
0.5T
2.5T
0.3T
ns
tJIT0
PCLK Input Jitter (PCLK
from imager mode)
Refer to
Jitter freq>f/40
f=10–100M
Hz
0.1T
ns
tJIT1
PCLK Input Jitter
Refer to
(External Oscillator mode) Jitter freq>f/40
f=10–100M
Hz
1T
ns
tJIT2
External Oscillator Jitter
0.1
UI
(1)
12
Recommended Input Timing Requirements are input specifications and not tested in production.
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SNLS420B – JULY 2012 – REVISED APRIL 2013
Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tLHT
CML Low-to-High Transition
Time
RL = 100Ω (Figure 6)
150
330
ps
tHLT
CML High-to-Low Transition
Time
RL = 100Ω (Figure 6)
150
330
ps
tDIS
Data Input Setup to PCLK
tDIH
Data Input Hold from PCLK
Serializer Data Inputs
(Figure 12)
tPLD
Serializer PLL Lock Time
RL = 100Ω (1) (2), (Figure 13)
tSD
Serializer Delay (2)
RT = 100Ω
10–bit mode
Register 0x03h b[0] (TRFB = 1)
(Figure 14)
RT = 100Ω
12–bit mode
Register 0x03h b[0] (TRFB = 1)
(Figure 14)
tJIND
tJINR
tJINT
λSTXBW
δSTX
δSTXf
(1)
(2)
(3)
(4)
(5)
2
ns
2
ns
1
2
ms
32.5T
38T
44T
ns
11.75T
13T
15T
ns
Serializer Output
Deterministic Jitter
Serializer output intrinsic deterministic
jitter . Measured (cycle-cycle) with
PRBS-7 test pattern (3) (4)
0.13
UI
Serializer Output Random
Jitter
Serializer output intrinsic random jitter
(cycle-cycle). Alternating-1,0
pattern. (3) (4)
0.04
UI
Peak-to-peak Serializer
Output Jitter
Serializer output peak-to-peak jitter
includes deterministic jitter, random
jitter, and jitter transfer from serializer
input. Measured (cycle-cycle) with
PRBS-7 test pattern. (3) (4)
0.396
UI
Serializer Jitter Transfer
Function -3 dB Bandwidth (5)
Serializer Jitter Transfer
Function (Peaking) (5)
PCLK = 100MHz
10–bit mode. Default Registers
PCLK = 75MHz
12–bit high frequency mode. Default
Registers
2.2
PCLK = 50MHz
12–bit low frequency mode. Default
Registers
2.2
PCLK = 100MHz
10–bit mode. Default Registers
Serializer Jitter Transfer
Function (Peaking
Frequency) (5)
2.2
MHz
1.06
PCLK = 75MHz
12–bit high frequency mode. Default
Registers
1.09
PCLK = 50MHz
12–bit low frequency mode. Default
Registers
1.16
PCLK = 100MHz
10–bit mode. Default Registers
dB
400
PCLK = 75MHz
12–bit high frequency mode. Default
Registers
500
PCLK = 50MHz
12–bit low frequency mode. Default
Registers
600
kHz
tPLD and tDDLT is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active PCLK
Specification is ensured by design.
Typical values represent most likely parametric norms at 1.8V or 3.3V, TA = +25°C, and at the Recommended Operation Conditions at
the time of product characterization and are not specified.
UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency.
Specification is ensured by characterization and is not tested in production.
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Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
tRCP
Parameter
Receiver Output
Clock Period
tPDC
PCLK Duty Cycle
tCLH
tCHL
tCLH
tCHL
tROS
tROH
Conditions
10–bit mode
Pin/Freq.
Min
10
50
13.33
66.66
12–bit low frequency mode
10
100
PCLK
45
50
55
12–bit high frequency mode
40
50
60
12–bit low frequency mode
40
50
60
1.3
2
2.8
1.3
2
2.8
1
2.5
4
1
2.5
4
0.38T
0.5T
0.38T
0.5T
LVCMOS Low-toVDDIO: 1.71V to 1.89V or 3.0V
High Transition Time to 3.6V,
CL = 8 pF (lumped load)
LVCMOS High-toDefault Registers
Low Transition Time
(Figure 16) (1)
PCLK
LVCMOS Low-toVDDIO: 1.71V to 1.89V or 3.0V
High Transition Time to 3.6V,
CL = 8 pF (lumped load)
LVCMOS High-toDefault Registers
Low Transition Time
(Figure 16) (1)
ROUT[11:0], HS, VS
ROUT Setup Data to VDDIO: 1.71V to 1.89V or 3.0V
PCLK
to 3.6V,
CL = 8 pF (lumped load)
ROUT Hold Data to
Default Registers (Figure 18)
PCLK
ROUT[11:0], HS, VS
Deserializer Delay
tDDLT
tRCJ
tDPJ
(1)
(2)
14
Deserializer Data
Lock Time
Receiver Clock Jitter PCLK
SSCG[3:0] = OFF (1)
Deserializer Period
Jitter
PCLK
SSCG[3:0] = OFF (2) (1)
ns
%
ns
ns
Default Registers
12–bit low frequency
Register 0x03h b[0] (RRFB = 1) mode
(Figure 17) (1)
12–bit high frequency
mode
With Adaptive Equalization
(Figure 15)
Units
ns
10–bit mode
tDD
Max
12–bit high frequency mode
10–bit mode
PCLK (Figure 18)
Typ
154T
158T
109T
112T
73T
75T
10–bit mode
15
22
12–bit low frequency
mode
15
22
12–bit high frequency
mode
15
22
10–bit mode
PCLK=100MHz
20
30
12–bit low frequency
mode
PCLK=50MHz
22
35
12–bit high frequency
mode
PCLK=75MHz
45
90
10–bit mode
PCLK=100MHz
170
815
12–bit low frequency
mode
PCLK=50MHz
180
330
12–bit high frequency
mode
PCLK=75MHz
300
515
ns
ms
ps
ps
Specification is ensured by characterization and is not tested in production.
tDPJ is the maximum amount the period is allowed to deviate measured over 30,000 samples.
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SNLS420B – JULY 2012 – REVISED APRIL 2013
Deserializer Switching Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
tDCCJ
fdev
fmod
(3)
Parameter
Deserializer Cycleto-Cycle Clock Jitter
Spread Spectrum
Clocking Deviation
Frequency
Conditions
PCLK
SSCG[3:0] = OFF (3) (1)
LVCMOS Output Bus
SSC[3:0] = ON (Figure 23) (1)
Spread Spectrum
Clocking Modulation
Frequency
Pin/Freq.
Min
Typ
Max
10–bit mode
PCLK=100MHz
440
1760
12–bit low frequency
mode
PCLK=50MHz
460
730
12–bit high frequency
mode
PCLK=75MHz
565
985
10 MHz–100 MHz
Units
ps
±0.5 to
±1.5
%
5 to 50
kHz
10 MHz–100 MHz
tDCCJ is the maximum amount of jitter between adjacent clock cycles measured over 30,000 samples.
AC Timing Specifications (SCL, SDA) - I2C Compliant
Over recommended supply and temperature ranges unless otherwise specified.(Figure 4)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
>0
100
kHz
Fast Mode
>0
400
kHz
Standard Mode
4.7
µs
Fast Mode
1.3
µs
Standard Mode
4.0
µs
Fast Mode
0.6
µs
4.0
µs
Recommended Input Timing Requirements
fSCL
Standard Mode
SCL Clock Frequency
tLOW
SCL Low Period
tHIGH
SCL High Period
tHD:STA
Hold time for a start or a repeated start
condition
Standard Mode
Fast Mode
0.6
µs
tSU:STA
Set Up time for a start or a repeated
start condition
Standard Mode
4.7
µs
Fast Mode
0.6
tHD:DAT
Standard Mode
Data Hold Time
Fast Mode
tSU:DAT
Data Set Up Time
tSU:STO
Set Up Time for STOP Condition
tBUF
Bus Free time between Stop and Start
tr
SCL & SDA Rise Time
tf
SCL & SDA Fall Time
µs
0
3.45
µs
0
900
ns
Standard Mode
250
ns
Fast Mode
100
ns
Standard Mode
4.0
µs
Fast Mode
0.6
µs
Standard Mode
4.7
µs
Fast Mode
1.3
µs
Standard Mode
1000
ns
Fast Mode
300
ns
Standard Mode
300
ns
Fast Mode
300
ns
Max
Units
VDDIO
V
Bidirectional Control Bus DC Timing Specifications (SCL, SDA) - I2C Compliant (1)
Over recommended supply and temperature ranges unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Recommended Input Timing Requirements
VIH
(1)
Input High Level
SDA and SCL
0.7*VDDIO
Specification is ensured by design.
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Bidirectional Control Bus DC Timing Specifications (SCL, SDA) - I2C Compliant(1) (continued)
Over recommended supply and temperature ranges unless otherwise specified
Symbol
Parameter
Conditions
Min
SDA and SCL
Typ
GND
Max
0.3*VDDIO
Units
VIL
Input Low Level
VHY
Input Hysteresis
VOL
Output Low Level
SDA, IOL=0.5mA
IIN
Input Current
SDA or SCL, VIN=VDDOP OR GND
tR
SDA Rise Time-READ
ns
SDA Fall Time-READ
SDA, RPU = 10kΩ, Cb ≤ 400pF
(Figure 4)
430
tF
20
ns
tSU;DAT
SeeFigure 4
560
ns
tHD;DAT
SeeFigure 4
615
ns
>50
0
0.4
V
—10
10
µA
tSP
CIN
V
mV
SDA or SCL
50
ns
<5
pF
AC Timing Diagrams and Test Circuits
SDA
tf
tHD;STA
tLOW
tr
tBUF
tr
tf
SCL
tSU;STA
tHD;STA
tHIGH
tSU;STO
tSU;DAT
tHD;DAT
START
STOP
REPEATED
START
START
Figure 4. Bi-directional Control Bus Timing
Signal Pattern
Device Pin Name
T
PCLK
(RFB = H)
DIN/ROUT
Figure 5. “Worst Case” Test Pattern
Vdiff
80%
80%
20%
Vdiff = 0V
20%
tLHT
tHLT
Vdiff = (DOUT+) - (DOUT-)
Figure 6. Serializer CML Output Load and Transition Times
DOUT+
100 nF
50:
ZDiff = 100:
SCOPE
BW 8 4.0 GHz
100:
50:
DOUT-
100 nF
Figure 7. Serializer CML Output Load and Transition Times
16
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10/12,
HS,VS
DIN
PARALLEL-TO-SERIAL
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DOUT+
RL
DOUT-
PCLK
Figure 8. Serializer VOD Diagram
Single Ended
| VOS
DOUTV
V
OD
V
OD+
OD-
DOUT+
Differential
V
OD+
0V
(DOUT+)-(DOUT-)
V
OD-
Figure 9. Serializer VOD Diagram
RIN-
Single Ended
Vswing-
Vswing+
RIN+
0V
Differential
Vswing+
(RIN+)-(RIN-)
0V
Vswing-
Figure 10. Differential Vswing Diagram
80%
VDD
80%
PCLK
20%
20%
tCLKT
0V
tCLKT
Figure 11. Serializer Input Clock Transition Times
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tTCP
PCLK
VDDIO/2
tDIS
VDDIO/2
VDDIO/2
tDIH
VDDIO
DINn VDDIO/2
Setup
Hold
VDDIO/2
0V
Figure 12. Serializer Setup/Hold Times
PDB
VDDIO/2
PCLK
tPLD
Output Active
TRI-STATE
DOUT±
TRI-STATE
SYMBOL N+2
| |
SYMBOL N+1
| |
SYMBOL N
| |
DIN
| |
Figure 13. Serializer PLL Lock Time
SYMBOL N+3
tSD
SYMBOL N-3
SYMBOL N-2
SYMBOL N-1
| |
| |
| |
SYMBOL N
0V
| |
SYMBOL N-4
| |
|
|
|
DOUT+-
|
PCLK
VDDIO/2
Figure 14. Serializer Delay
PDB
VDDIO/2
| |
tDDLT
RIN±
LOCK
TRI-STATE
|
VDDIO/2
Figure 15. Deserializer Data Lock Time
80%
80%
Deserializer
8 pF
lumped
20%
20%
tCLH
tCHL
Figure 16. Deserializer LVCMOS Output Load and Transition Times
18
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SYMBOL N + 2
SYMBOL N + 3
SYMBOL N + 3
| |
0V
| |
SYMBOL N + 1
| |
SYMBOL N
RIN±
| |
SNLS420B – JULY 2012 – REVISED APRIL 2013
| |
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tDD
PCLK
SYMBOL N - 1
| ||
SYMBOL N - 2
| ||
| ||
SYMBOL N - 3
| ||
| ||
ROUTn
VDDIO/2
SYMBOL N
SYMBOL N+1
Figure 17. Deserializer Delay
tRCP
PCLK
VDDIO
1/2 VDDIO
1/2 VDDIO
0V
VDDIO
ROUT[n],
VS, HS
1/2 VDDIO
1/2 VDDIO
0V
tROS
tROH
Figure 18. Deserializer Output Setup/Hold Times
Ew
VOD (+)
EH
0V
EH
VOD (-)
tBIT (1 UI)
Figure 19. CML Output Driver
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PDB= H
OEN
VIH
VIL
VIH
OSS_SEL
VIL
RIN
(Diff.)
'RQ¶W &DUH
tSEH
tONS
LOCK
TRI-STATE
TRI-STATE
PASS
tSES
tONH
LOW
ACTIVE
HIGH
ROUT[0:11],
HS, VS
TRI-STATE
LOW
PCLK
(RFB = L)
TRI-STATE
LOW
TRI-STATE
LOW
HIGH
HIGH
ACTIVE
ACTIVE
LOW
TRI-STATE
LOW
TRI-STATE
Figure 20. Output State (Setup and Hold) Times
4
2
JITTER TRANSFER (dB)
0
-2
-4
-6
-8
-10
-12
-14
- 16
- 18
1.0E+04
1.0E+05
1.0E+06
1.0E+07
MODULATION FREQUENCY ( Hz)
Figure 21. Typical Serializer Jitter Transfer Function at 100MHz
20
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JITTER AMPLITUDE (UI)
0.65
0.60
0.55
0.50
0.45
1E+04
1E+05
1E+06
1E+07
JITTER FREQUENCY (Hz)
Figure 22. Typical Deserializer Input Jitter Tolerance Curve at 1.4Gbps Line Rate
Frequency
fdev (max)
FPCLK+
fdev
FPCLK
fdev (min)
FPCLK-
Time
1 / fmod
Figure 23. Spread Spectrum Clock Output Profile
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Table 1. DS90UB913Q Control Registers
Addr
(Hex)
0x00
Name
Bits
Field
7:1
DEVICE ID
0
SER ID SEL
0: Device ID is from ID[x]
1: Register I2C Device ID overrides ID[x]
RSVD
Reserved
I2C Device ID
RW
7
0x01
Default
0x58'h
Description
7-bit address of Serializer; 0x58'h
(0101_1000X'b) default
6
RDS
RW
0
Digital Output Drive Strength
1: High Drive Strength
0: Low Drive Strength
5
VDDIO Control
RW
1
Auto Voltage Control
1: Enable
0: Disable
4
VDDIO MODE
RW
1
VDDIOVoltage set
0: 1.8V
1: 3.3V
3
ANAPWDN
RW
0
This register can be set only through local I2C access
1: Analog power-down : Powers Down the analog block
in the Serializer
0: No effect
2
RSVD
RW
0
Reserved
1
DIGITAL
RESET1
RW
0
1: Resets the digital block except for register values
values. Does not affect device I2C Bus or Device ID. This
bit is self-clearing.
0: Normal Operation
0
DIGITAL RESET0
RW
1
1: Digital Reset, resets the entire digital block including all
register values.This bit is self-clearing.
0: Normal Operation.
Power and Reset
0x02
22
R/W
RESERVED
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SNLS420B – JULY 2012 – REVISED APRIL 2013
Table 1. DS90UB913Q Control Registers (continued)
Addr
(Hex)
Name
Bits
Field
R/W
Default
7
RX CRC Checker
Enable
RW
1
Back-channel CRC Checker Enable
1:Enabled
0:Disabled
6
TX Parity
Generator Enable
RW
1
Forward channel Parity Generator Enable
1: Enable
0: Disable
0
Clear CRC Error Counters.
This bit is NOT self-clearing.
1: Clear Counters
0: Normal Operation
0
Automatically Acknowledge I2C Remote Write
The mode works when the system is LOCKed.
1: Enable: When enabled, I2C writes to the Deserializer
(or any remote I2C Slave, if I2C PASS ALL is enabled)
are immediately acknowledged without waiting for the
Deserializer to acknowledge the write. The accesses are
then remapped to address specified in 0x06.
0: Disable
5
4
0x03
CRC Error Reset
I2C Remote Write
Auto Acknowledge
RW
RW
3
I2C Pass All
RW
0
1: Enable Forward Control Channel pass-through of all
I2C accesses to I2C Slave IDs that do not match the
Serializer I2C Slave ID. The I2C accesses are then
remapped to address specified in register 0x06.
0: Enable Forward Control Channel pass-through only of
I2C accesses to I2C Slave IDs matching either the remote
Deserializer Slave ID or the remote Slave ID.
2
I2C
PASSTHROUGH
RW
1
I2C Pass-Through Mode
0: Pass-Through Disabled
1: Pass-Through Enabled
0
1:Enabled : When enabled this registers overrides the
clock to PLL mode (External Oscillator mode or Direct
PCLK mode) defined through MODE pin and allows
selection through register 0x35 in the Serializer
0: Disabled : When disabled,cClock to PLL mode
(External Oscillator mode or Direct PCLK mode) is
defined through MODE pin on the Serializer.
1
Pixel Clock Edge Select
1: Parallel Interface Data is strobed on the Rising Clock
Edge.
0: Parallel Interface Data is strobed on the Falling Clock
Edge.
General
Configuration
1
OV_CLK2PLL
RW
0
TRFB
RW
7
RSVD
RW
0
Reserved
6
RSVD
RW
0
Reserved.
5
MODE_OVERRID
E
RW
0
Allows overriding mode select bits coming from backchannel
1: Overrides MODE select bits
0: Does not override MODE select bits
4
MODE_UP To
DATE
R
0
Indicates that the status of mode select from Deserializer
is up to date
3
Pin_MODE_12–bit
High Frequency
R
0
1: 12 bit high frequency mode is selected.
0: 12 bit high frequency mode is not selected.
2
Pin_MODE_10–bit
mode
R
0
1: 10 bit mode is selected.
0: 10 bit mode is not selected.
0x04
0x05
Description
RESERVED
Mode Select
1:0
RSVD
Reserved
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Table 1. DS90UB913Q Control Registers (continued)
Addr
(Hex)
0x06
0x07
Name
Bits
Desializer Device
ID
0
Freeze Device ID
RW
Default
DESAlias
7:1
SlaveID
7:1
SlaveAlias
7:1
0
Deserializer ALIAS
ID
RW
RW
Description
0x00
7-bit Deserializer Device ID Configures the I2C Slave ID
of the remote Deserializer. A value of 0 in this field
disables I2C access to the remote Deserializer. This field
is automatically configured by the Bidirectional Control
Channel once RX Lock has been detected. Software may
overwrite this value, but should also assert the FREEZE
DEVICE ID bit to prevent overwriting by the Bidirectional
Control Channel.
0
1: Prevents auto-loading of the Deserializer Device ID by
the bidirectional control channel. The ID will be frozen at
the value written.
0: Update
0
7-bit Remote Deserializer Device Alias ID Configures the
decoder for detecting transactions designated for an I2C
Deserializer device. The transaction will be remapped to
the address specified in the DES ID register.
A value of 0 in this field disables access to the remote
I2C Slave.
DES ID
0
0x09
R/W
7:1
0
0x08
Field
RSVD
Reserved
SLAVE ID
7-bit Remote Slave Device ID Configures the physical I2C
address of the remote I2C Slave device attached to the
remote Deserializer. If an I2C transaction is addressed to
the Slave Alias ID, the transaction will be remapped to
this address before passing the transaction across the
Bidirectional Control Channel to the Deserializer. A value
of 0 in this field disables access to the remote I2C slave.
RW
0x00
RSVD
Reserved
SLAVE ALIAS ID
7-bit Remote Slave Device Alias ID Configures the
decoder for detecting transactions designated for an I2C
Slave device attached to the remote Deserializer. The
transaction will be remapped to the address specified in
the Slave ID register. A value of 0 in this field disables
access to the remote I2C Slave.
RW
0x00
RSVD
Reserved
0x0A
CRC Errors
7:0
CRC Error Byte 0
R
0
Number of back-channel CRC errors during normal
operation
Least Significant byte
0x0B
CRC Errors
7:0
CRC Error Byte 1
R
0
Number of back-channel CRC errors during normal
operation
Most Significant byte
7:5
Rev-ID
R
0
Revision ID
0x00: Production
4
RX Lock Detect
R
0
1: RX LOCKED
0: RX not LOCKED
3
BIST CRC Error
Status
R
0
1: CRC errors in BIST mode
0: No CRC errors in BIST mode
2
PCLK Detect
R
0
1: Valid PCLK detected
0: Valid PCLK not detected
0
1: CRC error is detected during communication with
Deserializer.
This bit is cleared upon loss of link or assertion of CRC
ERROR RESET in register 0x04.
0: No effect
0
1: Cable link detected
0: Cable link not detected
This includes any of the following faults
— Cable Open
— '+' and '-' shorted
— Short to GND
— Short to battery
0x0C
General Status
1
0
24
DES Error
LINK Detect
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SNLS420B – JULY 2012 – REVISED APRIL 2013
Table 1. DS90UB913Q Control Registers (continued)
Addr
(Hex)
0x0D
0x0E
Name
GPO[0] and
GPO[1]
Configuration
GPO[2] and
GPO[3]
Configuration
Bits
Field
R/W
Default
7
GPO1 Output
Value
RW
0
Local GPIO Output Value This value is output on the
GPIO pin when the GPIO function is enabled, the local
GPIO direction is Output, and remote GPIO control is
disabled.
6
GPO1 Remote
Enable
RW
1
Remote GPIO Control
1: Enable GPIO control from remote Deserializer. The
GPIO pin needs to be an output, and the value is
received from the remote Deserializer.
0: Disable GPIO control from remote Deserializer.
5
GPO1 Direction
RW
0
1: Input
0: Output
4
GPO0 Enable
RW
1
1: GPIO enable
0: Tri-state
3
GPO0 Output
Value
0
Local GPIO Output Value This value is output on the
GPIO pin when the GPIO function is enabled, the local
GPIO direction is Output, and remote GPIO control is
disabled.
RW
Description
2
GPO0 Remote
Enable
RW
1
Remote GPIO Control
1: Enable GPIO control from remote Deserializer. The
GPIO pin needs to be an output, and the value is
received from the remote Deserializer.
0: Disable GPIO control from remote Deserializer.
1
GPO0 Direction
RW
0
1: Input
0: Output
0
GPO0 Enable
RW
1
1: GPIO enable
0: Tri-state
7
GPO3 Output
Value
RW
0
Local GPIO Output Value This value is output on the
GPIO pin when the GPIO function is enabled, the local
GPIO direction is Output, and remote GPIO control is
disabled.
6
GPO3 Remote
Enable
RW
0
Remote GPIO Control
1: Enable GPIO control from remote Deserializer. The
GPIO pin needs to be an output, and the value is
received from the remote Deserializer.
0: Disable GPIO control from remote Deserializer.
5
GPO3 Direction
RW
1
1: Input
0: Output
4
GPO3 Enable
RW
1
1: GPIO enable
0: Tri-state
3
GPO2 Output
Value
RW
0
Local GPIO Output Value This value is output on the
GPIO pin when the GPIO function is enabled, the local
GPIO direction is Output, and remote GPIO control is
disabled.
2
GPO2 Remote
Enable
RW
1
Remote GPIO Control
1: Enable GPIO control from remote Deserializer. The
GPIO pin needs to be an output, and the value is
received from the remote Deserializer.
0: Disable GPIO control from remote Deserializer.
1
GPO2 Direction
RW
0
1: Input
0: Output
0
GPO2 Enable
RW
1
1: GPIO enable
0: Tri-state
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Table 1. DS90UB913Q Control Registers (continued)
Addr
(Hex)
Name
Bits
Field
7:5
RSVD
Reserved
SDA Output Delay
00
SDA Output Delay This field configures output delay on
the SDA output. Setting this value will increase output
delay in units of 50ns. Nominal output delay values for
SCL to SDA are:
00 : 350ns
01: 400ns
10: 450ns
11: 500ns
4:3
0x0F
0x10
0x11
26
R/W
RW
Default
2
Local Write Disable
RW
0
Disable Remote Writes to Local Registers Setting this bit
to a 1 will prevent remote writes to local device registers
from across the control channel. This prevents writes to
the Serializer registers from an I2C master attached to
the Deserializer. Setting this bit does not affect remote
access to I2C slaves at the Serializer.
1
I2C Bus Timer
Speed up
RW
0
Speed up I2C Bus Watchdog Timer
1: Watchdog Timer expires after approximately 50
microseconds
0: Watchdog Timer expires after approximately 1 second.
0
1. Disable I2C Bus Watchdog Timer When the I2C
Watchdog Timer may be used to detect when the I2C bus
is free or hung up following an invalid termination of a
transaction. If SDA is high and no signalling occurs for
approximately 1 second, the I2C bus will assumed to be
free. If SDA is low and no signaling occurs, the device
will attempt to clear the bus by driving 9 clocks on SCL
0: No effect
I2C Master Config
0
I2C Bus Timer
Disable
7
RSVD
RW
Reserved
6:4
SDA Hold Time
RW
0x1
Internal SDA Hold Time. This field configures the amount
of internal hold time provided for the SDA input relative to
the SCL input. Units are 50ns.
3:0
I2C Filter Depth
RW
0x7
I2C Glitch Filter Depth This field configures the maximum
width of glitch pulses on the SCL and SDA inputs that will
be rejected. Units are 10ns.
0x82
I2C Master SCL High Time This field configures the high
pulse width of the SCL output when the Serializer is the
Master on the local I2C bus. Units are 50 ns for the
nominal oscillator clock frequency. The default value is
set to provide a minimum (4µs + 1µs of rise time for
cases where rise time is very fast) SCL high time with the
internal oscillator clock running at 26MHz rather than the
nominal 20MHz.
I2C SCL Low Time This field configures the low pulse
width of the SCL output when the Serializer is the Master
on the local I2C bus. This value is also used as the SDA
setup time by the I2C Slave for providing data prior to
releasing SCL during accesses over the Bidirectional
Control Channel. Units are 50 ns for the nominal
oscillator clock frequency. The default value is set to
provide a minimum (4.7µs + 0.3µs of fall time for cases
where fall time is very fast) SCL low time with the internal
oscillator clock running at 26MHz rather than the nominal
20MHz.
I2C Control
SCL High Time
Description
7:0
SCL High Time
RW
0x12
SCL LOW Time
7:0
SCL Low Time
RW
0x82
0x13
General Purpose
Control
7:0
GPCR[7:0]
RW
0
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1: High
0: Low
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SNLS420B – JULY 2012 – REVISED APRIL 2013
Table 1. DS90UB913Q Control Registers (continued)
Addr
(Hex)
Name
Bits
Field
7:3
RSVD
Reserved
Clock Source
Allows choosing different OSC clock frequencies for
forward channel frame.
OSC Clock Frequency in Functional Mode when OSC
mode is selected or when the selected clock source is
not present e.g. missing PCLK/ External Oscillator. See
Table 3 for oscillator clock frequencies when PCLK/
External Clock is missing.
2:1
0x14
R/W
RW
0x0
RW
0
BIST Enable
0x15–0
x1D
7:1
BCC Watchdog
Timer
RW
0x7F
0
BCC Watchdog
Timer Disable
RW
0
BCC Watchdog
Control
The watchdog timer allows termination of a control
channel transaction if it fails to complete within a
programmed amount of time. This field sets the
Bidirectional Control Channel Watchdog Timeout value in
units of 2ms. This field should not be set to 0.
Disable Bidirectional Control Channel Watchdog Timer
1: Disables BCC Watchdog Timer operation
0: Enables BCC Watchdog Timer operation
RESERVED
CRC Errors
7:0
BIST Mode CRC
Errors Count
R
0x2B0x34
Number of CRC Errors in the back channel when in BIST
mode
0
RESERVED
7:4
0x35
BIST Control:
1: Enable BIST mode
0: Disable BIST mode
RESERVED
0x1F0x29
0x2A
Description
BIST Control
0
0x1E
Default
PLL Clock
Overwrite
RSVD
Reserved
3
PIN_LOCK to
External Oscillator
RW
0
Status of mode select pin
1: Indicates External Oscillator mode is selected by
mode-resistor
0: External Oscillator mode is not selected by moderesistor
2
PIN_LOCK2Oscilla
tor
RW
0
Status of mode select pin
1: Indicates PCLK mode is selected by mode-resistor
0: PCLK mode not selected by mode-resistor
1
LOCK to External
Oscillator
0
Affects only when 0x03[1]=1 (OV_CLK2PLL) and
0x35[0]=0.
1: Routes GPO3 directly to PLL
0: Allows PLL to lock to PCLK"
0
RSVD
RW
Reserved
Table 2. DS90UB914Q Control Registers
Addr
(Hex)
Name
Bits
7:1
0x00
I2C Device ID
0
Field
R/W
Default
DEVICE ID
RW
0x60'h
Deserializer ID
Select
RW
0
Description
7-bit address of Deserializer;
0x60h
0: De-Serializer Device ID is set using address
coming from CAD
1: Register I2C Device ID overrides ID[x]
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Table 2. DS90UB914Q Control Registers (continued)
Addr
(Hex)
Name
Bits
7:6
5
4:2
0x01
0x02
R/W
Default
Description
RSVD
Reserved
ANAPWDN
This register can be set only through local I2C
access
1: Analog power-down : Powers Down the
analog block in the Serializer
0: No effect
RW
0
RSVD
Reserved
Reset
1
Digital Reset 1
RW
0
Digital Reset Resets the entire digital block
except registers. This bit is self-clearing.
1: Reset
0: No effect
0
Digital Reset 0
RW
0
Digital Reset Resets the entire digital block
including registers. This bit is self-clearing.
1: Reset
0: No effect
7
RSVD
Reserved
6
RSVD
Reserved
5
Auto-Clock
RW
0
1: Output PCLK or OSC clock when not
LOCKED
0: Only PCLK
4
SSCG LFMODE
RW
0
1: Selects 8x mode for 10-18 MHz frequency
range in SSCG
0: SSCG running at 4X mode
0
SSCG Select
0000: Normal Operation, SSCG OFF
0001: fmod (kHz) PCLK/2168, fdev +/-0.50%
0010: fmod (kHz) PCLK/2168, fdev +/-1.00%
0011: fmod (kHz) PCLK/2168, fdev +/-1.50%
0100: fmod (kHz) PCLK/2168, fdev +/-2.00%
0101: fmod (kHz) PCLK/1300, fdev +/-0.50%
0110: fmod (kHz) PCLK/1300, fdev +/-1.00%
0111: fmod (kHz) PCLK/1300, fdev +/-1.50%
1000: fmod (kHz) PCLK/1300, fdev +/-2.00%
1001: fmod (kHz) PCLK/868, fdev +/-0.50%
1010: fmod (kHz) PCLK/868, fdev +/-1.00%
1011: fmod (kHz) PCLK/868, fdev +/-1.50%
1100: fmod (kHz) PCLK/868, fdev +/-2.00%
1101: fmod (kHz) PCLK/650, fdev +/-0.50%
1110: fmod (kHz) PCLK/650, fdev +/-1.00%
1111: fmod (kHz) PCLK/650, fdev +/-1.50%
Note: This regsiter should be changed only
after disabling SSCG.
General
Configuration 0
3:0
28
Field
SSCG
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SNLS420B – JULY 2012 – REVISED APRIL 2013
Table 2. DS90UB914Q Control Registers (continued)
Addr
(Hex)
Name
Bits
Field
R/W
Default
7
RX Parity Checker
Enable
RW
1
Forward Channel Parity Checker Enable
1: Enable
0: Disable
6
TX CRC Checker
Enable
RW
1
Back Channel CRC Generator Enable
1: Enable
0: Disable
5
VDDIO Control
RW
1
Auto voltage control
1: Enable (auto detect mode)
0: Disable
4
VDDIO Mode
RW
0
VDDIO voltage set
1: 3.3V
0: 1.8V
RW
1
I2C Pass-Through Mode
1: Pass-Through Enabled
0: Pass-Through Disabled
0x03
I2C Passthrough
3
General
Configuration 1
2
AUTO ACK
RW
0
Automatically Acknowledge I2C Remote Write
When enabled, I2C writes to the Deserializer (or
any remote I2C Slave, if I2C PASS ALL is
enabled) are immediately acknowledged
without waiting for the Deserializer to
acknowledge the write. The accesses are then
remapped to address specified in 0x06. This
allows I2C bus without LOCK.
1: Enable
0: Disable
1
Parity Error Reset
RW
0
Parity Error Reset, This bit is self-clearing.
1: Parity Error Reset
0: No effect
1
Pixel Clock Edge Select
1: Parallel Interface Data is strobed on the
Falling Clock Edge.
0: Parallel Interface Data is strobed on the
Rising Clock Edge.
0
0x04
EQ Feature
Control 1
7:0
RRFB
EQ level - when
AEQ bypass is
enabled EQ setting
is provided by this
register
RW
RW
0x05
0x07
0x00
Equalization gain
0x00 = ~0.0 dB
0x01 = ~4.5 dB
0x03 = ~6.5 dB
0x07 = ~7.5 dB
0x0F = ~8.0 dB
0x1F = ~11.0 dB
0x3F = ~12.5 dB
RESERVED
7:1
0x06
Description
SER ID
Remote ID
RW
RW
0
Freeze Device ID
7:1
Serializer Alias ID
SER Alias
0
RSVD
RW
0x0C
0
0x00
Remote Serializer ID
Freeze Serializer Device ID Prevent autoloading of the Serializer Device ID from the
Forward Channel. The ID will be frozen at the
value written.
7-bit Remote Serializer Device Alias ID
Configures the decoder for detecting
transactions designated for an I2C Deserializer
device. The transaction will be remapped to the
address specified in the SER ID register. A
value of 0 in this field disables access to the
remote I2C Slave.
Reserved
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Table 2. DS90UB914Q Control Registers (continued)
Addr
(Hex)
0x08
Name
Slave ID[0]
Bits
7:1
0
0x09
Slave ID[1]
7:1
0
0x0A
Slave ID[2]
7:1
0
0x0B
Slave ID[3]
7:1
0
0x0C
Slave ID[4]
7:1
0
0x0D
Slave ID[5]
7:1
0
30
Field
Slave ID0
R/W
RW
Default
Description
0
7-bit Remote Slave Device ID 0 Configures the
physical I2C address of the remote I2C Slave
device attached to the remote Serializer. If an
I2C transaction is addressed to the Slave Alias
ID0, the transaction will be remapped to this
address before passing the transaction across
the Bidirectional Control Channel to the
Serializer.
RSVD
Reserved
Slave ID1
7-bit Remote Slave Device ID 1 Configures the
physical I2C address of the remote I2C Slave
device attached to the remote Serializer. If an
I2C transaction is addressed to the Slave Alias
ID1, the transaction will be remapped to this
address before passing the transaction across
the Bidirectional Control Channel to the
Serializer.
RW
0
RSVD
Reserved
Slave ID2
7-bit Remote Slave Device ID 2 Configures the
physical I2C address of the remote I2C Slave
device attached to the remote Serializer. If an
I2C transaction is addressed to the Slave Alias
ID2, the transaction will be remapped to this
address before passing the transaction across
the Bidirectional Control Channel to the
Serializer.
RW
0x00
RSVD
Reserved
Slave ID3
7-bit Remote Slave Device ID 3 Configures the
physical I2C address of the remote I2C Slave
device attached to the remote Serializer. If an
I2C transaction is addressed to the Slave Alias
ID3, the transaction will be remapped to this
address before passing the transaction across
the Bidirectional Control Channel to the
Serializer.
RW
0
RSVD
Reserved
Slave ID4
7-bit Remote Slave Device ID 4 Configures the
physical I2C address of the remote I2C Slave
device attached to the remote Serializer. If an
I2C transaction is addressed to the Slave Alias
ID4, the transaction will be remapped to this
address before passing the transaction across
the Bidirectional Control Channel to the
Serializer.
RW
0
RSVD
Reserved
Slave ID5
7-bit Remote Slave Device ID 5 Configures the
physical I2C address of the remote I2C Slave
device attached to the remote Serializer. If an
I2C transaction is addressed to the Slave Alias
ID5 , the transaction will be remapped to this
address before passing the transaction across
the Bidirectional Control Channel to the
Serializer.
RSVD
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RW
0x00
Reserved
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SNLS420B – JULY 2012 – REVISED APRIL 2013
Table 2. DS90UB914Q Control Registers (continued)
Addr
(Hex)
0x0E
Name
Slave ID[6]
Bits
7:1
0
0x0F
Slave ID[7]
7:1
0
0x10
Slave Alias[0]
7:1
0
0x11
Slave Alias[1]
7:1
0
0x12
Slave Alias[2]
7:1
0
0x13
Slave Alias[3]
7:1
0
Field
Slave ID6
R/W
RW
Default
Description
0
7-bit Remote Slave Device ID 6 Configures the
physical I2C address of the remote I2C Slave
device attached to the remote Serializer. If an
I2C transaction is addressed to the Slave Alias
ID6, the transaction will be remapped to this
address before passing the transaction across
the Bidirectional Control Channel to the
Serializer.
RSVD
Reserved
Slave ID7
7-bit Remote Slave Device ID 7 Configures the
physical I2C address of the remote I2C Slave
device attached to the remote Serializer. If an
I2C transaction is addressed to the Slave Alias
ID7, the transaction will be remapped to this
address before passing the transaction across
the Bidirectional Control Channel to the
Serializer.
RW
0x00
RSVD
Reserved
Slave Alias ID0
7-bit Remote Slave Device Alias ID 0
Configures the decoder for detecting
transactions designated for an I2C Slave device
attached to the remote Serializer. The
transaction will be remapped to the address
specified in the Slave ID0 register. A value of 0
in this field disables access to the remote I2C
Slave.
RW
0x00
RSVD
Reserved
Slave Alias ID1
7-bit Remote Slave Device Alias ID 1
Configures the decoder for detecting
transactions designated for an I2C Slave device
attached to the remote Serializer. The
transaction will be remapped to the address
specified in the Slave ID1 register. A value of 0
in this field disables access to the remote I2C
Slave.
RW
0x00
RSVD
Reserved
Slave Alias ID2
7-bit Remote Slave Device Alias ID 2
Configures the decoder for detecting
transactions designated for an I2C Slave device
attached to the remote Serializer. The
transaction will be remapped to the address
specified in the Slave ID2 register. A value of 0
in this field disables access to the remote I2C
Slave.
RW
0x00
RSVD
Reserved
Slave Alias ID3
7-bit Remote Slave Device Alias ID 3
Configures the decoder for detecting
transactions designated for an I2C Slave device
attached to the remote Serializer. The
transaction will be remapped to the address
specified in the Slave ID3 register. A value of 0
in this field disables access to the remote I2C
Slave.
RSVD
RW
0x00
Reserved
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Table 2. DS90UB914Q Control Registers (continued)
Addr
(Hex)
0x14
Name
Slave Alias[4]
Bits
7:1
0
0x15
Slave Alias[5]
7:1
0
0x16
Slave Alias[6]
7:1
0
0x17
Slave Alias[7]
7:1
0
0x18
Parity Errors
Threshold
7:0
Field
Slave Alias ID4
R/W
RW
Default
Description
0x00
7-bit Remote Slave Device Alias ID 4
Configures the decoder for detecting
transactions designated for an I2C Slave device
attached to the remote Serializer. The
transaction will be remapped to the address
specified in the Slave ID4 register. A value of 0
in this field disables access to the remote I2C
Slave.
RSVD
Reserved
Slave Alias ID5
7-bit Remote Slave Device Alias ID 5
Configures the decoder for detecting
transactions designated for an I2C Slave device
attached to the remote Serializer. The
transaction will be remapped to the address
specified in the Slave ID5 register. A value of 0
in this field disables access to the remote I2C
Slave.
RW
0x00
RSVD
Reserved
Slave Alias ID6
7-bit Remote Slave Device Alias ID 6
Configures the decoder for detecting
transactions designated for an I2C Slave device
attached to the remote Serializer. The
transaction will be remapped to the address
specified in the Slave ID6 register. A value of 0
in this field disables access to the remote I2C
Slave.
RW
0x00
RSVD
Reserved
Slave Alias ID7
7-bit Remote Slave Device Alias ID 7
Configures the decoder for detecting
transactions designated for an I2C Slave device
attached to the remote Serializer. The
transaction will be remapped to the address
specified in the Slave ID7 register. A value of 0
in this field disables access to the remote I2C
Slave.
RW
0x00
RSVD
Reserved
Parity Error
Threshold Byte 0
0
Parity errors threshold on the Forward channel
during normal information. This sets the
maximum number of parity errors that can be
counted using register 0x1A.
Least significant Byte.
RW
0x19
Parity Errors
Threshold
7:0
Parity Error
Threshold Byte 1
RW
0
Parity errors threshold on the Forward channel
during normal operation. This sets the
maximum number of parity errors that can be
counted using register 0x1B.
Most significant Byte
0x1A
Parity Errors
7:0
Parity Error Byte 0
RW
0
Number of parity errors in the Forward channel
during normal operation.
Least significant Byte
0x1B
Parity Errors
7:0
Parity Error Byte 1
RW
0
Number of parity errors in the Forward channel
during normal operation
Most significant Byte
32
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SNLS420B – JULY 2012 – REVISED APRIL 2013
Table 2. DS90UB914Q Control Registers (continued)
Addr
(Hex)
0x1C
Name
Bits
Field
R/W
Default
R
0
7:4
Rev-ID
3
RSVD
2
Parity Error
R
1
Signal Detect
R
0
Lock
R
7
GPIO1 Output
Vaue
6
RSVD
0
0
0
RW
0
RW
1
1: Serial input detected
0: Serial input not detected
De-Serializer CDR, PLL's clock to recovered
clock frequency
1: De-Serializer locked to recovered clock
0: De-Serializer not locked
Local GPIO Output Value This value is the
output on the GPIO pin when the GPIO function
is enabled, the local GPIO direction is Output.
Local GPIO Direction
1: Input
0: Output
4
GPIO1 Enable
RW
1
GPIO Function Enable
1: Enable GPIO operation
0: Enable normal operation
3
GPIO0 Output
Value
RW
0
Local GPIO Output Value This value is output
on the GPIO pin when the GPIO function is
enabled, the local GPIO direction is Output.
2
RSVD
1
GPIO0 Direction
RW
1
Local GPIO Direction
1: Input
0: Output
0
GPIO0 Enable
RW
1
GPIO Function Enable
1: Enable GPIO operation
0: Enable normal operation
RW
0
Local GPIO Output Value This value is the
output on the GPIO pin when the GPIO function
is enabled, the local GPIO direction is Output.
GPIO[1] and
GPIO[0] Config
7
0x1E
Parity Error detected
1: Parity Errors detected
0: No Parity Errors
Reserved
5
0x1D
Revision ID
0x0000: Production
Reserved
General Status
GPIO1 Direction
Description
GPIO3 Output
Vaue
Reserved
6
RSVD
5
GPIO3 Direction
RW
1
Local GPIO Direction
1: Input
0: Output
4
GPIO3 Enable
RW
1
GPIO Function Enable
1: Enable GPIO operation
0: Enable normal operation
3
GPIO2 Output
Value
RW
0
Local GPIO Output Value This value is output
on the GPIO pin when the GPIO function is
enabled, the local GPIO direction is Output.
2
RSVD
1
GPIO2 Direction
RW
1
Local GPIO Direction
1: Input
0: Output
0
GPIO2 Enable
RW
1
GPIO Function Enable
1: Enable GPIO operation
0: Enable normal operation
GPIO[3] and
GPIO[2] Config
Reserved
Reserved
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Table 2. DS90UB914Q Control Registers (continued)
Addr
(Hex)
0x1F
0x20
0x21
34
Name
Mode and OSS
Select
Bits
Field
R/W
Default
Description
7
OEN_OSS
Override
RW
0
Allows overriding OEN and OSS select coming
from Pins
1: Overrides OEN/OSS_SEL selected by pins
0: Does NOT override OEN/OSS_SEL select
by pins
6
OEN Select
RW
0
OEN configuration from register
5
OSS Select
R
0
OSS_SEL configuration from register
4
MODE_OVERRID
E
RW
0
Allows overriding mode select bits coming from
back-channel
1: Overrides MODE select bits
0: Does not override MODE select bits
3
PIN_MODE_12–bit
HF mode
R
0
2
PIN_MODE_10 bit
mode
R
0
1
MODE_12–bit High
Frequency
0
MODE_10–bit
mode
RW
RW
Status of mode select pin
0
Selects 12 bit high frequency mode. This bit is
automatically updated by the mode settings
from RX unless MODE_OVERRIDE is SET
1: 12 bit high frequency mode is selected.
0: 12 bit high frequency mode is not selected.
0
Selects 10 bit mode. This bit is automatically
updated by the mode settings from RX unless
MODE_OVERRIDE is SET
1: Enables 10 bit mode.
0: Disables 10 bit mode.
7:1
BCC Watchdog
timer
RW
0
The watchdog timer allows termination of a
control channel transaction if it fails to complete
within a programmed amount of time. This field
sets the Bidirectional Control Channel
Watchdog Timeout value in units of 2ms. This
field should not be set to 0.
0
BCC Watchdog
Timer Disable
RW
0
Disable Bidirectional Control Channel
Watchdog Timer
1: Disables BCC Watchdog Timer operation
0: Enables BCC Watchdog Timer operation
7
I2C pass through
all
RW
0
I2C Pass-Through All Transactions
0: Disabled
1: Enabled
6:4
I2C SDA Hold
RW
0
Internal SDA Hold Time This field configures
the amount of internal hold time provided for
the SDA input relative to the SCL input. Units
are 50ns.
3:0
I2C Filter Depth
RW
0
I2C Glitch Filter Depth This field configures the
maximum width of glitch pulses on the SCL and
SDA inputs that will be rejected. Units are 10ns.
BCC Watchdog
Control
I2C Control 1
Status of mode select pin
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SNLS420B – JULY 2012 – REVISED APRIL 2013
Table 2. DS90UB914Q Control Registers (continued)
Addr
(Hex)
Name
Bits
R/W
Default
Description
Control Channel Sequence Error Detected This
bit indicates a sequence error has been
detected in forward control channel.
1: If this bit is set, an error may have occurred
in the control channel operation
0: No forward channel errors have been
detected on the control channel
7
Forward Channel
Sequence Error
R
0
6
Clear Sequence
Error
RW
0
5
RSVD
Reserved
SDA Output Delay
0
SDA Output Delay This field configures output
delay on the SDA output. Setting this value will
increase output delay in units of 50ns. Nominal
output delay values for SCL to SDA are:
00 : 350ns
01: 400ns
10: 450ns
11: 500ns
0
Disable Remote Writes to local registers
Setting this bit to a 1 will prevent remote writes
to local device registers from across the control
channel. This prevents writes to the
Deserializer registers from an I2C master
attached to the Serializer. Setting this bit does
not affect remote access to I2C slaves at the
Deserializer.
0
Speed up I2C Bus Watchdog Timer
1: Watchdog Timer expires after approximately
50µs
0: Watchdog Timer expires after approximately
1s.
Disable I2C Bus Watchdog Timer When the I2C
Watchdog Timer may be used to detect when
the I2C bus is free or hung up following an
invalid termination of a transaction. If SDA is
high and no signaling occurs for approximately
1 second, the I2C bus will assumed to be free.
If SDA is low and no signaling occurs, the
device will attempt to clear the bus by driving 9
clocks on SCL
4:3
0x22
Field
RW
I2C Control 2
2
Local Write Disable
RW
2
1
General Purpose
Control
RW
0
7:0
GPCR
RW
0
7:4
RSVD
3
0x24
0
Parity Error Count
7:0
Scratch Register
Reserved
BIST Pin
Configuration
RW
1
Bist Configured through Pin.
1: Bist configured through pin.
0: Bist configured through register bit
"reg_24[0]"
BIST Clock Source
RW
00
BIST Clock Source
See Table 4
BIST Enable
RW
0
BIST Control
1: Enabled
0: Disabled
R
0
Number of Forward channel Parity errors in the
BIST mode.
BIST Control
2:1
0x25
RW
I2C Bus Timer
Disable
0
0x23
I C Bus Timer
Speedup
Clears the Sequence Error Detect bit
BIST Error Count
0x26–0
x3B
RESERVED
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Table 2. DS90UB914Q Control Registers (continued)
Addr
(Hex)
Name
Bits
7:2
Oscillator output
divider select
0x3C
1:0
Field
R/W
Reserved
OSC OUT
DIVIDER SEL
Selects the divider for the OSC clock out on
PCLK when system is not locked and selected
by OEN/OSSSEL 0x02[5]
00: 50M (+/- 30%)
01: 25M (+/- 30%)
1X: 12.5M (+/- 30%)
RW
CML Output
Enable
4
3:0
0x41
SCL High Time
SCL Low Time
7:0
RSVD
Reserved
CML OUT Enable
SCL High Time
0x82
0x82
I2C SCL Low Time This field configures the low
pulse width of the SCL output when the DeSerializer is the Master on the local I2C bus.
This value is also used as the SDA setup time
by the I2C Slave for providing data prior to
releasing SCL during accesses over the
Bidirectional Control Channel. Units are 50 ns
for the nominal oscillator clock frequency. The
default value is set to provide a minimum
(4.7µs + 0.3µs of fall time for cases where fall
time is very fast) SCL low time with the internal
oscillator clock running at 26MHz rather than
the nominal 20MHz.
RSVD
RW
RW
Reserved
Force Back
Channel Error
Force One Back
Channel Error
RW
0
1: This bit introduces multiple errors into Back
channel frame.
0: No effect
RW
0
1: This bit introduces ONLY one error into Back
channel frame. Self clearing bit
0: No effect
0x430x4C
0x4D
RESERVED
AEQ Test Mode
Select
7
6
0x4E
0: CML Loop-through Driver is powered up
1: CML Loop-through Driver is powered down.
I2C Master SCL High Time This field configures
the high pulse width of the SCL output when
the De-Serializer is the Master on the local I2C
bus. Units are 50 ns for the nominal oscillator
clock frequency. The default value is set to
provide a minimum (4μs + 0.3μs of rise time for
cases where rise time is very fast) SCL high
time with the internal oscillator clock running at
26MHz rather than the nominal 20MHz.
7:2
0
1
Reserved
SCL Low Time
CRC Force Error
RW
RSVD
7:0
1
0x42
0
RESERVED
7:5
0x40
Description
RSVD
0x3D0x3E
0x3F
Default
EQ Value
RSVD
Reserved
AEQ Bypass
RW
5:0
RSVD
7:0
AEQ / Manual Eq
Readback
0
Bypass AEQ and use set manual EQ value
using register 0x04
Reserved
R
0
Read back the adaptive and manual
Equalization value
Table 3. Clock Sources for Forward Channel Frame on the Serializer During Normal Operation
DS90UB913Q
Reg 0x14 [2:1]
36
10–bit
Mode
12–bit
High Frequency Mode
12–bit
Low Frequency Mode
00
50 MHz
37.5 MHz
25 MHz
01
100 MHz
75 MHz
50 MHz
10
50 MHz
37.5 MHz
25 MHz
11
25MHz
18.75 MHz
12.5 MHz
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Table 4. BIST Clock Sources
DS90UB914Q
Reg 0x24 [2:1]
10–bit
Mode
12–bit
High Frequency Mode
12–bit
Low Frequency Mode
00
PCLK
PCLK
PCLK
01
100 MHz
75 MHz
50 MHz
10
50 MHz
37.5 MHz
25 MHz
11
25MHz
18.75 MHz
12.5 MHz
Functional Description
The DS90UB913/914Q FPD- Link III chipsets are intended to link mega-pixel camera imagers and video
processors in ECUs. The Serializer/Deserializer chipset can operate from 10MHz to 100MHz pixel clock
frequency. The DS90UB913Q device transforms a 10/12-bit wide parallel LVCMOS data bus along with a
bidirectional control channel control bus into a single high-speed differential pair. The high speed serial bit stream
contains an embedded clock and DC-balanced information which enhances signal quality to support AC
coupling. The DS90UB914Q device receives the single serial data stream and converts it back into a 10/12-bit
wide parallel data bus together with the control channel data bus. The DS90UB913/914Q chipsets can accept up
to
■12 bits of DATA+2 bits SYNC for an input PCLK range of 10MHz-50MHz in the 12-bit low frequency mode
■ 12 bits DATA + 2 SYNC bits for an input PCLK range of 15MHz to 75MHz in the 12-bit high frequency mode
■10 bits DATA + 2 SYNC bits for an input PCLK range of 20MHz to 100MHz in the 10-bit mode.
The DS90UB914Q chipset has a 2:1 multiplexer which allows customers to select between two Serializer inputs.
The control channel function of the DS90UB913/DS90UB914Q chipset provides bidirectional communication
between the image sensor and ECUs. The integrated bidirectional control channel transfers data bidirectionally
over the same differential pair used for video data interface. This interface offers advantages over other chipsets
by eliminating the need for additional wires for programming and control. The bidirectional control channel bus is
controlled via an I2C port. The bidirectional control channel offers asymmetrical communication and is not
dependent on video blanking intervals.
The DS90UB913/914Q chipset offer customers the choice to work with different clocking schemes. The
DS90UB913/914Q chipsets can use an external oscillator as the reference clock source for the PLL or PCLK
from the imager as primary reference clock to the PLL.
Transmission Media
The DS90UB913/914Q chipset is intended to be used in a point-to-point configuration through a shielded twisted
pair cable. The Serializer and Deserializer provide internal termination to minimize impedance discontinuities.
The interconnect (cable and connectors) should have a differential impedance of 100 Ohms. The maximum
length of cable that can be used is dependent on the quality of the cable (gauge, impedance), connector,
board(discontinuities, power plane), the electrical environment (e.g power stability, ground noise, input clock
jitter, PCLK frequency, etc). The resulting signal quality at the receiving end of the transmission media may be
assessed by monitoring the differential eye opening of the serial data stream. A differential probe should be used
to measure across the termination resistor at the CMLOUTP/N pins. Figure 19 illustrates the minimum eye width
and eye height that is necessary for bit error free operation.
DS90UB913/914Q Operation with External Oscillator as Reference Clock
In some applications, the pixel clock that comes from the imager can have jitter which exceeds the tolerance of
the DS90UB913/914Q chipsets. In this case, the DS90UB913Q device should be operated by using an external
clock source as the reference clock for the DS90UB913/914Q chipsets. This is the recommended operating
mode. The external oscillator clock output goes through a divide-by-2 circuit in the DS90UB913Q Serializer and
this divided clock output is used as the reference clock for the imager. The output data and pixel clock from the
imager are then fed into the DS90UB913Q device. Figure 24 shows the operation of the DS90UB13/914Q
chipsets while using an external automotive grade oscillator.
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DS90UB913Q
Serializer
FPD Link IIIHigh Speed
Camera Data
DOUT+
10 or 12
Image
Sensor
DATA
HSYNC
DIN[11:0] or
DIN[9:0]
HSYNC,
VSYNC
DOUT-
VSYNC
Pixel Clock
DS90UB914Q
Deserializer
Camera Data
RIN+
10 or 12
ROUT[11:0]
or
ROUT[9:0]
HSYNC,
VSYNC
RIN-
Bi-Directional
Control Channel
PCLK
PCLK
DATA
HSYNC
VSYNC
Pixel Clock
ECU Module
SDA
SDA
SCL
2
SCL
PLL
GPIO[3:0]
GPO[1:0]
GPO[1:0]
SDA
Camera Unit
Reference Clock
(Ext. OSC/2)
4
GPO[3:0]
SCL
Microcontroller
SDA
SCL
GPO3
÷2
GPO2
External
Oscillator
Figure 24. DS90UB913/914Q Operation in the External Oscillator Mode
When the DS90UB913Q device is operated using an external oscillator, the GPO3 pin on the DS90UB913Q is
the input pin for the external oscillator. In applications where the DS90UB913Q device is operated from an
external oscillator, the divide-by-2 circuit in the DS90UB913Q device feeds back the divided clock output to the
imager device through GPO2 pin. The pixel clock to external oscillator ratios needs to be fixed for the 12–bit high
frequency mode and the 10–bit mode. In the 10-bit mode, the pixel clock frequency divided by the external
oscillator frequency must be 2. In the 12-bit high frequency mode, the pixel clock frequency divided by
the external oscillator frequency must be 1.5. For example, if the external oscillator frequency is 48MHz in the
10–bit mode, the pixel clock frequency of the imager needs to be twice of the external oscillator frequency, i.e.
96MHz. If the external oscillator frequency is 48MHz in the 12-bit high frequency mode, the pixel clock frequency
of the imager needs to be 1.5 times of the external oscillator frequency, i.e. 72MHz. In this mode, GPO2 and
GPO3 on the Serializer cannot act as the output of the input signal coming from GPIO2 or GPIO3 on the
Deserializer.
DS90UB913/914Q Operation with Pixel Clock from Imager as Reference Clock
The DS90UB913/914Q chipsets can be operated by using the pixel clock from the imager as the reference
clock.Figure 25 shows the operation of the DS90UB913/914Q chipsets using the pixel clock from the imager. If
the DS90UB913Q device is operated using the pixel clock from the imager as the reference clock, then the
imager uses an external oscillator as its reference clock. There are 4 GPIOs on the Serializer and 4 GPIOs on
the Deserializer in this mode.
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DS90UB914Q
Deserializer
DS90UB913Q
FPD-Link III
Camera Data
Image
Sensor
Camera Data
DOUT+
10 or 12
DIN[11:0] or
DIN[9:0]
FV,LV
YUV
HSYNC
VSYNC
ROUT[11:0]
or
ROUT[9:0]
FV, LV
DOUT-
SDA
SCL
YUV
HSYNC
RIN0-
VSYNC
Bi-Directional
Back Channel
SDA
SCL
10 or 12
RIN0+
PCLK
Pixel Clock
4
GPO[3:0]
GPIO[3:0]
GPO
Pixel Clock
Camera Unit
ECU Module
RIN1+
RIN1-
PLL
4
GPIO
SDA
PCLK
SCL
Microcontroller
SDA
SCL
Ext.
Oscillator
Figure 25. DS90UB913Q/914Q Operation in PCLK mode
MODE Pin on Serializer
The mode pin on the Serializer can be configured to select if the DS90UB913Q device is to be operated from the
external oscillator or the PCLK from the imager. The pin must be pulled to VDD(1.8V, not VDDIO) with a 10 kΩ
resistor and a pull down resistor (RMODE) of the recommended value to set the modes shown in Figure 26. The
recommended maximum resistor tolerance is 1%.
1.8V
10k
VDDIO
MODE
RPU
RPU
RMODE
DS90UB913Q
HOST
SCL
SCL
SDA
SDA
To other
Devices
Figure 26. MODE Pin configuration on DS90UB913Q
Table 5. DS90UB913Q Serializer MODE Resistor Value
DS90UB913Q Serializer MODE Resistor Value
Mode Select
RMODE Resistor Value
PCLK from imager mode
0kΩ
External Oscillator mode
4.7kΩ
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MODE Pin on Deserializer
The mode pin on the Deserializer can be used to configure the device to work in the 12-bit low frequency mode,
12- bit high frequency mode or the 10 bit mode of operation. Internally, the DS90UB913/914Q chipset operates
in a divide-by-1 mode in the 12- bit low frequency mode, divide-by-2 mode in the 10-bit mode and a divide-by-1.5
mode in the 12- bit high frequency mode. The pin must be pulled to VDD (1.8V, not VDDIO) with a 10 kΩ resistor
and a pull down resistor (RMODE) of the recommended value to set the different modes in the Deserializer as
mentioned in Table 6. The Deserializer automatically configures the Serializer to correct mode via the backchannel. The recommended maximum resistor tolerance is 1%
.
1.8V
10k
VDDIO
MODE
RPU
RPU
HOST
RMODE
DS90UB914Q
SCL
SCL
SDA
SDA
To Other
Devices
Figure 27. Mode Pin Configuration on DS90UB914Q Deserializer
Table 6. DS90UB914Q Deserializer MODE Resistor Value
DS90UB914Q Deserializer MODE resistor Value
MODE Select
RMODE Resistor Value
12-bit low frequency mode 10-50 MHz PCLK, 10/12 bits DATA+ 2 SYNC
0kΩ
12-bit high frequency mode 15-75 MHz PCLK, 10/12 bits DATA+ 2 SYNC
3kΩ
10-bit mode 20 MHz – 100 MHz PCLK, 10 bits DATA+ 2 SYNC
11kΩ
Line Rate Calculations for the DS90UB913/914Q
The DS90UB913Q device divides the clock internally by divide-by-1 in the 12 bit low frequency mode, by divideby-2 in the 10-bit mode and by divide-by-1.5 in the 12-bit high frequency mode. Conversely, the DS90UB914Q
multiplies the recovered serial clock to generate the proper pixel clock output frequency. Thus the maximum line
rate in the three different modes remains 1.4Gbps. The following are the formulae used to calculate the
maximum line rate in the different modes.
• For 12 bit low frequency mode, Line rate = fPCLK*28; e.g. fPCLK=50MHz, line rate = 50*28=1.4Gbps
• For 10 bit mode, Line rate = fPCLK/2*28; e.g. fPCLK=100MHz, line rate = (100/2)*28=1.4Gbps
• For the 12 bit high frequency mode, Line rate = fPCLK*(2/3)*28; e.g. fPCLK=75MHz, line rate =
(75)*(2/3)*28=1.4Gbps
Deserializer Multiplexer Input
The DS90UB914Q offers a 2:1 multiplexer that can be used to select which camera is used as the input.
Figure 28 shows the operation of the 2:1 multiplexer in the Deserializer. The selection of the camera can be pin
controlled as well as register controlled. Both the Deserializer inputs cannot be enabled at the same time. If the
Serializer A is selected as the active Serializer, the back-channel for Deserializer A turns ON and vice versa. To
switch between the two cameras, first the Serializer B has to be selected using the SEL pin/register on the
Deserializer. After that the back channel driver for Deserializer B has to be enabled using the register in the
Deserializer.
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Serializer A
DS90UB913Q
Camera A
DATA
PCLK
DATA
PCLK
2
I C
Serializer B
DS90UB913Q
Camera B
CMOS
Image
Sensor
GPIO
GPIO
FSYNC
2:1
CMOS
Image
Sensor
DS90UB914Q
FSYNC
2
I C
Deserializer A
ECU
Module
DATA
PCLK
GPIO
FSYNC
2
I C
Serializer B
PC
Figure 28. Using the multiplexer on the Deserializer to enable a two camera system
Serial Frame Format
The High Speed Forward Channel is composed of 28 bits of data containing video data, sync signals, I2C and
parity bits. This data payload is optimized for signal transmission over an AC coupled link. Data is randomized,
balanced and scrambled. The 28 bits frame structure changes in the 12 bit low frequency mode, 12 bit high
frequency mode and the 10 bit mode internally and is seamless to the customer. The bidirectional control
channel data is transferred over the single serial link along with the high-speed forward data. This architecture
provides a full duplex low speed forward and backward path across the serial link together with a high speed
forward channel without the dependence on the video blanking phase.
Error Detection
The chipset provides error detection operations for validating data integrity in long distance transmission and
reception. The data error detection function offers users flexibility and usability of performing bit-by-bit data
transmission error checking. The error detection operating modes support data validation of the following signals:
• Bidirectional control channel data across the serial link
• Parallel video/sync data across the serial link
The chipset provides 1 parity bit on the forward channel and 4 CRC bits on the back channel for error detection
purposes. The DS90UB913/914Q chipset checks the forward and back channel serial links for errors and stores
the number of detected errors in two 8-bit registers in the Serializer and the Deserializer respectively.
To check parity errors on the forward channel, monitor registers 0x1A and 0x1B on the Deserializer. If there is a
loss of LOCK, then the counters on registers 0x1A and 0x1B are reset. Whenever there is a parity error on the
forward channel, the PASS pin will go low.
To check CRC errors on the back-channel, monitor registers 0x0A and 0x0B on the Serializer.
Description of Bidirectional Control Bus and I2C Modes
The I2C compatible interface allows programming of the DS90UB913Q, DS90UB914Q, or an external remote
device (such as image sensor) through the bidirectional control channel. Register programming transactions
to/from the DS90UB913Q/914Q chipset are employed through the clock (SCL) and data (SDA) lines. These two
signals have open drain I/Os and both lines must be pulled-up to VDDIO by an external resistor. Pull-up resistors
or current sources are required on the SCL and SDA busses to pull them high when they are not being driven
low. A logic LOW is transmitted by driving the output low. Logic HIGH is transmitted by releasing the output and
allowing it to be pulled-up externally. The appropriate pull-up resistor values will depend upon the total bus
capacitance and operating speed. The DS90UB913/914Q I2C bus data rate supports up to 400 kbps according
to I2C fast mode specifications.
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DS90UB913Q, DS90UB914Q
Bus Activity:
Master
SDA Line
Register
Address
Slave
Address
7-bit Address
S
Stop
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Start
SNLS420B – JULY 2012 – REVISED APRIL 2013
Data
P
0
A
C
K
A
C
K
A
C
K
Bus Activity:
Slave
S
Register
Address
Slave
Address
7-bit Address
A
C
K
Bus Activity:
Slave
Slave
Address
S
0
N
A
C
K
7-bit Address
A
C
K
Stop
SDA Line
Start
Bus Activity:
Master
Start
Figure 29. Write Byte
P
1
A
C
K
Data
Figure 30. Read Byte
SDA
1
2
6
MSB
R/W
Direction
Bit
Acknowledge
from the Device
7-bit Slave Address
SCL
ACK
LSB
MSB
7
8
9
LSB
N/ACK
Data Byte
*Acknowledge
or Not-ACK
1
8
2
Repeated for the Lower Data Byte
and Additional Data Transfers
START
9
STOP
Figure 31. Basic Operation
SDA
SCL
S
P
STOP condition
START condition, or
START repeat condition
Figure 32. Start and Stop Conditions
Slave Clock Stretching
The I2C compatible interface allows programming of the DS90UB913Q, DS90UB914Q, or an external remote
device (such as image sensor) through the bidirectional control To communicate and synchronize with remote
devices on the I2C bus through the bidirectional control channel/MCU, the chipset utilizes bus clock
stretching (holding the SCL line low) during data transmission; where the I2C slave pulls the SCL line low
on the 9th clock of every I2C transfer (before the ACK signal). The slave device will not control the clock and
only stretches it until the remote peripheral has responded. The I2C master must support clock stretching to
operate with the DS90UB913/914Q chipset.
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I2C Pass Through
I2C pass-through provides an alternative means to independently address slave devices. The mode enables or
disables I2C bidirectional control channel communication to the remote I2C bus. This option is used to determine
whether or not an I2C instruction is to be transferred over to the remote I2C device. When enabled, the I2C bus
traffic will continue to pass through, I2C commands will be excluded to the remote I2C device. The pass through
function also provides access and communication to only specific devices on the remote bus.
See Figure 33 for an example of this function.
If master controller transmits I2C transaction for address 0xA0, the SER A with I2C pass through enabled will
transfer I2C commands to remote Camera A. The SER B with I2C pass through disabled, any I2C commands will
be bypassed on the I2C bus to Camera B.
DS90UB913Q
CMOS
Image
Sensor
DIN[11:0]
,HS,VS
PCLK
ROUT[11:0],
HS,VS,
PCLK
2
SDA
SCL
Camera A
Slave ID: (0xA0)
I C
SER A: I2C _MASTER
I2C_PASS_THRU Enabled
DS90UB913Q
CMOS
Image
Sensor
DS90UB914Q
2
I C
DES A: I2C_SLAVE
ECU
Module
DS90UB914Q
DIN[11:0]
,HS,VS
PCLK
ROUT[11:0],
HS,VS,
PCLK
2
SDA
SCL
Camera B
Slave ID: (0xA0)
SDA
SCL
I C
SER B: I2C_MASTER
I2C_PASS_THRU Disabled
2
I C
SDA
SCL
DES B: I2C_SLAVE
PC
Master
Figure 33. I2C Pass Through
ID[x] Address Decoder on the Serializer
The ID[x] pin on the Serializer is used to decode and set the physical slave address of the Serializer (I2C only) to
allow up to five devices on the bus connected to the Serializer using only a single pin. The pin sets one of the 5
possible addresses for each Serializer device. The pin must be pulled to VDD (1.8V, not VDDIO) with a 10 kΩ
resistor and a pull down resistor (RID) of the recommended value to set the physical device address. The
recommended maximum resistor tolerance is 1%.
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1.8V
10k
VDDIO
ID[x]
RPU
RPU
RID
HOST
DS90UB913Q
SCL
SCL
SDA
SDA
To other Devices
Figure 34. ID[x] Address Decoder on the Serializer
Table 7. ID[x] Resistor Value for DS90UB913Q Serializer
ID[x] Resistor Value — DS90UB913Q Serializer
Resistor RID0 Ω
(1% Tolerance)
Address 7'b
Address 8'b 0 appended (WRITE)
0k
0x58
0xB0
2k
0x59
0xB2
4.7k
0x5A
0xB4
8.2k
0x5B
0xB6
14k
0x5C
0xB8
100k
0x5D
0xBA
ID[x] Address Decoder on the Deserializer
The IDx[0] and IDx[1] pins on the Deserializer are used to decode and set the physical slave address of the
Deserializer (I2C only) to allow up to 16 devices on the bus using only two pins. The pins set one of 16 possible
addresses for each Deserializer device. As there will be more Deserializer devices connected on the same board
than Serializers, more I2C device addresses have been defined for the DS90UB914Q Deserializer than the
DSDS90UB913Q Serializer. The pins must be pulled to VDD (1.8V, not VDDIO) with a 10 kΩ resistor and two
pull down resistors (RID0 and RID1) of the recommended value to set the physical device address. The
recommended maximum resistor tolerance is 1%.
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1.8V
1.8V
10k
10k
RID1
RID0
VDDIO
IDx[0]
RPU
IDx[1]
RPU
HOST
DS90UB914Q
SCL
SCL
SDA
SDA
To other
Devices
Figure 35. ID[x[ Address Decoder on the Deserializer
Table 8. Resistor Values for IDx[0] and IDx[1] on DS90UB914Q Deserializer
ID[x] Resistor Value — DS90UB913Q Serializer
Resistor RID1 Ω
(1%Tolerance)
Resistor RID0 Ω
(1%Tolerance)
Address 7'b
Address 8'b 0 appended
(WRITE)
0k
0k
0x60
0xC0
0k
3k
0x61
0xC2
0k
11k
0x62
0xC4
0k
100k
0x63
0xC6
3k
0k
0x64
0xC8
3k
3k
0x65
0xCA
3k
11k
0x66
0XCC
3k
100k
0x67
0XCE
11k
0k
0x68
0XD0
11k
3k
0x69
0XD2
11k
11k
0x6A
0XD4
11k
100k
0x6B
0XD6
100k
0k
0x6C
0XD8
100k
3k
0x6D
0XDA
100k
11k
0x6E
0XDC
100k
100k
0x6F
0XDE
Clock-Data Recovery Status Flag (LOCK), Output Enable (OEN) and Output State Select (OSS_SEL)
When PDB is driven HIGH, the Deserializer’s CDR PLL begins locking to the serial input and LOCK is TRISTATE or LOW (depending on the value of the OEN setting). After the DS90UB914Q completes its lock
sequence to the input serial data, the LOCK output is driven HIGH, indicating valid data and clock recovered
from the serial input is available on the parallel bus and PCLK outputs. The states of the outputs are based on
the OEN and OSS_SEL setting (Table 5). See Figure 19.
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Table 9. Output States
Inputs
Outputs
Serial Inputs
PDB
OEN
OSS
LOCK
Pass
DATA, GPIO,
I2S
CLK
X
0
X
X
Z
Z
Z
Z
X
1
0
0
L or H
L
L
L
X
1
0
1
L or H
Z
Z
Z
Static
1
1
0
L
L
L
L/Osc(Register Bit
Enable)
Static
1
1
1
H
Previous State
L
L
Active
1
1
0
H
L
L
L
Active
1
1
1
H
Valid
Valid
Valid
Programmable Controller
An integrated I2C slave controller is embedded in the DS90UB913Q Serializer as well as the DS90UB914Q
Deserializer. It must be used to configure the extra features embedded within the programmable registers or it
can be used to control the set of programmable GPIOs.
Multiple Device Addressing
Some applications require multiple camera devices with the same fixed address to be accessed on the same I2C
bus. The DS90UB913/914 provides slave ID matching/aliasing to generate different target slave addresses when
connecting more than two identical devices together on the same bus. This allows the slave devices to be
independently addressed. Each device connected to the bus is addressable through a unique ID by programming
of the SLAVE_ID_MATCH register on Deserializer. This will remap the SLAVE_ID_MATCH address to the target
SLAVE_ID_INDEX address; up to 8 ID indexes are supported. The ECU Controller must keep track of the list of
I2C peripherals in order to properly address the target device.
See Figure 36 for an example of this function.
• ECU is the I2C master and has an I2C master interface
• The I2C interfaces in DES A and DES B are both slave interfaces
• The I2C protocol is bridged from DES A to SER A and from DES B to SER B
• The I2C interfaces in SER A and SER B are both master interfaces
If master controller transmits I2C slave 0xA0, the DES A address 0xC0 will forward the transaction to remote
Camera A. If the controller transmits slave address 0xA4, the DES B 0xC2 will recognize that 0xA4 is mapped to
0xA0 and will be transmitted to the remote Camera B. If controller sends command to address 0xA6, the DES B
0xC2 will forward transaction to slave device 0xA2.
The Slave ID index/match is supported only in the camera mode (SER: MODE pin = L; DES: MODE pin = H).
For Multiple device addressing in display mode (SER: MODE pin = H; DES: MODE pin = L), use the I2C pass
through function.
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Camera A
DS90UB913Q
Slave ID: (0xA0)
CMOS
Image
Sensor
ROUT[11:0],
HS, VS,
PCLK
DIN[11:0]
, HS, VS,
PCLK
2
SDA
SCL
I C
SER A: ID[x](0xB0)
PC/
EEPROM
Slave ID: (0xA2)
Camera B
DS90UB913Q
Slave ID: (0xA0)
CMOS
Image
Sensor
DS90UB914Q
DES A: ID[x](0xC0)
SLAVE_ID1_MATCH(0xA0)
SLAVE_ID1_INDEX(0xA0)
SLAVE_ID2_MATCH(0xA2)
SLAVE_ID2_INDEX(0xA2)
ECU
Module
DS90UB914Q
DIN[11:0]
, HS, VS,
PCLK
ROUT[11:0],
HS, VS,
PCLK
2
SDA
SCL
PC/
EEPROM
SDA
SCL
2
I C
I C
SER B: ID[x](0xB2)
Slave ID: (0xA2)
2
I C
SDA
SCL
DES B: ID[x](0xC2)
SLAVE_ID2_MATCH(0xA4)
SLAVE_ID2_INDEX(0xA0)
SLAVE_ID2_MATCH(0xA6)
SLAVE_ID2_INDEX(0xA2)
PC
Master
Figure 36. Multiple Device Addressing
Synchronizing Multiple Cameras
For applications requiring multiple cameras for frame-synchronization, it is recommended to utilize the General
Purpose Input/Output (GPIO) pins to transmit control signals to synchronize multiple cameras together. To
synchronize the cameras properly, the system controller needs to provide a field sync output (such as a vertical
or frame sync signal) and the cameras must be set to accept an auxiliary sync input. The vertical synchronize
signal corresponds to the start and end of a frame and the start and end of a field. Note this form of
synchronization timing relationship has a non-deterministic latency. After the control data is reconstructed from
the birectional control channel, there will be a time variation of the GPIO signals arriving at the different target
devices (between the parallel links). The maximum latency delta (t1) of the GPIO data transmitted across
multiple links is 25µs.
Note: The user must verify that the timing variations between the different links are within their system and timing
specifications.
See Figure 37 for an example of this function.
The maximum time (t1) between the rising edge of GPIO (i.e. sync signal) arriving at Camera A and Camera B is
25µs.
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DS90UB913Q
Camera A
CMOS
Image
Sensor
DS90UB914Q
DATA
PCLK
DATA
PCLK
2
I C
Serializer A
FSYNC
FSO
GPIO
GPO
FSIN
FSYNC
2
I C
Deserializer A
ECU
Module
Camera B
CMOS
Image
Sensor
DS90UB913Q
DS90UB914Q
DATA
PCLK
DATA
PCLK
2
I C
Serializer B
FSYNC
FSO
GPIO
GPO
FSIN
FSYNC
2
PC
I C
Deserializer B
Figure 37. Synchronizing Multiple Cameras
DES A
GPIO[n] Input
SER B
GPIO[n] Output
|
SER A
GPIO[n] Output
|
DES B
GPIO[n] Input
t1
Figure 38. GPIO Delta Latency
General Purpose I/O (GPIO) Descriptions
There are 4 GPOs on the Serializer and 4 GPIOs on the Deserializer when the DS90UB913/914Q chipsets are
run off the pixel clock from the imager as the reference clock source. The GPOs on the Serializer can be
configured as outputs for the input signals that are fed into the Deserializer GPIOs. In addition, the GPOs on the
Serializer can behave as outputs of the local register on the Serializer. The GPIOs on the Deserializer can be
configured to be the input signals feeding the output of the GPOs on the Serializer. In addition the GPIOs on the
Deserializer can be configured to behave as outputs of the local register on the Deserializer. If the
DS90UB913/914Q chipsets are run off the external oscillator source as the reference clock, then GPO3 on the
Serializer is automatically configured to be the input for the external clock and GPIO2 on the Deserializer is
configured to be the output of the divide-by-2 clock which is fed into the imager as its reference clock. In this
case, the GPIO2 and GPIO3 on the Deserializer can only behave as outputs of the local register on the
Deserializer. The GPIO maximum switching rate is up to 66 kHz when configured for communication between
Deserializer GPIO to Serializer GPO.
LVCMOS VDDIO Option
1.8V/2.8V/3.3V Serializer inputs and 1.8V/3.3V Deserializer outputs are user configurable to provide compatibility
with 1.8V, 2.8V and 3.3V system interfaces.
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SNLS420B – JULY 2012 – REVISED APRIL 2013
Deserializer – Adaptive Input Equalization(AEQ)
The receiver inputs provide an adaptive input equalization filter in order to compensate for loss from the media.
The level of equalization can also be manually selected via register controls. The fully adaptive equalizer output
can be seen using the CMLOUTP/CMLOUTN pins in the Deserializer.
18
EQUALIZER GAIN (dB)
16
14
12
10
8
6
4
2
0
100
200
300
400
500
600
700
SERIAL LINE FREQUENCY (MHz)
Figure 39. Maximum Equalizer Gain vs. Line Frequency
EMI Reduction
Deserializer Staggered Output
The receiver staggers output switching to provide a random distribution of transitions within a defined window.
Outputs transitions are distributed randomly. This minimizes the number of outputs switching simultaneously and
helps to reduce supply noise. In addition it spreads the noise spectrum out reducing overall EMI.
Spread Spectrum Clock Generation(SSCG) on the Deserializer
The DS90UB914Q parallel data and clock outputs have programmable SSCG ranges from 10 MHz to 100 MHz.
The modulation rate and modulation frequency variation of output spread is controlled through the SSC control
registers on the DS90UB914Q device. SSC profiles can be generated using bits [3:0] in register 0x02 in the
Deserializer.
Powerdown
The SER has a PDB input pin to ENABLE or Powerdown (SLEEP) the device. The modes can be controlled by
the host and is used to disable the Link to save power when the remote device is not operational. In this mode, if
the PDB pin is tied High and the SER will enter SLEEP when the PCLK stops. When the PCLK starts again, the
SER will then lock to the valid input PCLK and transmit the data to the DES. In SLEEP mode, the high-speed
driver outputs are static (High). The DES has a PDB input pin to ENABLE or Powerdown (SLEEP) the device.
This pin can be controlled by the system and is used to disable the DES to save power. An auto mode is also
available. In this mode, the PDB pin is tied High and the DES will enter SLEEP when the serial stream stops.
When the serial stream starts up again, the DES will lock to the input stream and assert the LOCK pin and output
valid data. In SLEEP mode, the Data and PCLK outputs are set by the OSS_SEL configuration.
Pixel Clock Edge Select (TRFB / RRFB)
The TRFB/RRFB selects which edge of the Pixel Clock is used. For the SER, this register determines the edge
that the data is latched on. If TRFB register is 1, data is latched on the Rising edge of the PCLK. If TRFB register
is 0, data is latched on the Falling edge of the PCLK. For the DES, this register determines the edge that the
data is strobed on. If RRFB register is 1, data is strobed on the Rising edge of the PCLK. If RRFB register is 0,
data is strobed on the falling edge of the PCLK.
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PCLK
DIN/
ROUT
TRFB/RRFB: 0
TRFB/RRFB: 1
Figure 40. Programmable PCLK Strobe Select
Power Up Requirements and PDB Pin
It is required to delay and release the PDB Signal after VDD (VDDn and VDDIO) power supplies have settled to
the recommended operating voltage. An external RC network can be connected to the PDB pin to ensure PDB
arrives after all the VDD has stabilized.
Built In Self Test
An optional At-Speed Built In Self Test (BIST) feature supports the testing of the high speed serial link and lowspeed back channel. This is useful in the prototype stage, equipment production, and in-system test and also for
system diagnostics.
BIST Configuration and Status
The chipset can be programmed into BIST mode using either pins or registers. By default BIST configuration is
controlled through pins. BIST can be configured via registers using BIST Control register (0x24). Pin based
configuration is defined as follows:
• BISTEN : Enable the BIST Process
• GPIO0 and GPIO1 : Defines the BIST clock source ( PCLK vs. various frequencies of internal OSC
Table 10. BIST Configuration
Deserializer GPIO[0:1]
Oscillator Source
BIST Frequency (MHz)
00
External PCLK
PCLK or External Oscillator
01
Internal
50
10
Internal
25
11
Internal
12.5
The BIST mode provides various options for source PCLK. Using external pins, GPIO0 and GPIO1 or using
registers, customer can program the BIST mode to use external PCLK or various OSC frequencies. The BIST
status can be monitored real time on PASS pin. For every frame with error(s), PASS pin toggles low for half
PCLK period. If two consecutive frames have errors, PCLK will toggle twice to allow counting of frames with
errors. Once the BIST is done, the PASS pin reflects the pass/fail status of the last BIST run. The status can also
be read through I2C for the number of frames in errors. BIST status on PASS pin remains until it is changed by a
new BIST session or a reset. The BIST status on PASS pin is not maintained till RX loses LOCK after BISTEN is
de-assserted. To evaluate BIST in the external oscillator mode, both external oscillator and PCLK need to be
present.
The BIST status on PASS pin is not maintained till RX loses LOCK after BISTEN is de-assserted. So for all
practical purposes, the BIST status can be monitored from register 0x25 i.e. BIST Error Count on the
DS90UB914 Deserializer. To evaluate BIST in the external oscillator mode, both external oscillator and PCLK
need to be present.
Sample BIST Sequence
Step1. For the DS90UB913/914Q FPD-Link III chipset, BIST Mode is enabled via the BISTEN pin of
DS90UB914Q FPD-Link III deserializer. The desired clock source is selected through the GPIO0 and GPIO1 pins
as shown in Table 6.
50
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Step2. The DS90UB913Q Serializer is woken up through the back channel if it is not already on. The SSO
pattern on the data pins is send through the FPD-Link III to the deserializer. Once the serializer and deserializer
are in the BIST mode and the deserializer acquires Lock, the PASS pin of the deserializer goes high and BIST
starts checking data stream. If an error in the payload is detected the PASS pin will switch low for one half of the
clock period. During the BIST test, the PASS output can be monitored and counted to determine the payload
error rate.
Step3. To stop the BIST mode, the deserializer BISTEN pin is set low. The deserializer stops checking the data.
The final test result is not maintained on the PASS pin. To monitor the BIST status, check the BIST Error Count
register, 0x25 on the Deserializer.
Step4. The link returns to normal operation after the deserailzer BISTEN pin is low. Figure 42 shows the
waveform diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2 shows one with multiple
errors. In most cases, it is difficult to generate errors due to the robustness of the link (differential data
transmission etc.), thus they may be introduced by greatly extending the cable length, faulting the interconnect,
or by reducing signal condition enhancements (Rx equalization).
Normal
Step 1: DES in BIST
BIST
Wait
Step 2: Wait, SER in BIST
BIST
start
Step 3: DES in Normal
Mode - check PASS
BIST
stop
Step 4: DES/SER in Normal
Figure 41. AT-Speed BIST System Flow Diagram
DES Outputs
BISTEN
(DES)
LOCK
PCLK
(RFB = L)
ROUT[0:11],
HS, VS
Case 1 - Pass
SSO
DATA
(internal)
PASS
Prior Result
PASS
PASS
X
X
Case 2 - Fail
X = bit error(s)
DATA
(internal)
X
FAIL
Prior Result
Normal
BIST Test
BIST Duration
BIST
Result
Held
Normal
Figure 42. BIST Timing Diagram
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APPLICATIONS INFORMATION
AC COUPLING
The SER/DES supports only AC-coupled interconnects through an integrated DC balanced decoding scheme.
External AC coupling capacitors must be placed in series in the FPD-Link III signal path as illustrated in
Figure 43.
DOUT+
RIN+
DOUT-
RIN-
D
R
Figure 43. AC-Coupled Connection
For high-speed FPD–Link III transmissions, the smallest available package should be used for the AC coupling
capacitor. This will help minimize degradation of signal quality due to package parasitics. The I/O’s require a 100
nF AC coupling capacitors to the line.
Adaptive Equalizer – Loss Compensation
The adaptive equalizer is designed to compensate for signal degradation due to the differential insertion loss of
the interconnect components. There are limits to the amount of loss that can be compensated – these limits are
defined by the gain curve of the equalizer. In addition, there is an inherent tolerance for loss defined by the delta
between the serializer’s minimum VOD and the input threshold (Vswing) of the deserializer. In order to determine
the maximum cable reach, other factors that affect signal integrity such as jitter, skew, ISI, crosstalk, etc. need to
be taken into consideration. Figure 44 illustrates the maximum allowable interconnect loss with the adaptive
equalizer at its maximum gain setting (“914 equalizer gain”).
25
EFFECTIVE GAIN (dB)
20
15
914 Equalizer Gain (dB)
VOD-Vswing Loss
10
Allowable Interconnect
Loss
5
0
100
200
300
400
500
600
700
SERIAL LINE FREQUENCY (MHz)
Figure 44. Adaptive Equalizer – Interconnect Loss Compensation
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SNLS420B – JULY 2012 – REVISED APRIL 2013
Figure 45 shows the typical connection of a DS90UB913Q Serializer
DS90UB913Q (SER)
VDDIO
VDDIO
C3
1.8V
VDDT
C4
C8
C9
C13
1.8V
DIN0
DIN1
DIN2
DIN3
DIN4
DIN5
DIN6
DIN7
DIN8
DIN9
DIN10
DIN11
HS
VS
PCLK
LVCMOS
Parallel
Bus
1.8V
VDDPLL
C5
C14
C10
FB1
1.8V
VDDCML
C6
C11
C15
C7
C12
FB2
1.8V
VDDD
C1
Serial
FPD-Link III
Interface
DOUT+
DOUTC2
10 k:
MODE
1.8V
RID
10 k:
LVCMOS
Control
Interface
ID[X]
RID
PDB
GPO[0]
GPO[1]
GPO[2]
GPO[3]
GPO
Control
Interface
VDDIO
RPU
I2C
Bus
Interface
RPU
SCL
FB3
SDA
FB4
C16
Optional
Optional
C17
RES
DAP (GND)
NOTE:
C1 - C2 = 0.1 PF (50 WV)
C3 ± C7 = 0.01 PF
C8 - C12 = 0.1 PF
C13 - C14 = 4.7 PF
C15 = 22 PF
C16 - C17 = >100 pF
RPU = 1 k: to 4.7 k:
RID (see ID[x] Resistor Value Table)
FB1 - FB4: Impedance = 1 k: (@ 100 MHz)
low DC resistance (<1:)
The "Optional" components shown are
provisions to provide higher system noise
immunity and will therefore result in higher
performance.
Figure 45. DS90UB913Q Typical Connection Diagram — Pin Control
Copyright © 2012–2013, Texas Instruments Incorporated
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Figure 46 shows a typical connection of the DS90UB914Q Deserializer.
DS90UB914Q (Des)
1.8V
VDDD
C3
C11
C4
C12
C5
C13
VDDIO
VDDIO1
C8
VDDR
C16
C18
VDDIO2
C9
VDDSSCG
VDDIO3
C10
1.8V
VDDPLL
FB1
C6
C14
C17
FB2
C7
C15
C19
1.8V
VDDCML
C1
RIN1+
Serial
FPD-Link II
Interface
RIN1-
C2
RIN0+
C1
RIN0-
C2
1.8V
GPIO[0]
GPIO[1]
GPIO[2]
GPIO[3]
MODE
10 k:
RMODE
ROUT0
ROUT1
ROUT2
ROUT3
ROUT4
ROUT5
ROUT6
LVCMOS
Parallel
Outputs
ROUT7
ROUT8
ROUT9
ROUT10
ROUT11
HS
VS
PCLK
LOCK
PASS
1.8V
10 k:
IDx[0]
RID0
PDB
SEL
OEN
OSS_SEL
BISTEN
1.8V
VDDIO
10 k:
IDx[1]
RPU
I2C
Bus
Interface
RPU
RID1
SCL
FB3
SDA
FB4
C20
C21
Optional
Optional
RES_PIN43
DAP (GND)
NOTE:
C1 - C2 = 0.1 PF (50 WV)
C3 - C10 = 0.01 PF
C11 - C16 = 0.1 PF
C17 - C18 = 4.7 PF
C19 = 22 PF
C20 - C21 = >100 pF
RPU = 1 k: to 4.7 k:
RID (see ID[x] Resistor Value Table)
FB1 - FB4: Impedance = 1 k: (@ 100 MHz)
low DC resistance (<1:)
The "Optional" components shown are
provisions to provide higher system noise
immunity and will therefore result in higher
performance.
Figure 46. DS90UB914Q Typical Connection Diagram — Pin Control
54
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SNLS420B – JULY 2012 – REVISED APRIL 2013
PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS
Circuit board layout and stack-up for the Ser/Des devices should be designed to provide low-noise power feed to
the device. Good layout practice will also separate high frequency or high-level inputs and outputs to minimize
unwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved by
using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane capacitance
for the PCB power system with low-inductance parasitics, which has proven especially effective at high
frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass
capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the
range of 0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF to 10 uF range. Voltage rating of the
tantalum capacitors should be at least 5X the power supply voltage being used.
Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per
supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power
entry. This is typically in the 50uF to 100uF range and will smooth low frequency switching noise. It is
recommended to connect power and ground pins directly to the power and ground planes with bypass capacitors
connected to the plane with via on both ends of the capacitor. Connecting power or ground pins to an external
bypass capacitor will increase the inductance of the path.
A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size
reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of
these external bypass capacitors, usually in the range of 20-30 MHz. To provide effective bypassing, multiple
capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At
high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing
the impedance at high frequency.
Some devices provide separate power for different portions of the circuit. This is done to isolate switching noise
effects between different sections of the circuit. Separate planes on the PCB are typically not required. Pin
Description tables typically provide guidance on which circuit blocks are connected to which power pin pairs. In
some cases, an external filter many be used to provide clean power to sensitive circuits such as PLLs.
Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the
differential lines to prevent coupling from the LVCMOS lines to the differential lines. Closely-coupled differential
lines of 100 Ohms are typically recommended for differential interconnect. The closely coupled lines help to
ensure that coupled noise will appear as common-mode and thus is rejected by the receivers. The tightly coupled
lines will also radiate less.
Information on the WQFN style package is provided in Ti's Application Note: AN-1187 (Literature Number
SN0A401).
INTERCONNECT GUIDELINES
See AN-1108 (Literature Number SNLA008) and AN-905 (Literature Number SNLA035) for full details.
• Use 100Ω coupled differential pairs
• Use the S/2S/3S rule in spacings
– – S = space between the pair
– – 2S = space between pairs
– – 3S = space to LVCMOS signal
• Minimize the number of Vias
• Use differential connectors when operating above 500Mbps line speed
• Maintain balance of the traces
• Minimize skew within the pair
Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the Texas
Instrument web site at: www.ti.com/lvds
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SNLS420B – JULY 2012 – REVISED APRIL 2013
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REVISION HISTORY
Changes from Revision A (April 2013) to Revision B
•
56
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 55
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PACKAGE OPTION ADDENDUM
www.ti.com
17-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
DS90UB913QSQ/NOPB
ACTIVE
WQFN
RTV
32
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
UB913SQ
DS90UB913QSQE/NOPB
ACTIVE
WQFN
RTV
32
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
UB913SQ
DS90UB913QSQX/NOPB
ACTIVE
WQFN
RTV
32
4500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
UB913SQ
DS90UB914QSQ/NOPB
ACTIVE
WQFN
RHS
48
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
UB914QSQ
DS90UB914QSQE/NOPB
ACTIVE
WQFN
RHS
48
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
UB914QSQ
DS90UB914QSQX/NOPB
ACTIVE
WQFN
RHS
48
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
UB914QSQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
17-Apr-2013
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
DS90UB913QSQ/NOPB
WQFN
RTV
32
DS90UB913QSQE/NOPB
WQFN
RTV
DS90UB913QSQX/NOPB
WQFN
RTV
DS90UB914QSQ/NOPB
WQFN
DS90UB914QSQE/NOPB
DS90UB914QSQX/NOPB
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
1000
178.0
12.4
5.3
5.3
1.3
8.0
12.0
Q1
32
250
178.0
12.4
5.3
5.3
1.3
8.0
12.0
Q1
32
4500
330.0
12.4
5.3
5.3
1.3
8.0
12.0
Q1
RHS
48
1000
330.0
16.4
7.3
7.3
1.3
12.0
16.0
Q1
WQFN
RHS
48
250
178.0
16.4
7.3
7.3
1.3
12.0
16.0
Q1
WQFN
RHS
48
2500
330.0
16.4
7.3
7.3
1.3
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DS90UB913QSQ/NOPB
WQFN
RTV
32
1000
213.0
191.0
55.0
DS90UB913QSQE/NOPB
WQFN
RTV
32
250
213.0
191.0
55.0
DS90UB913QSQX/NOPB
WQFN
RTV
32
4500
367.0
367.0
35.0
DS90UB914QSQ/NOPB
WQFN
RHS
48
1000
367.0
367.0
38.0
DS90UB914QSQE/NOPB
WQFN
RHS
48
250
213.0
191.0
55.0
DS90UB914QSQX/NOPB
WQFN
RHS
48
2500
367.0
367.0
38.0
Pack Materials-Page 2
MECHANICAL DATA
RHS0048A
SQA48A (Rev B)
www.ti.com
MECHANICAL DATA
RTV0032A
SQA32A (Rev B)
www.ti.com
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