October 2007 LMH0356 3Gbps HD/SD SDI Reclocker with 4:1 Input Mux and FR4 EQs General Description Features The LMH0356 3Gbps HD/SD SDI Reclocker with 4:1 Input Mux and FR4 EQs retimes serial digital video data conforming to the SMPTE 424M, SMPTE 292M, and SMPTE 259M (C) standards. The LMH0356 operates at serial data rates of 270 Mbps, 1.483 Gbps, 1.485 Gbps, 2.967 Gbps, and 2.97 Gbps. The LMH0356 supports DVB-ASI operation at 270 Mbps. The LMH0356 includes an integrated 4:1 input multiplexer for selecting one of four input data streams for retiming. In addition, the four inputs of the LMH0356 each have an FR4 equalizer capable of equalizing 0-30” of FR4 trace length. The LMH0356 automatically detects the incoming data rate and adjusts itself to retime the incoming data to suppress accumulated jitter. The LMH0356 recovers the serial data-rate clock and optionally provides it as an output. The LMH0356 has two differential serial data outputs; the second output may be selected as a low-jitter, data-rate clock output. Controls and indicators are: serial clock or second serial data output select, manual rate select input, SD/HD rate indicator output, lock detect output, auto/manual data bypass, output mute, and device enable. The serial data inputs, outputs, and serial clock outputs are differential LVPECL compatible. The CML serial data and serial clock outputs are suitable for driving 100Ω differentially terminated networks. The control logic inputs and outputs are LVCMOS compatible. The LMH0356 is powered from a single 3.3V supply. Power dissipation is typically 440 mW. The device is housed in a 48pin LLP package. ■ Supports SMPTE 424M, SMPTE 292M, and SMPTE 259M (C) serial digital video standards ■ Supports 270 Mbps, 1.483 Gbps, 1.485 Gbps, 2.967 ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Gbps, and 2.97 Gbps serial data rate operation Supports DVB-ASI at 270 Mbps Single 3.3V supply operation 440 mW typical power consumption Integrated 4:1 multiplexed input 0-30” FR4 equalizer on each multiplexed input Two differential, reclocked outputs Choice of second reclocked output or recovered clock output Single 27 MHz external crystal or reference clock input Manual rate select input SD/HD operating rate indicator output Lock Detect indicator output Output mute function for data and clock Auto/Manual reclocker bypass Device power down control (10mW typical power consumption in disabled state) Differential LVPECL compatible serial data inputs and outputs LVCMOS control inputs and indicator outputs 48-Pin LLP package Industrial temperature range: -40°C to +85°C Footprint compatible with the LMH0056 Applications ■ SDTV/HDTV and 3Gbps serial digital video interfaces for: — — — — 2.97 Gbps Signal Before FR4 Equalization (0.6 UI Jitter) 2.97 Gbps Signal After FR4 Equalization (0.23 UI JItter) 30016710 © 2007 National Semiconductor Corporation Digital video routers and switchers Digital video processing and editing equipment DVB-ASI equipment Video standards and format converters 30016711 300167 2.97 Gbps Signal After Reclocking (0.06 UI JItter) 30016712 www.national.com LMH0356 3Gbps HD/SD SDI Reclocker with 4:1 Input Mux and FR4 EQs PRELIMINARY LMH0356 Typical Application 30016701 www.national.com 2 LMH0356 Block Diagram 30016703 3 www.national.com LMH0356 Connection Diagram 30016702 The exposed die attach pad is the primary negative electrical terminal for this device. It must be connected to the negative power supply voltage. 48-Pin LLP Order Number LMH0356SQ See NS Package Number SQA48A www.national.com 4 LMH0356 Pin Descriptions Pin Name Description 1 SDI0 Data Input 0 True 2 SDI0 Data Input 0 Complement 3 VCC Positive power supply input 4 SDI1 Data Input 1 True 5 SDI1 Data Input 1 Complement 6 VCC Positive power supply input 7 SDI2 Data Input 2 True 8 SDI2 Data Input 2 Complement 9 ENABLE Device Enable 10 SDI3 Data Input 3 True 11 SDI3 Data Input 3 Complement 12 VCC Positive power supply input 13 VEE Negative power supply input 14 VCC Positive power supply input 15 BYPASS/AUTO BYPASS Bypass/Auto Bypass mode select 16 OUTPUT MUTE Data and Clock Output Mute input (active low) 17 VEE Negative power supply input 18 XTAL IN/EXT CLK Crystal or External Oscillator input 19 VEE Negative power supply input 20 VEE Negative power supply input 21 VEE Negative power supply input 22 XTAL OUT Crystal Oscillator output 23 VEE Negative power supply input 24 LOCK DETECT PLL Lock Detect output (active high) 25 VEE Negative power supply input 26 VEE Negative power supply input 27 VEE Negative power supply input 28 SCO/SDO2 Serial Clock or Serial Data Output 2 Complement 29 SCO/SDO2 Serial Clock or Serial Data Output 2 True 30 VCC Positive power supply input 31 VCC Positive power supply input 32 SDO Data Output Complement 33 SDO Data Output True 34 VCC Positive power supply input 35 VCC Positive power supply input 36 SD/HD Data Rate Range output 37 SCO_EN Serial Clock or Serial Data 2 Output select (active high enables serial clock output) 38 VEE Negative power supply input 39 VEE Negative power supply input 40 VEE Negative power supply input 41 VEE Negative power supply input 42 VEE Negative power supply input 43 LF1 Loop Filter 44 LF2 Loop Filter 45 RATE 0 Data Rate select input 46 RATE 1 Data Rate select input 47 SEL0 Data Input select input 5 www.national.com LMH0356 Pin 48 DAP www.national.com Name Description SEL1 Data Input select input VEE Connect exposed DAP to negative power supply (ground) 6 It is anticipated that this device will not be offered in a military qualified version. If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VCC–VEE) Logic Supply Voltage (Vi) 4.0V VEE−0.15V to VCC +0.15V Logic Input Current (single input): Vi = VEE−0.15V Vi = VCC+0.15V Logic Output Voltage (Vo) Logic Output Source/Sink Current Serial Data Input Voltage (VSDI) Serial Data Output Sink Current (ISDO) Package Thermal Resistance −65°C to +150°C +125°C +260°C (Pb-free) 8 kV 400V 1250V Recommended Operating Conditions Supply Voltage (VCC–VEE) Logic Input Voltage Differential Serial Input Voltage Serial Data or Clock Output Sink Current (ISO) Operating Free Air Temperature (TA) −5 mA +5 mA VEE−0.15V to VCC +0.15V ±8 mA VCC to VCC−2.0V 3.3V ±5% VEE to VCC 800 mV ±10% 16 mA max. −40°C to +85°C 24 mA θJA 48-pin LLP 26.1°C/W θJC 48-pin LLP 1.9°C/W DC Electrical Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (Notes 2, 3) Symbol Parameter Conditions VIH Input Voltage High Level VIL Input Voltage Low Level IIH Input Current High Level VIH = VCC IIL Input Current Low Level VIL = VEE Min Typ 2 VEE VOH Output Voltage High Level IOH = −2 mA VOL Output Voltage Low Level IOL = +2 mA VSDID Serial Input Voltage, Differential VCMI Input Common Mode Voltage VSDOD Serial Output Voltage, Differential 100Ω differential load VCMO Output Common Mode Voltage 100Ω differential load Power Supply Current, 3.3V supply, Total 2970 Mbps, device enabled ICC Reference Logic inputs Logic outputs SDI SDO, SCO V 0.8 V 65 µA −1 −25 µA 2 V VEE + 0.6 V 200 1600 mVP-P VCC−1.6 VCC−0.2 V 880 mVP-P 720 800 VCC− 7 Units VCC 1 VSDOD Device disabled (ENABLE = 0) Max V 133 mA 3 mA www.national.com LMH0356 Storage Temp. Range Junction Temperature Lead Temperature (Soldering 4 Sec) ESD Rating (HBM) ESD Rating (MM) ESD Rating (CDM) Absolute Maximum Ratings (Note 1) LMH0356 AC Electrical Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (Note 3) Symbol Parameter Conditions BRSD Serial Data Rate SMPTE 259M, C BRSD Serial Data Rate BRSD Reference Min SDI, SDO Typ Max Units 270 Mbps SMPTE 292M 1483, 1485 Mbps Serial Data Rate SMPTE 424M 2967, 2970 Mbps TOLJIT Serial Input Jitter Tolerance 270 Mbps, (Notes 7, 9, 11) >6 UIP-P TOLJIT Serial Input Jitter Tolerance 270 Mbps, (Notes 7, 8, 10) TOLJIT Serial Input Jitter Tolerance TOLJIT SDI >0.6 UIP-P 1483 or 1485 Mbps, (Notes 7, 8, 9) >6 UIP-P Serial Input Jitter Tolerance 1483 or 1485 Mbps, (Notes 7, 8, 10) >0.6 UIP-P TOLJIT Serial Input Jitter Tolerance 2967 or 2970 Mbps, (Notes 7, 8, 9) >6 UIP-P TOLJIT Serial Input Jitter Tolerance 2967 or 2970 Mbps, (Notes 7, 8, 10) >0.6 UIP-P tJIT Serial Data Output Jitter 270 Mbps, (Note 8) tJIT Serial Data Output Jitter tJIT BWLOOP 0.01 0.06 UIP-P 1483 or 1485 Mbps, (Note 8) 0.03 0.08 UIP-P Serial Data Output Jitter 2967 or 2970 Mbps, (Note 8) 0.09 0.15 UIP-P Loop Bandwidth 270 Mbps, <0.1dB Peaking 320 kHz 1485 Mbps, <0.1dB Peaking 1.6 MHz 2970 Mbps, <0.1dB Peaking 2.4 MHz 270 MHz 1483 MHz 1485 MHz 2967 MHz 2970 MHz FCO Serial Clock Output Frequency 270 Mbps data rate FCO Serial Clock Output Frequency 1483 Mbps data rate FCO Serial Clock Output Frequency 1485 Mbps data rate FCO Serial Clock Output Frequency 2967 Mbps data rate FCO Serial Clock Output Frequency 2970 Mbps data rate tJIT Serial Clock Output Jitter TACQ tr, tf SDO SCO SDO, SCO Serial Clock Output Duty Cycle SCO Acquisition Time Input rise/fall time www.national.com 3 psRMS 40 60 % 45 55 % 2 Serial Clock Output Alignment with respect to Data Interval Auto-Rate Detect Mode, (Notes 4, 6) 10 16 ms Fixed Rate Mode, (Notes 4, 6) 1 6 ms 1.5 3 ns 10%–90% Logic inputs 8 Parameter Conditions Reference Min Typ SDI Max Units tr, tf Input rise/fall time 20%–80%, 270 Mbps 1500 ps tr, tf Input rise/fall time 20%–80%, 1483 or 1485 Mbps 270 ps tr, tf Input rise/fall time 20%–80%, 2967 or 2970 Mbps 135 ps tr, tf Output rise/fall time 10%–90% Logic outputs 1.5 3 ns tr, tf Output rise/fall time 20%–80%, (Note 5) SDO, SCO 90 130 ps FREF Reference Clock Frequency 27 MHz FTOL Reference Clock Frequency Tolerance ±50 ppm Note 1: “Absolute Maximum Ratings” are those parameter values beyond which the life and operation of the device cannot be guaranteed. The stating herein of these maximums shall not be construed to imply that the device can or should be operated at or beyond these values. The table of “Electrical Characteristics” specifies acceptable device operating conditions. Note 2: Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are referenced to VEE (equal to zero volts). Note 3: Typical values are stated for: VCC = +3.3V, TA = +25°C. Note 4: Spec is guaranteed by design. Note 5: RL = 100Ω differential. Note 6: Measured from first SDI transition until Lock Detect (LD) output goes high (true). Note 7: Peak-to-peak amplitude with sinusoidal modulation per SMPTE RP 184-1996 paragraph 4.1. The test data signal shall be color bars. Note 8: This parameter is guaranteed by characterization over voltage and temperature limits. Note 9: Refer to “A1” in Figure 1 of SMPTE RP 184-1996. Note 10: Refer to “A2” in Figure 1 of SMPTE RP 184-1996. Note 11: Characterized to the limitations of SDI test equipment. 9 www.national.com LMH0356 Symbol LMH0356 data inputs are differential LVPECL compatible. These inputs are intended to be DC interfaced to devices such as the LMH0344 adaptive cable equalizer. These inputs have 50Ω internal terminations (100Ω differential) and may be AC-coupled if a suitable input bias voltage is provided. The LMH0356 provides four independent, equalized and multiplexed data inputs. The active input channel is selected via the SEL0 and SEL1 pins, as shown in Table 2. The equalizer on each of the four inputs is capable of equalizing up to 30” of FR4 trace without the need for programming for different trace lengths or data rates. Figure 1 shows the equivalent input circuit for SDI[3:0] and SDI[3:0]. The LMH0356 has two, retimed, differential, serial data outputs, SDO and SCO/SDO2. These outputs provide low jitter, differential, retimed data to devices such as the LMH0302 cable driver or the LMH0031 deserializer. Output SCO/SDO2 is multiplexed and can provide either a second serial data output or a serial clock output. Figure 2 shows the equivalent output circuit for SDO, SDO, SCO/SDO2, and SCO/SDO2. The SCO_EN input controls the operating mode for the SCO/ SDO2 output. When the SCO_EN input is high the SCO/ SDO2 output provides a serial clock. When SCO_EN is low, the SCO/SDO2 output provides retimed serial data. Both differential serial data outputs, SDO and SCO/SDO2, are muted when the MUTE input is a logic low level. SCO/ SDO2 also mutes when the Bypass mode is activated when this output is operating as the serial clock output. When muted, SDO and SDO (or SDO2 and SDO2) will assume opposite differential output levels. The CML serial data outputs are differential LVPECL compatible. These outputs have internal 50Ω pull-ups and are suitable for driving AC or DC-coupled, 100Ω center-tapped, AC grounded or 100Ω un-centertapped, differentially terminated networks. Device Description The LMH0356 3Gbps HD/SD SDI Reclocker with 4:1 Input Mux and FR4 EQs is used in many types of digital video signal processing equipment. Supported serial digital video standards are SMPTE 259M (C), SMPTE 292M, and SMPTE 424M. Corresponding serial data rates are 270 Mbps, 1.483 Gbps, 1.485 Gbps, 2.967 Gbps, and 2.97 Gbps. DVB-ASI data at 270 Mbps may also be retimed. The LMH0356 retimes the serial data stream to suppress accumulated jitter. It provides two low-jitter, differential, serial data outputs. The second output may be selected to output either serial data or a low-jitter serial data-rate clock. Controls and indicators are: serial clock or second serial data output select, manual rate select input, SD/HD rate output, lock detect output, auto/manual data bypass and output mute. Serial data inputs are CML and LVPECL compatible. Serial data and clock outputs are differential CML and produce LVPECL compatible levels. The output buffer design can drive AC or DC-coupled, terminated 100Ω differential loads. The differential output level is 800 mVP-P ±10% into 100Ω AC or DC-coupled differential loads. Logic inputs and outputs are LVCMOS compatible. The device package is a 48–pin LLP with an exposed die attach pad. The exposed die attach pad is electrically connected to device ground (VEE) and is the primary electrical terminal for the device. This terminal must be connected to the negative power supply or circuit ground. Serial Data Inputs, Serial Data and Clock Outputs SERIAL DATA INPUT AND OUTPUTS The differential serial data inputs, SDI0-SDI3, accept serial digital video data at the rates specified in Table 1. The serial 30016708 FIGURE 1. Equivalent SDI Input Circuit (SDI[3:0], SDI[3:0]) www.national.com 10 LMH0356 30016709 FIGURE 2. Equivalent SDO Output Circuit (SDO, SDO, SCO/SDO2, SCO/SDO2) downs which maintain a logic-low input condition unless externally driven to a logic-high condition. This input also serves to place the device in a test mode. The codes shown in Table 1 select the desired operating serial data rate. The LMH0356 then enters either the Auto-Rate Detect mode or a single operating rate. Selecting the 270 Mbps rate mode may also be used when reclocking DVB-ASI data. DVB-ASI data is MPEG2 coded data that is transmitted in 8B10B coding. The device will reclock this data without harmonic locking. OPERATING SERIAL DATA RATES This device operates at serial data rates of 270 Mbps, 1483 Mbps, 1485 Mbps, 2967 Mbps, and 2970 Mbps. The device does not lock to harmonics of these rates. The device does not lock and automatically enters the reclocker bypass mode for the following data rates: 143 Mbps, 177 Mbps, 360 Mbps, and 540 Mbps. SERIAL DATA CLOCK/SERIAL DATA 2 OUTPUT The Serial Data Clock/Serial Data 2 Output is controlled by the SCO_EN input and provides either a second retimed serial data output or a low jitter differential clock output appropriate to the serial data rate being processed. When operating as a serial clock output, the rising edge of the clock will be positioned within the corresponding serial data bit interval within 10% of the center of the data interval. Differential output SCO/SDO2 functions as the second serial data output when the SCO_EN input is a logic-low level. This output functions as the serial clock output when the SCO_EN input is a logic-high level. The SCO_EN input has an internal pull-down device and the default state of SCO_EN is low (serial data output 2 enabled). SCO/SDO2 is muted when the MUTE input is a logic low level. When the Bypass mode is activated and this output is functioning as a serial clock output, the output will also be muted. TABLE 1. Data Rate Select Input Codes RATE [1:0] Code Data Rate or Mode 00 Auto-Rate Detect mode 01 270 Mbps 10 1483/1485 Mbps, 2967/2970 Mbps Comments May be used to support DVBASI operation Control Inputs and Indicator Outputs SERIAL DATA RATE SELECTOR The Serial Data Rate Selector (RATE [1:0]) permits the user to fix the operating serial data rate. The pins have internal pull- 11 www.national.com LMH0356 MUTE The MUTE input, when low, mutes the serial data and clock outputs. It may be connected to Lock Detect or externally driven to mute or un-mute the outputs. If MUTE is connected to LD, then the data and clock outputs are muted when the PLL is not locked. This function overrides the Bypass function: see Table 3. MUTE has an internal pull-up device to enable the output by default. SERIAL DATA INPUT SELECTOR The Serial Data Input Selector (SEL [1:0]) allows the user to select the active input channel. Table 2 shows the input selected for a given state of SEL [1:0]. TABLE 2. Data Input Select Codes SEL [1:0] Code Selected Input 00 SDI0 01 SDI1 10 SDI2 11 SDI3 BYPASS/AUTO BYPASS The Bypass/Auto Bypass input, when high, forces the device to output the data without reclocking it. When this input is low, the device automatically bypasses the reclocking function when the device is in an unlocked condition or the detected data rate is a rate which the device does not support. See Table 3. BYPASS/AUTO BYPASS has an internal pull-down device. LOCK DETECT The Lock Detect (LD) output, when high, indicates that data is being received and the PLL is locked. LD may be connected to the MUTE input to mute the data and clock outputs when no data signal is being received. See Table 3. TABLE 3. Control Functionality LOCK DETECT OUTPUT MUTE BYPASS/AUTO BYPASS 0 1 0 PLL unlocked, reclocker bypassed DEVICE STATUS 1 1 0 PLL locked to supported data rate, reclocker not bypassed X 0 X Outputs muted 0 LOCK DETECT X Outputs muted 1 LOCK DETECT 0 PLL locked to supported data rate, reclocker not bypassed 1 LOCK DETECT 1 PLL locked to supported data rate, reclocker bypassed X 1 1 Outputs not muted, reclocker bypassed www.national.com 12 30016705 FIGURE 3. SDI, Lock Detect, and SD/HD 13 www.national.com LMH0356 is only valid when the PLL is locked and the Lock Detect output is high. When the PLL is not locked (the Lock Detect output is low), the SD/HD output defaults to HD (low). The SD/ HD output is undefined for a short time after lock detect assertion or de-assertion due to a data rate change on SDI. See Figure 3 for a timing diagram showing the relationship between SDI, Lock Detect, and SD/HD. SD/HD The SD/HD output indicates whether the LMH0356 is processing SD or HD / 3Gbps data rates. It may be used to control another device such as the LMH0302 cable driver. When this output is high it indicates that the data rate is 270 Mbps. When low, the indicated data rate is 1483, 1485, 2967, or 2970 Mbps. The SD/HD output is a registered function and LMH0356 SCO_EN Input SCO_EN enables the SCO/SDO2 differential output to function either as a serial clock or second serial data output. SCO/SDO2 functions as a serial clock when SCO_EN is high. This pin has an internal pull-down device. The default state (low) enables the SCO/SDO2 output as a second serial data output. and XTAL OUT pins. Alternatively, a 27 MHz LVCMOS compatible clock signal may be input to XTAL IN/EXT CLK. Parameters for a suitable crystal are given in Table 4. Frequency 27 MHz ENABLE The ENABLE pin is used to enable or disable the LMH0356. When the device is disabled, the output drivers and most of the internal circuitry are powered down. The crystal oscillator / external clock reference circuitry (XTAL IN and XTAL OUT) remain active regardless of the state of ENABLE, allowing the 27 MHz reference clock signal to be generated and passed on to additional reclockers. The ENABLE pin is active high and has an internal pull-up device to enable the LMH0356 by default. Frequency Stability ±50 ppm @ recommended drive level Operating Mode Fundamental mode, Parallel Resonant Load Capacitance 20 pF Shunt Capacitance 7 pF Series Resistance 40Ω max. Recommended Drive Level 100 µW Maximum Drive Level 500 µW Operating Temperature Range −10°C to +60°C TABLE 4. Crystal Parameters Parameter CRYSTAL OR EXTERNAL CLOCK REFERENCE The LMH0356 uses a 27 MHz crystal or external clock signal as a timing reference input. A 27 MHz parallel resonant crystal and load network may be connected to the XTAL IN/EXT CLK www.national.com 14 Value LMH0356 Application Information Figure 4 shows the application circuit for the LMH0356. 30016704 FIGURE 4. Application Circuit 15 www.national.com LMH0356 Physical Dimensions inches (millimeters) unless otherwise noted 48-Pin LLP Order Number LMH0356SQ NS Package Number SQA48A www.national.com 16 LMH0356 Notes 17 www.national.com LMH0356 3Gbps HD/SD SDI Reclocker with 4:1 Input Mux and FR4 EQs Notes THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. 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