ASAHI KASEI [AK5434D] AK5434D Dual channel 14bit 30MHz A/D Converter with differential input Features 【Power Supply】 3.0V~3.45V Single-Supply 【Operation Temperature】 −40°C~+105°C 【Package】 30pinVSOP (Pin pitch 0.65mm) Input range： Input signal bandwidth： S/H Gain： ADC： S/(N+D)： Outputs： Power consumption： 4V (Differential input @ Gain 0dB) DC ~ 400MHz (typ.) 0dB/6dB/12dB 14bit, 30MHz 69dB (typ.) (30MHz operation, input signal frequency 14.9MHz@1ch) 14bit parallel data with straight binary 172mW @typ. (power consumption @Power Down mode: under 1mW) Circuit Block Diagram AVDD AVSS S/H1 A/D Ch2 AI2N DVDD REF MUX AI2P DVSS AI1N IREF AI1P VCM VRP Ch1 D13~D0 14 S/H2 CONTROL SS PDN GAIN -1- CHSEL CLKI MS1515-E-00 2013/02 ASAHI KASEI [AK5434D] Clock Function S/H1, S/H2 Sample/Hold AMP MUX Switch that selects input signal to A/D from S/H1 and S/H2 A/D 14bit 30MSPS A/D Converter REF Reference voltage generator CONTROL Operation control circuit Pin Allocation MS1515-E-00 16 15 17 14 18 13 19 12 20 21 22 23 24 25 26 ＡＫ５４34D 30 VSOP （TOP VIEW） SS CHSEL AVSS AVDD AI1P AI1N VCM AI2N AI2P VRP CLKI GAIN IREF DVSS DVDD 11 10 9 8 7 6 5 27 4 28 3 29 2 30 1 -2- D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 PDN 2013/02 ASAHI KASEI [AK5434D] Pin Description No. Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PDN D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SS 17 18 19 20 21 22 CHSEL AVSS AVDD AI1P AI1N VCM 23 AI2N 24 AI2P 25 VRP 26 CLKI 27 GAIN 28 IREF 29 DVSS 30 DVDD (NOTE)IO MS1515-E-00 I/O @Power down I O O O O O O O O O O O O O O I − High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z − Description Power down（H: Normal Operation, L: Power down） ADC output data MSB Straight binary code ADC output data ADC output data ADC output data ADC output data ADC output data ADC output data ADC output data ADC output data ADC output data ADC output data ADC output data ADC output data ADC output data LSB Sampling timing setting L: Sampling timing is determined by applying Logic to CHSEL-pin. H: The sampling timing is the timing of CHSEL=L. Ch1 and Ch2 are sampled simultaneously. I − Ch1/Ch2 select（L:Ch1, H:Ch2） PWR − Analog Ground PWR − Analog supply（3.0V～3.45V） I − Ch1 differential input P side I − Ch1 differential input N side O High-Z Common-mode voltage output Connect 1μF between AVSS and this pin. I − Ch2 differential input N side I − Ch2 differential input P side O L ADC Reference-voltage output. Connect 1μF between AVSS and this pin. I − ADC clock input I − S/H gain setting (L:0dB, M:12dB, H:6dB) O High-Z bias current output Connect 8.2kΩ between AVSS and this pin. PWR − Digital Ground PWR − Digital Power Supply（3.0V~3.45V） I: INPUT, O: OUTPUT, PWR: POWER/GROUND -3- 2013/02 ASAHI KASEI [AK5434D] Absolute Maximum Ratings AVSS, DVSS=0V,All voltages are with respect to ground Parameter Symbol Min. Power Supplies AVDD −0.3 Analog DVDD −0.3 Digial IIN −10 Input Current Analog Input Voltage Range (Note 1) Digital Input Voltage Range (Note 2) Operating Temperature Storage Temperature Max. Unit 4.0 4.0 V V 10 mA VINA −0.3 AVDD+0.3 V VIND −0.3 DVDD+0.3 V Ta −40 105 °C Tstg −65 150 °C Note Except AVDD, AVSS, DVDD, DVSS pins (Note 1) AI1P, AI1N, AI2P, AI2N, GAIN, CLKI (Note 2) CHSEL, SS, PDN All power supply ground pins (AVSS, DVSS) should be at the same potential. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal Operating Specifications are not guaranteed at these extremes. Operating Condition Parameter Symbol Min. Typ. Max. Unit Note Supply Voltage Analog (Core) AVDD 3.0 3.3 3.45 V Digital (Core, IO) DVDD 3.0 3.3 3.45 V Power supply voltages are values where each ground pin (AVSS=DVSS) is at 0V (Voltage reference) All power supply ground pins (AVSS, DVSS) should be at the same potential. MS1515-E-00 -4- 2013/02 ASAHI KASEI [AK5434D] Electrical Characteristics Analog Specifications (AVDD=DVDD=3.3V, S/H gain=0dB, Ta=25°C, CLKI=30MHz, fin=14.9MHz, Signal Level=3.4Vpp-diff) Parameter Symbol Condition min Typ Max Units DC Characteristics Resolution RES 14 Bits Integral INL ±2.8 ±10.5 LSB Non-Linearity Differential DNL ±0.8 ±4.0 LSB Non-Linearity Offset EOC AIxP=AIxN=VCM (x=1,2) LSB ±100 Gain Error GERR Gain setting 0dB -10 0 +10 %FS Gain Gain setting 6dB 5.5 6 6.5 dB Gain setting 12dB 11.5 12 12.5 dB Input Range AINFS Gain setting 0dB 3.6 4.0 4.4 Vpp-diff Common Voltage VCM 1.26 1.4 1.54 V ADC Reference VRP 1.8 2.0 2.2 V Voltage AC Characteristics S/N SNR 68 73 dB S/(N+D) SND 64 69 dB S/(N+D) (Note 1) SND2 fin=1MHz 66 71 dB SFDR SFDR 70 dB Total Harmonic THD 64 70 dBc Distortion Input Resistance RIN (Note 4) 60 kΩ (Note 1) Input Capacitance CIN 5 8 pF (Note 1) Input Signal BW -3dB Level 400 MHz bandwidth (Note 1) CMRR CMR fin=1MHz, common swing -26dB 50 56 dB Crosstalk CTK fin=7.45MHz dB −80 −70 Current IA Analog fin=1MHz 46 68 mA Consumption ID Digital(Note 2) fin=1MHz 6 9 mA IPD 0.3 mA Current IAS Analog 0.1 mA Consumption in IDS Digital 0.1 mA power down (Note 3) (Note 1) Design Value (Note 2) CL=10pF are connected to D0~D13 pins. (Note 3) Power down PDN=Low, CLKI=Low fix, Current consumption without no input signal. (Note 4) Equivalent resistance that from VCM operation middle point to differential input pins AI1P/N, AI2P/N. It is in inverse proportion to sampling frequency. MS1515-E-00 -5- 2013/02 ASAHI KASEI [AK5434D] Switching Characteristics Parameter Conversion rate Clock cycle Clock rise time Note 1 Clock fall time Note 1 Clock High width Clock Low width Clock duty Pipeline delay Note 2 Aperture delay Note 2 AD output delay CHSEL setup CHSEL hold Start up time 1 Start up time 2 (AVDD=DVDD=3.0~3.45V, Ta=−40~105°C, CL=10pF) Conditions min. typ. max. Unit 15 30 MHz 33.3 66.7 ns 0.3AVDD 2 15 ns to 0.7AVDD 0.7AVDD 2 15 ns to 0.3AVDD 15 ns 15 ns 40 50 60 % 8 CLKI Symbol fs tcy tr tf tH tL tduty tpd tap tdl tset thold tst1 tst2 0 10 10 2 4 ns 6 20 2 2 5 5 ns ns ns ms ms Note 1) Clock high width and Low width must be fulfilled. Note 2) Design Value tap AI2P/N N+8 N+1 AI1P/N N 0.7AVDD CLKI 0.3AVDD tH tf tr tL tdl tcy 0.8DVDD D13~D0 N-8 N 0.2DVDD tset CHSEL MS1515-E-00 thold 0.7DVDD 0.3DVDD -6- 2013/02 ASAHI KASEI PDN [AK5434D] 0.7AVDD tst1 CLKI 0.7AVDD tst2 D13~D0 Digital DC Characteristics (AVDD=DVDD=3.0~3.6V, Ta=－40~105°C) Parameter Symbol High level input threshold 1 VIH1 Low level input threshold 1 VIL1 High level input threshold 2 VIH2 Low level input threshold 2 VIL2 High level input threshold 3 VIH3 Middle level input threshold 3 VIM3 Low level input threshold 3 VIL3 High level output voltage VOH Low level output voltage VOL Input leakage current ILKG High-Z leakage current Note 1) CHSEL, SS, PDN, Note 2) CLKI Note 3) D13~D0 IOZ Pin Note 1 Note 1 Note 2 Note 2 GAIN GAIN GAIN Note 3, Note 4 Note 3, Note 5 Note 1, Note2, GAIN Note 3 Min. 0.7×DVDD Max. 0.2×DVDD ±10 Unit V V V V V V V V V μA ±10 μA 0.3×DVDD 0.7×AVDD 0.3×AVDD 0.8×AVDD 0.3×AVDD 0.7×AVDD 0.2×AVDD 0.8×DVDD Remark Note 4) IOH = −1mA Note 5) IOL = 1mA MS1515-E-00 -7- 2013/02 ASAHI KASEI [AK5434D] Functional Description Power down function Power Down mode can be activated by applying a logic Level “0” to the PDN-pin. All the data output pins [D13: D0] become Low state.at Power Down mode. PDN Condition L Power down H Normal opration S/H AMP gain select The gain of the S/H amplifier can be selected by the input level of GAIN-pin. GAIN Gain Input full scale AVSS 0dB 4Vpp-diff AVDD 6dB 2Vpp-diff VCM 12dB 1Vpp-diff Sampling timing setting The sampling timing of two channels can be set with SS-pin. SS Sampling timing L S/H1 or S/H2 samples the signal according to CHSEL. H At CHSEL=L, S/H1 and S/H2 sample the signal at the same time. Sampling channel select The samples timing can be selected with CHSEL-pin. Separate sampling (@SS=Low) CHSEL Sampling channel L S/H1 H S/H2 Simultaneous sampling (@SS=High) CHSEL Sampling channel L S/H1 & S/H2 H Not sampled Only at CHSEL=Low, sampling is done at the same timing (SS=High). MS1515-E-00 -8- 2013/02 ASAHI KASEI [AK5434D] Operation timing At SS=”L” CLKI CHSEL S/H1 S Hold S S Hold S/H2 A/D sampling channel 2 1 2 1 2 S 1 S Hold S Hold Hold S Hold S 1 2 1 2 1 2 CH1 CH2 CH1 CH2 CH1 CH2 Pipeline delay（ 8CLKI） D13~D0 At SS=”H” CLKI CHSEL S/H1 S Hold S S Hold S Hold S Hold S/H2 S Hold S S Hold S Hold S Hold Sampling timing A/D sampling channel 2 1 2 1 2 1 1 2 1 2 1 2 1 CH1 CH2 CH1 CH2 CH1 CH2 CH1 Pipeline delay（ 9CLKI） Pipeline delay（ 8CLKI） D13~D0 MS1515-E-00 -9- 2013/02 ASAHI KASEI [AK5434D] External Circuit Examples 0.1μF, 10μF 8.2kΩ±1% IREF AVDD AVSS AVSS 1μF±10% AVSS VCM AVSS 0.1μF, 10μF 1μF±10% DVDD VRP DVSS AVSS DVSS AIN1P AIN2P 0.1μF 1kΩ±5% VCM 1kΩ±5% AIN1N AIN2N 0.1μF Note) Resisters must be metal-film type. MS1515-E-00 -10- 2013/02 ASAHI KASEI [AK5434D] Packages 30-VSOP-0.65 MS1515-E-00 -11- 2013/02 ASAHI KASEI [AK5434D] Marking Marketing Code: AK5434D Date Code: XXXXXXX AK5434D XXXXXXX MS1515-E-00 -12- 2013/02 ASAHI KASEI [AK5434D] IMPORTANT NOTICE z These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei Microdevices Corporation (AKM) or authorized distributors as to current status of the products. z Descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application examples of the semiconductor products. You are fully responsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. z Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKM. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS1515-E-00 -13- 2013/02