A3977 Microstepping DMOS Driver with Translator Features and Benefits Description ▪ ±2.5 A, 35 V output rating ▪ Low rDS(on) outputs, 0.45 Ω source, 0.36 Ω sink typical ▪ Automatic current decay mode detection/selection ▪ 3.0 to 5.5 V logic supply voltage range ▪ Mixed, fast, and slow current decay modes ▪ Home output ▪ Synchronous rectification for low power dissipation ▪ Internal UVLO and thermal shutdown circuitry ▪ Crossover-current protection The A3977 is a complete microstepping motor driver, with builtin translator. It is designed to operate bipolar stepper motors in full-, half-, quarter-, and eighth-step modes, with output drive capability of 35 V and ±2.5 A. The A3977 includes a fixed off-time current regulator that has the ability to operate in slow-, fast-, or mixed-decay modes. This current-decay control scheme results in reduced audible motor noise, increased step accuracy, and reduced power dissipation. The translator is the key to the easy implementation of the A3977. Simply inputting one pulse on the STEP input drives the motor one step (two logic inputs determine if it is a full-, half-, quarter-, or eighth-step). There are no phase-sequence tables, high-frequency control lines, or complex interfaces to program. The A3977 interface is an ideal fit for applications where a complex microprocessor is unavailable or over-burdened. Packages: Package ED, 44-pin PLCC with internally fused pins Internal synchronous-rectification control circuitry is provided to improve power dissipation during PWM operation. Internal circuit protection includes thermal shutdown with hysteresis, undervoltage lockout (UVLO) and crossover-current protection. Special power-up sequencing is not required. Package LP, 28-pin TSSOP with exposed thermal pad The A3977 is supplied in a choice of two power packages, a 44-pin plastic PLCC with 3 internally-fused pins on each of four sides (suffix ED), and a thin (<1.2 mm), 28-pin TSSOP with an exposed thermal pad (suffix LP). Both packages are lead (Pb) free, with 100% matte tin leadframe plating. Not to scale 1 44 43 OUT 1B 2 SLEEP GND GND 3 ENABLE GND 4 LOAD SUPPLY 1 HOME 5 SENSE 1 6 DIR OUT 1A Pin-out Diagram 42 41 40 VBB1 7 NC 8 PFD 9 39 NC CHARGE PUMP NC PWM TIMER TRANSLATOR & CONTROL LOGIC RC1 10 GND 11 GND 12 GND 13 REF 14 37 CP1 36 VCP 35 GND 34 GND 33 GND REG ÷8 32 RC2 15 LOGIC SUPPLY 16 38 CP2 VREG 31 STEP 30 NC VDD NC 17 29 NC 21 22 23 24 25 MS 2 MS1 SENSE 2 GND GND GND SUPPLY LOAD 2 26 27 28 OUT 2B 20 RESET 19 SR 18 OUT 2A VBB2 Dwg. PP-075-1 26184.22K A3977 Microstepping DMOS Driver with Translator Selection Guide Part Number Packing Package Ambient Temperature, TA (°C) A3977KEDTR-T* 450 per reel 44-pin PLCC –40 to 125 A3977SEDTR-T* 450 per reel 44-pin PLCC –20 to 85 A3977SLPTR-T 4000 per reel 28-pin TSSOP –20 to 85 *Variant is in production but has been determined to be LAST TIME BUY. This classification indicates that the variant is obsolete and notice has been given. Sale of the variant is currently restricted to existing customer applications. The variant should not be purchased for new design applications because of obsolescence in the near future. Samples are no longer available. Status date change April 23, 2013. Deadline for receipt of LAST TIME BUY orders is September 30, 2013. Absolute Maximum Ratings Characteristic Symbol Load Supply Voltage VBB Logic Supply Voltage VDD Logic Input Voltage Range Reference Voltage Sense Voltage (DC) Output Current VIN Notes Rating Units 35 V 7.0 V Pulsed, tw > 30 ns –0.3 to VDD+ 0.3 V Pulsed, tw < 30 ns –1.0 to VDD+ 1 V VREF VDD V VSENSE 0.5 V ±2.5 A Range K –40 to 125 ºC Range S IOUT Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a junction temperature of 150°C. Operating Ambient Temperature TA –20 to 85 ºC Maximum Junction Temperature TJ(max) 150 ºC Tstg –55 to 150 ºC Storage Temperature Thermal Characteristics Characteristic Package Thermal Resistance Symbol RθJA Test Conditions* Value Units Package ED, on 4-layer PCB based on JEDEC standard 22 ºC/W Package LP, on 4-layer PCB based on JEDEC standard 28 ºC/W *Additional thermal information available on the Allegro website. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 A3977 Microstepping DMOS Driver with Translator FUNCTIONAL BLOCK DIAGRAM VREG LOGIC SUPPLY 2V UVLO AND FAULT VDD REF. SUPPLY CP2 CP1 CHARGE PUMP REGULATOR BANDGAP REF DAC SENSE1 LOAD SUPPLY VCP VBB1 VCP DMOS H BRIDGE + OUT 1A RC1 PWM LATCH BLANKING OUT1B MIXED DECAY PWM TIMER 4 STEP MS 2 HOME SLEEP VPFD GATE DRIVE MS 1 CONTROL LOGIC RESET SENSE1 TRANSLATOR DIR VBB2 OUT 2A SR OUT2B ENABLE PFD DMOS H BRIDGE PWM TIMER PWM LATCH BLANKING MIXED DECAY 4 RC 2 + DAC - SENSE2 Dwg. FP-050-2 Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 A3977 Microstepping DMOS Driver with Translator LP Pin-out (TSSOP) Table 1. Microstep Resolution Truth Table MS1 L H L H MS2 L L H H Resolution Full step (2 phase) Half step Quarter step Eighth step Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4 A3977 Microstepping DMOS Driver with Translator ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 35 V, VDD = 3.0 V to 5.5V (unless otherwise noted) Characteristic Symbol Test Conditions Min. Typ. Max. Units Output Drivers Load Supply Voltage Range VBB Output Leakage Current IDSS Output On Resistance Body Diode Forward Voltage Motor Supply Current rDS(on) VF IBB Operating 8.0 – 35 V During sleep mode 0 – 35 V VOUT = VBB – <1.0 20 μA VOUT = 0 V – <1.0 -20 μA Source driver, IOUT = -2.5 A – 0.45 0.57 Ω Sink driver, IOUT = 2.5 A – 0.36 0.43 Ω Source diode, IF = -2.5 A – – 1.4 V Sink diode, IF = 2.5 A – – 1.4 V fPWM < 50 kHz – – 8.0 mA Operating, outputs disabled – – 6.0 mA Sleep mode – – 20 μA 3.0 5.0 5.5 V Control Logic Logic Supply Voltage Range Logic Input Voltage Logic Input Current Maximum STEP Frequency HOME Output Voltage Blank Time Fixed Off Time Mixed Decay Trip Point VDD Operating VIN(1) 0.7VDD – – V VIN(0) – – 0.3VDD V IIN(1) VIN = 0.7VDD -20 <1.0 20 μA IIN(0) VIN = 0.3VDD -20 <1.0 20 μA 500* – – kHz VOH IOH = -200 μA 0.7VDD – – V VOL IOL = 200 μA – – 0.3VDD V fSTEP tBLANK Rt = 56 kΩ, Ct = 680 pF 700 950 1200 ns toff Rt = 56 kΩ, Ct = 680 pF 30 38 46 μs PFDH – V – – V 0 0.6VDD 0.21VDD – – PFDL VDD V – 0 ±3.0 μA Ref. Input Voltage Range VREF Reference Input Current IREF Gain (Gm) Error (note 3) EG Crossover Dead Time tDT Operating VREF = 2 V, Phase Current = 38.27% – – ±10 % VREF = 2 V, Phase Current = 70.71% – – ±5.0 % – – ±5.0 % 100 475 800 ns VREF = 2 V, Phase Current = 100.00% SR enabled Continued on the next page… Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 A3977 Microstepping DMOS Driver with Translator ELECTRICAL CHARACTERISTICS (continued) at TA = +25°C, VBB = 35 V, VDD = 3.0 V to 5.5V (unless otherwise noted) Characteristic Symbol Test Conditions Min. Typ. Max. Units – 165 – °C Output Drivers (continued) Thermal Shutdown Temp. Thermal Shutdown Hysteresis UVLO Enable Threshold UVLO Hysteresis Logic Supply Current TJ ∆TJ VUVLO – 15 – °C 2.45 2.7 2.95 V 0.05 0.10 – V fPWM < 50 kHz Outputs off – – 12 mA – – 10 mA Sleep mode – – 20 μA Increasing VDD ∆VUVLO IDD * Operation at a step frequency greater than the specified minimum value is possible but not warranteed. NOTES: 1. Typical Data is for design information only. 2. Negative current is defined as coming out of (sourcing) the specified device terminal. 3. EG = ([VREF/8] – VSENSE)/(VREF/8) Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6 A3977 Microstepping DMOS Driver with Translator Functional Description Device Operation. The A3977 is a complete microstepping motor driver with built in translator for easy operation with minimal control lines. It is designed to operate bipolar stepper motors in full-, half-, quarter- and eighth-step modes. The current in each of the two output full-bridges, all N-channel DMOS, is regulated with fixed off-time pulse-width modulated (PWM) control circuitry. The fullbridge current at each step is set by the value of an external current sense resistor (RS), a reference voltage (VREF), and the DACs output voltage controlled by the output of the translator. At power up, or reset, the translator sets the DACs and phase current polarity to initial home state (see figures for home-state conditions), and sets the current regulator for both phases to mixed-decay mode. When a step command signal occurs on the STEP input the translator automatically sequences the DACs to the next level (see table 2 for the current level sequence and current polarity). The microstep resolution is set by inputs MS1 and MS2 as shown in table 1. If the new DAC output level is lower than the previous level the decay mode for that full-bridge will be set by the PFD input (fast, slow, or mixed decay). If the new DAC level is higher or equal to the previous level then the decay mode for that full-bridge will be slow decay. This automatic current-decay selection will improve microstepping performance by reducing the distortion of the current waveform due to the motor BEMF. Reset Input (RESET). The RESET input (active low) sets the translator to a predefined home state (see figures for home state conditions) and turns off all of the DMOS outputs. The HOME output goes low and all STEP inputs are ignored until the RESET input goes high. Home Output (HOME). The HOME output is a logic output indicator of the initial state of the translator. At power up the translator is reset to the home state (see figures for home state conditions). Step Input (STEP). A low-to-high transition on the STEP input sequences the translator and advances the motor one increment. The translator controls the input to the DACs and the direction of current flow in each winding. The size of the increment is determined by the state of inputs MS1 and MS2 (see table 1). Microstep Select (MS1 and MS2). Input terminals MS1 and MS2 select the microstepping format per table 1. Changes to these inputs do not take effect until the STEP command (see figure). Direction Input (DIR). The state of the DIRECTION input will determine the direction of rotation of the motor. Internal PWM Current Control. Each full-bridge is controlled by a fixed off-time PWM current-control circuit that limits the load current to a desired value (ITRIP). Initially, a diagonal pair of source and sink DMOS outputs are enabled and current flows through the motor winding and RS. When the voltage across the current-sense resistor equals the DAC output voltage, the current-sense comparator resets the PWM latch, which turns off the source driver (slow-decay mode) or the sink and source drivers (fast- or mixed-decay modes). The maximum value of current limiting is set by the selection of RS and the voltage at the VREF input with a transconductance function approximated by: ITRIPmax = VREF/8RS The DAC output reduces the VREF output to the current-sense comparator in precise steps (see table 2 for % ITRIPmax at each step). ITRIP = (% ITRIPmax/100) x ITRIPmax It is critical to ensure that the maximum rating (0.5 V) on the SENSE terminal is not exceeded. For full-step mode, VREF can be applied up to the maximum rating of VDD, because the peak sense value is 0.707 x VREF/8. In all other modes VREF should not exceed 4 V. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 7 A3977 Microstepping DMOS Driver with Translator Functional Description (cont’d) Fixed Off-Time. The internal PWM current-control circuitry uses a one shot to control the time the drivers remain off. The one shot off-time, toff, is determined by the selection of an external resistor (RT) and capacitor (CT) connected from the RC timing terminal to ground. The offtime, over a range of values of CT = 470 pF to 1500 pF and RT = 12 kΩ to 100 kΩ is approximated by: toff = RTCT RC Blanking. In addition to the fixed off-time of the PWM control circuit, the CT component sets the comparator blanking time. This function blanks the output of the current-sense comparator when the outputs are switched by the internal current-control circuitry. The comparator output is blanked to prevent false over-current detection due to reverse recovery currents of the clamp diodes, and/or switching transients related to the capacitance of the load. The blank time tBLANK can be approximated by: tBLANK = 1400CT Charge Pump. (CP1 and CP2). The charge pump is used to generate a gate supply greater than VBB to drive the source-side DMOS gates. A 0.22 μF ceramic capacitor should be connected between CP1 and CP2 for pumping purposes. A 0.22 μF ceramic capacitor is required between VCP and VBB to act as a reservoir to operate the high-side DMOS devices. VREG. This internally generated voltage is used to operate the sink-side DMOS outputs. The VREG terminal should be decoupled with a 0.22 μF capacitor to ground. VREG is internally monitored and in the case of a fault condition, the outputs of the device are disabled. Enable Input (ENABLE). This active-low input enables all of the DMOS outputs. When logic high the outputs are disabled. Inputs to the translator (STEP, DIRECTION, MS1, MS2) are all active independent of the ENABLE input state. Shutdown. In the event of a fault (excessive junction temperature, or low voltage on VCP) the outputs of the device are disabled until the fault condition is removed. At power up, and in the event of low VDD, the undervoltage lockout (UVLO) circuit disables the drivers and resets the translator to the HOME state. Sleep Mode (SLEEP). An active-low control input used to minimize power consumption when not in use. This disables much of the internal circuitry including the output DMOS, regulator, and charge pump. A logic high allows normal operation and startup of the device in the home position. When coming out of sleep mode, wait 1 ms before issuing a STEP command to allow the charge pump (gate drive) to stabilize. Percent Fast Decay Input (PFD). When a STEP input signal commands a lower output current from the previous step, it switches the output current decay to either slow-, fast-, or mixed-decay depending on the voltage level at the PFD input. If the voltage at the PFD input is greater than 0.6 VDD then slow-decay mode is selected. If the voltage on the PFD input is less than 0.21 VDD then fast-decay mode is selected. Mixed decay is between these two levels. This terminal should be decoupled with a 0.1 μF capacitor. Mixed Decay Operation. If the voltage on the PFD input is between 0.6VDD and 0.21VDD, the bridge will operate in mixed-decay mode depending on the step sequence (see figures). As the trip point is reached, the device will go into fast-decay mode until the voltage on the RC terminal decays to the voltage applied to the PFD terminal. The time that the device operates in fast decay is approximated by: tFD = RTCTIn (0.6VDD/VPFD) After this fast decay portion, tFD, the device will switch to slow-decay mode for the remainder of the fixed off-time period. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 8 A3977 Microstepping DMOS Driver with Translator Functional Description (cont’d) Synchronous Rectification. When a PWM off-cycle is triggered by an internal fixed off-time cycle, load current will recirculate according to the decay mode selected by the control logic. The A3977 synchronous rectification feature will turn on the appropriate MOSFETs during the current decay and effectively short out the body diodes with the low rDS(on) driver. This will reduce power dissipation significantly and eliminate the need for external Schottky diodes for most applications. The synchronous rectification can be set in either active mode or disabled mode. Active Mode. When the SR input is logic low, active mode is enabled and synchronous rectification will occur. This mode prevents reversal of the load current by turning off synchronous rectification when a zero current level is detected. This prevents the motor winding from conducting in the reverse direction. Disabled Mode. When the SR input is logic high, synchronous rectification is disabled. This mode is typically used when external diodes are required to transfer power dissipation from the A3977 package to the external diodes. Timing Requirements (TA = +25°C, VDD = 5 V, Logic Levels are VDD and Ground) A. Minimum Command Active Time Before Step Pulse (Data Set-Up Time) ..... 200 ns B. Minimum Command Active Time After Step Pulse (Data Hold Time) ........... 200 ns C. Minimum STEP Pulse Width ...................... 1.0 μs D. Minimum STEP Low Time ......................... 1.0 μs E. Maximum Wake-Up Time ......................... 1.0 ms Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 9 A3977 Microstepping DMOS Driver with Translator Applications Information Layout. The printed wiring board should use a heavy ground plane. For optimum electrical and thermal performance, the driver should be soldered directly onto the board. The load supply terminal, VBB, should be decoupled with an electrolytic capacitor (>47 μF is recommended) placed as close to the device as possible. To avoid problems due to capacitive coupling of the high dv/dt switching transients, route the bridge-output traces away from the sensitive logic-input traces. Always drive the logic inputs with a low source impedance to increase noise immunity. Grounding. A star ground system located close to the driver is recommended. The 44-lead PLCC has the analog ground and the power ground internally bonded to the power tabs of the package (leads 44, 1, 2, 11 – 13, 22 – 24, and 33 – 35). On the 28-lead TSSOP package, the analog ground (lead 7) and the power ground (lead 21) must be con- nected together externally. The copper ground plane located under the exposed thermal pad is typically used as the star ground. Current Sensing. To minimize inaccuracies caused by ground-trace IR drops in sensing the output current level, the current-sense resistor (RS) should have an independent ground return to the star ground of the device. This path should be as short as possible. For low-value sense resistors the IR drops in the printed wiring board sense resistor’s traces can be significant and should be taken into account. The use of sockets should be avoided as they can introduce variation in RS due to their contact resistance. Allegro MicroSystems recommends a value of RS given by RS = 0.5/ITRIPmax Thermal Protection. Circuitry turns off all drivers when the junction temperature reaches 165°C, typically. It is intended only to protect the device from failures due to excessive junction temperatures and should not imply that output short circuits are permitted. Thermal shutdown has a hysteresis of approximately 15°C. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 10 A3977 Microstepping DMOS Driver with Translator Table 2. Step Sequencing (DIR = L) Full Step # Half Step # Quarter Step # Eighth Step # Phase 2 Current [%Itripmax] Phase 1 Current [%Itripmax] Step Angle 1 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 0.00 19.51 38.27 55.56 70.71 83.15 92.39 98.08 100.00 98.08 92.39 83.15 70.71 55.56 38.27 19.51 0.00 -19.51 -38.27 -55.56 -70.71 -83.15 -92.39 -98.08 -100.00 -98.08 -92.39 -83.15 -70.71 -55.56 -38.27 -19.51 100.00 98.08 92.39 83.15 70.71 55.56 38.27 19.51 0.00 -19.51 -38.27 -55.56 -70.71 -83.15 -92.39 -98.08 -100.00 -98.08 -92.39 -83.15 -70.71 -55.56 -38.27 -19.51 0.00 19.51 38.27 55.56 70.71 83.15 92.39 98.08 0 11.25 22.50 33.75 45* 56.25 67.50 78.75 90 101.25 112.50 123.75 135 146.25 157.50 168.75 180 191.25 202.50 213.75 225 236.25 247.50 258.75 270 281.25 292.50 303.75 315 326.25 337.50 348.75 2 1 2 3 4 3 5 6 2 4 7 8 5 9 10 3 6 11 12 7 13 14 4 8 15 16 * Home state; HOME output low. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 11 A3977 Microstepping DMOS Driver with Translator Full-Step Operation MS1 = MS2 = L, DIR = H The vector addition of the output currents at any step is 100%. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 12 A3977 Microstepping DMOS Driver with Translator Half-Step Operation MS1 = H, MS2 = L, DIR = H The mixed-decay mode is controlled by the percent fast decay voltage (VPFD). If the voltage at the PFD input is greater than 0.6VDD then slow-decay mode is selected. If the voltage on the PFD input is less than 0.21VDD then fast-decay mode is selected. Mixed decay is between these two levels. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 13 A3977 Microstepping DMOS Driver with Translator Quarter-Step Operation MS1 = L, MS2 = H, DIR = H The mixed-decay mode is controlled by the percent fast decay voltage (VPFD). If the voltage at the PFD input is greater than 0.6VDD then slow-decay mode is selected. If the voltage on the PFD input is less than 0.21VDD then fast-decay mode is selected. Mixed decay is between these two levels. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 14 A3977 Microstepping DMOS Driver with Translator 8 Microstep/Step Operation MS1 = MS2 = H, DIR = H The mixed-decay mode is controlled by the percent fast decay voltage (VPFD). If the voltage at the PFD input is greater than 0.6VDD then slow-decay mode is selected. If the voltage on the PFD input is less than 0.21VDD then fast-decay mode is selected. Mixed decay is between these two levels. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 15 A3977 Microstepping DMOS Driver with Translator Terminal List Terminal Name GND SENSE1 HOME DIR OUT1A NC PFD RC1 GND AGND REF RC2 LOGIC SUPPLY NC OUT2A MS2 MS1 SENSE2 GND LOAD SUPPLY2 SR RESET OUT2B NC STEP VREG PGND GND VCP CP1 CP2 NC OUT1B ENABLE SLEEP LOAD SUPPLY1 Terminal Description Analog and power ground Sense resistor for bridge 1 Logic output Logic Input DMOS H bridge 1 output A No (internal) connection Mixed decay setting Analog Input for fixed offtime – bridge 1 Analog and power ground Analog ground Gm reference input Analog input for fixed offtime – bridge 2 VDD, the logic supply voltage No (internal) connection DMOS H bridge 2 output A Logic input Logic input Sense resistor for bridge 2 Analog and power ground VBB2, the load supply for bridge 2 Logic input Logic input DMOS H bridge 2 output B No (internal) connection Logic input Regulator decoupling Power ground Analog and power ground Reservoir capacitor Charge pump capacitor Charge pump capacitor No (internal) connection DMOS H bridge 1 output B Logic input Logic input VBB1, the load supply for bridge 1 LP (TSSOP) – 1 2 3 4 – 5 6 – 7* 8 9 10 – 11 12 13 14 – 15 16 17 18 – 19 20 21* – 22 23 24 – 25 26 27 28 ED (PLCC) 44, 1, 2 3 4 5 6 7, 8 9 10 11, 12, 13 – 14 15 16 17 18 19 20 21 22, 23, 24 25 26 27 28 29, 30 31 32 – 33, 34, 35 36 37 38 39 40 41 42 43 * AGND and PGND on the TSSOP package must be connected together externally. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 16 A3977 Microstepping DMOS Driver with Translator ED Package, 44-pin PLCC 17.53 ±0.13 16.59 ±0.08 0.51 2 1 44 7.75 ±0.36 A 17.53 ±0.13 16.59 ±0.08 7.75 ±0.36 0.74 ±0.08 4.57 MAX 44X SEATING PLANE 0.10 C 0.43 ±0.10 C 1.27 7.75 ±0.36 7.75 ±0.36 For Reference Only (reference JEDEC MS-018 AC) Dimensions in millimeters Internally fused pins 44, 1 and 2; 11-13; 22-24; and 33-35 Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 17 A3977 Microstepping DMOS Driver with Translator LP Package, 28-pin TSSOP 0.45 9.70 ±0.10 28 +0.05 0.15 –0.06 0.65 28 4° ±4 1.65 B 3.00 4.40 ±0.10 6.40 ±0.20 3.00 6.10 0.60 ±0.15 A 1 (1.00) 2 5.00 0.25 28X SEATING PLANE 0.10 C +0.05 0.25 –0.06 0.65 C SEATING PLANE GAUGE PLANE 1 2 5.00 C PCB Layout Reference View 1.20 MAX 0.10 MAX For reference only (reference JEDEC MO-153 AET) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area B Exposed thermal pad (bottom surface) C Reference land pattern layout (reference IPC7351 SOP65P640X120-29CM); All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 18 A3977 Microstepping DMOS Driver with Translator Revision History Revision Revision Date Rev. K April 23, 2013 Description of Revision Update product selection and applications component recommendations Copyright ©2002-2013, Allegro MicroSystems, LLC Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 19