APW8723 5V to 12V Single Buck Voltage Mode PWM Controller Features General Description • Wide 5V to 12V Supply Voltage The APW8723 is a voltage mode, fixed 300kHz switching • Power-On-Reset Monitoring on VCC • Excellent Output Voltage Regulations frequency, synchronous buck converter. The APW8723 allows wide input voltage that is either a single 5V~12V or two supply voltage(s) for various applications. The power-on-reset (POR) circuit monitors the VCC supply - 0.8V Internal Reference - ±1% Over Temperature Range • Integrated Soft-Start • Voltage Mode PWM Operation with External voltage to prevent wrong logic controls. A built-in soft-start circuit prevents the output voltages from overshoot as well as limits the input current. An internal 0.8V temperature-compensated reference voltage with high accuracy Compensation • Up to 90% Duty Ratio for Fast Transient Response • Constant Switching Frequency is designed to meet the requirement of low output voltage applications. The APW8723 provides excellent out- - 300kHz ±10% • Integrated Bootstrap Forward P-CH MOSFET put voltage regulations against load current variation. APW8723 is built in reference voltage offset function for • Drive Dual Low Cost N-MOSFETs with Adaptive applications that require adjusting supply voltage. Dead Time Control The controller’s over-current protection monitors the output current by using the voltage drop across the RDS(ON) of • 50% Under-Voltage Protection • 125% Over-Voltage Protection • Adjustable Over-Current Protection Threshold low-side MOSFET, eliminating the need for a current sensing resistor that features high efficiency and low cost. In addition, the APW8723 also integrates excellent protec- - Using the RDS(ON) of Low-Side MOSFET • Shutdown Control by COMP • Power Good Monitoring • TDFN3x3-10 Package • Lead Free and Green Devices Available tion functions, The over-voltage protection (OVP) , undervoltage protection (UVP) and over-temperature protection (OTP). OVP circuit which monitors the FB voltage to prevent the PWM output from over voltage, and UVP circuit which monitors the FB voltage to prevent the PWM output from under voltage or short circuit. OTP circuit which (RoHS Compliant) monitors the junction temperature to prevent over-heating conditions. The APW8723 is available in TDFN3x3-10 package. Applications • • DSL, Switch HUB • Wireless Lan • Notebook Computer • Mother Board • LCD Monitor/TV Graphic Cards ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2013 1 www.anpec.com.tw APW8723 Simplified Application Circuit VIN APW8723 (TDFN3x3-10) BOOT UGATE COMP PHASE LGATE/ OCSET REFOUT OFS Current Controller Ordering and Marking Information Package Code QB : TDFN3x3-10 Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device APW8723 Assembly Material Handling Code Temperature Range Package Code APW8723 QB : APW 8723 XXXXX XXXXX - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Pin Configuration BOOT UGATE PHASE LGATE/OCSET VCC 1 2 3 4 5 10 9 8 7 6 REPOUT OFS POK COMP FB TDFN3x3-10 (Top View) Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2013 2 www.anpec.com.tw APW8723 Absolute Maximum Ratings (Note 1) Symbol VVCC Parameter VCC Supply Voltage (VCC to GND) BOOT Supply Voltage (BOOT to PHASE) VBOOT BOOT Supply Voltage (BOOT to GND) VUGATE UGATE Voltage (UGATE to PHASE) VLGATE LGATE Voltage (LGATE to GND) VPHASE PHASE Voltage (PHASE to GND) Storage Temperature Maximum Lead Soldering Temperature, 10 Seconds V V -0.3 ~ 32 V < 40ns -0.3 ~ 40 V > 40ns -0.3 ~ VBOOT+0.3 V < 40ns -5 ~ VBOOT+5 V > 40ns -0.3 ~ VVCC+0.3 V < 40ns -5 ~ VVCC+5 V > 40ns -0.3 ~ 16 V < 40ns -5 ~ 30 V Maximum Junction Temperature TSTG -0.3 ~ 16 -0.3 ~ 16 POK to GND TSDR Unit > 40ns FB and COMP to GND TJ Rating -0.3 ~ 7 V -0.3~VCC+0.3 V 150 °C -65 ~ 150 °C 260 °C Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics Symbol θJA Parameter Thermal Resistance -Junction to Ambient Typical Value Unit (Note 2) TDFN3x3-10 °C/W 55 Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. Recommended Operating Conditions (Note 3) Symbol Parameter Range Unit VIN VIN Supply Voltage 4 ~ 13.2 V VVCC VCC Supply Voltage 4.5 ~ 13.2 V VOUT Converter Output Voltage 0.8 ~ 5 V IOUT Converter Output Current 0 ~ 25 A TA Ambient Temperature -40 ~ 85 °C TJ Junction Temperature -40 ~ 125 °C Note 3: Refer to the application circuit for further information. Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2013 3 www.anpec.com.tw APW8723 Electrical Characteristics Refer to the typical application circuit. These specifications apply over VVCC = 12V, TA = -40°C to 85°C, unless otherwise noted. Typical values are at TA = 25°C. Symbol Parameter APW8723 Test Conditions Unit Min. Typ. Max. INPUT SUPPLY VOLTAGE AND CURRENT IVCC VCC Supply Current (Shutdown Mode) UGATE and LGATE open; COMP=GND - - 550 µA VCC Supply Current UGATE and LGATE open - 2 3 mA Rising VCC POR Threshold 3.8 4.1 4.4 V VCC POR Hysteresis 0.3 0.5 0.6 V 270 300 330 kHz - 1.5 - V - - 90 % 0.792 0.8 0.808 V - 667 - uA/V 20 - MHz - 0.1 µA POWER-ON-RESET(POR) OSCILLATOR FOSC Oscillator Frequency ∆VOSC Oscillator Sawtooth Amplitude (Note 4) DMAX Maximum Duty Cycle (1.2V~2.7V typical) REFERENCE VREF Reference Voltage TA = -40 ~ 85°C ERROR AMPLIFIER gm Transconductance (Note 4) Open-Loop Bandwidth (Note 4) RL = 10kΩ, CL = 10pF - FB Input Leakage Current VFB = 0.8V - Maximum COMP Source Current VCOMP=2V 200 uA Maximum COMP Sink Current VCOMP=2V 200 uA GATE DRIVERS TD High-side Gate Driver Source Current VBOOT-GND= 12V, VUGATE-PHASE = 6V - 1.0 - High-side Gate Driver Sink Current VBOOT-GND= 12V, VUGATE-PHASE = 6V - 1.1 - Low-side Gate Driver Source Current VVCC = 12V, VLGATE-GND = 6V - 1.8 - Low-side Gate Driver Sink Current VVCC = 12V, VLGATE-GND = 6V - 2.0 - - 30 - ns 45 50 55 % - 2 - µs Dead-time (Note 4) A A PROTECTIONS VFB_UV FB Under-Voltage Protection Trip Point Percentage of VOFS Under-Voltage Debounce Interval VFB_OV FB Over-Voltage Protection Rising Threshold VFB rising 120 125 130 % FB Over-Voltage Protection Hysteresis VFB falling - 20 - % - 2 - µs 55 - 600 mV 621 690 759 mV Over-Voltage Debounce Interval OCP setting Range VOCP_MAX VOCSET=IOCSET×ROCSET Built-in Maximum OCP Voltage Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2013 4 www.anpec.com.tw APW8723 Electrical Characteristics (Cont.) Refer to the typical application circuit. These specifications apply over VVCC = 12V, TA = -40°C to 85°C, unless otherwise noted. Typical values are at TA = 25°C. Symbol Parameter APW8723 Test Conditions Unit Min. Typ. Max. OCSET Current Source 9 10 11 Over-Temperature Protection Threshold - 140 - o Hysteresis - 40 - o - 2 - ms - - 0.4 V PROTECTIONS (cont.) IOCSET µA C C SOFT-START TSS Internal Soft-Start Interval (Note 4) VOUT from 0% to 90% Regulation COMP VOLTAGE VDISABLE Shutdown Threshold of VCOMP OFS FUNCTION REFOUT current limiting Only sourcing OFS setting range - 2 - mA 0.4 - 3 V - 0.1 1 µA 85 90 95 % POWER GOOD (Only for TDFN3×3-10 Package) IPOK POK Leakage Current VPOK=5V VFB is from low to target value (POK Goes High) VPOK POK Threshold POK Delay Time VFB Falling, POK Goes Low 45 VFB Rising, POK Goes Low 120 Vref=90% regulation to POK high goes - 50 125 1.5 55 % 130 % - ms Note 4: Guaranteed by design, not production tested. Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2013 5 www.anpec.com.tw APW8723 Typical Operating Characteristics Switching Frequency vs. Junction Temperature Reference Voltage vs. Junction Temperature 0.81 350 340 Switching Frequency (kHz) Reference Voltage (V) VCC = 12V 0.805 0.8 0.795 330 320 310 300 290 280 270 260 0.79 -20 250 0 20 40 60 80 100 120 -20 0 20 60 80 100 120 Load Regulation Line Regulation 0.2 0.3 VCC=12V IL=0A Vout=1.2V 0.2 Output Voltage Variation (%) Output Voltage Variation (%) 40 o Junction Temperature ( C) o Junction Temperature ( C) 0.1 0 -0.1 -0.2 0.1 0 -0.1 -0.2 -0.3 4 5 6 7 8 9 10 11 12 0 13 2 4 6 8 10 Output Current (A) Input Voltage(V) IOCSET vs. Junction Temperature 11.4 OCSET Current Source (A) 11 10.6 10.2 9.8 9.4 9 8.6 -20 0 20 40 60 80 100 120 Junction Temperature (oC) Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2013 6 www.anpec.com.tw APW8723 Operating Waveforms Refer to the typical application circuit. The test condition is VIN=12V, TA= 25oC unless otherwise specified. Power On Power Off VIN VIN 1 1 2 VOUT 2 VOUT VUGATE V UGATE 3 3 CH1: VIN, 5V/Div CH1: VIN, 5V/Div CH2: VOUT, 1V/Div CH3: VUGATE, 10V/Div TIME: 1ms/Div CH2: VOUT, 1V/Div CH3: VUGATE, 10V/Div TIME: 50ms/Div Enable Shutdown VCOMP VCOMP 1 1 V OUT VOUT 2 2 V UGATE VUGATE 3 3 CH1: VCOMP, 1V/Div CH2: VOUT, 1V/Div CH3: VUGATE, 10V/Div TIME: 1ms/Div Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2013 CH1: VCOMP, 1V/Div CH2: VOUT, 1V/Div CH3: VUGATE, 10V/Div TIME: 1ms/Div 7 www.anpec.com.tw APW8723 Operating Waveforms Refer to the typical application circuit. The test condition is VIN=12V, TA= 25oC unless otherwise specified. Over-Current Protection Under-Voltage Protection R OCSET =6.8kΩ,R DS (low Side )=10.5mΩ VOUT V OUT 1 VPHASE 2 1 IL IL 3 2 CH1: VOUT, 1V/Div CH2: IL,10A/Div TIME: 1ms/Div CH1: VOUT, 1V/Div CH2: VPHASE,10V/Div CH3: IL,10A/Div TIME: 10us/Div UGATE Falling UGATE Rising VUGATE VUGATE 1 1 2 VLGATE 2 VPHASE 3 3 CH1: VUGATE, 20V/Div CH2: VLGATE ,10V/Div CH3: VPHASE ,10V/Div TIME: 20ns/Div Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2013 V PHASE V LGATE CH1: VUGATE, 20V/Div CH2: VLGATE ,10V/Div CH3: VPHASE ,10V/Div TIME: 20ns/Div 8 www.anpec.com.tw APW8723 Operating Waveforms Refer to the typical application circuit. The test condition is VIN=12V, TA= 25oC unless otherwise specified. Power OK Load Transient VOUT 1 V OUT 1 I OUT Pok 2 2 CH1: VOUT, 50mV/Div,AC CH2: IOUT, 5A/Div TIME: 200us/Div CH1: VOUT, 1V/Div CH2: POK, 5V/Div TIME: 1ms/Div Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2013 9 www.anpec.com.tw APW8723 Pin Description PIN NO. FUNCTION NAME TDFN3x3-10 1 BOOT This pin provides the bootstrap voltage to the high-side gate driver for driving the N-channel MOSFET. An external capacitor (0.1µF at least) from PHASE to BOOT, an internal switch generates the bootstrap voltage for the high-side gate driver (UGATE). 2 UGATE High-side Gate Driver Output. This pin is the gate driver for high-side MOSFET. 3 PHASE This pin is the return path for the high-side gate driver. Connecting this pin to the high-side MOSFET source and connect a capacitor to BOOT for the bootstrap voltage. This pin is also used to monitor the voltage drop across the low-side MOSFET for over-current protection. 4 LGATE/ OCSET Low-side Gate Driver Output and Over-Current Setting Input. This pin is the gate driver for low-side MOSFET. It also used to set the maximum inductor current. Refer to the section in “Function Description” for detail. 5 VCC Power Supply Input. Connect a nominal 5V to 12V power supply voltage to this pin. A power-on reset function monitors the input voltage at this pin. It is recommended that a decoupling capacitor (1µF to 10µF) be connected to GND for noise decoupling. 6 FB Feedback Input of Converter. The converter senses feedback voltage via FB and regulates the FB voltage at 0.8V. Connecting FB with a resistor-divider from the output sets the output voltage of the converter. This is a multiplexed pin. During soft-start and normal converter operation, this pin represents the output of the error amplifier. It is used to compensate the regulation control loop in combination with the FB pin. 7 COMP 8 POK POK is an open drain output used to indicate the status of the output voltage. Connect the POK pin to 5 to 12V through a pull-high resistor. 9 OFS Reference Voltage Offset Setting. Must connect this pin to REFOUT pin through a resister when APW8723 is used. Operated an installation that can make bi-direction current flow within limits to develop a positive and negative voltage difference between OFS pin and REFOUT pin, then the APW8723 can adjust reference voltage. 10 REFOUT 11 (Exposed Pad) GND Pulling COMP low (VDISABLE = 0.4V max.) will shut down the controller. When the pull-down device is released, the COMP pin will start to rise. When the COMP pin rises above the VDISABLE trip point, the APW8723 will begin a new initialization and soft-start cycle. 0.8V Reference Output. Bypass to GND with a capacitor (0.01µF to 0.1µF). Signal and Power ground. conductivity. Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2013 Connect this pad to the system ground plan for good thermal 10 www.anpec.com.tw APW8723 Block Diagram VCC Regulator BOOT Power-On Reset I OCSET (10 µA typical) Sample and Hold UVLO UGATE Sense Low Side VREF (0.8V typical ) To LGATE VROCSET PHASE UVP Comparator 0.5 VROCSET Soft Start and Fault Logic IZCMP VCC 1. 25 Inhibit OVP Comparator Gate Control LGATE Soft-start PWM Comparator Error Amplifier VREF (0. 8V typical ) REFOUT Oscillator 0 .4V OFS FB Disable COMP Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2013 GND 11 www.anpec.com.tw APW8723 Typical Application Circuit VCC Supply (5~12 V) R4 2 R2 C4 1 µF APW8723 (TDFN3*3-10) 5 8 R5 100kΩ OFF Q3 2N7002 7 Exposed pad ON C1 33pF R2 10kΩ VIN 6 C2 47nF BOOT VCC POK UGATE COMP PHASE 1 C3 0.1µF 2 C IN1 C IN2 1 µF 220µF x 2 Q1 APM 310 9 L1 3 VOUT 0.5 µH GND Q2 APM 3106 LGATE/ 4 OCSET FB REFOUT 10 OFS 9 R OCSET C OUT 1000 µF x 2 R OFFSET Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2013 R3 R1 2kΩ 1 kΩ C5 0.1µF Current Controller 12 www.anpec.com.tw APW8723 Function Description Power-On-Reset (POR) A resistor (ROCSET), connected from the LGATE/OCSET to The Power-On-Reset (POR) function of APW8723 con- GND, programs the over-current trip level. Before the IC initiates a soft-start process, an internal current source, tinually monitors the input supply voltage (VCC) and ensures that the IC has sufficient supply voltage and can IOCSET (10µA typical), flowing through the ROCSET develops a voltage (VROCSET) across the ROCSET. The device holds work well. The POR function initiates a soft-start process while the VCC voltage just exceeds the POR threshold; VROCSET and stops the current source IOCSET during normal operation. When the voltage across the low-side MOSFET the POR function also inhibits the operations of the IC while the VCC voltage falls below the POR threshold. exceeds the VROCSET, the APW8723 turns off the high side and low-side MOSFET, and the device will enter hiccup mode until the over-current phenomenon is released. The APW8723 has an internal OCP voltage, VOCP_MAX, and the value is 0.621V(minmum). When the ROCSET x IOCSET Soft-Start The APW8723 builds in a soft-start function about 2ms (Typ.) interval, which controls the output voltage rising as exceed 0.621V or the ROCSET is floating or not connected, the VROCSET will be the default value 0.621V. The over cur- well as limiting the current surge at the start-up. During soft-start, an internal ramp voltage connected to the one rent threshold would be 0.621V across low-side MOSFET. The threshold of the valley inductor current limit is there- of the positive inputs of the error amplifier replaces the reference voltage (0.8V typical) until the ramp voltage fore given by: reaches the reference voltage. The soft-start circuit interval is shown as figure 1. ILIMIT = IOCSET × ROCSET RDS(ON) (low − side) Voltage(V) For the over-current is never occurred in the normal oper- Soft Start POK Delay Time Time ating load range, the variation of all parameters in the above equation should be considered: VVCC OCSET count completed OCSET count start (OCSET duratiom, t2- t1, less than 0.474ms) VPOK 0.9 xVREF - The RDS(ON) of low-side MOSFET is varied by temperature and gate to source voltage. Users should determine the maximum RDS(ON) by using the manufacturer’s datasheet. VOUT - The minimum IOCSET (9µA) and minimum ROCSET should be used in the above equation. t0 t1 t2 t3 t4 - Note that the ILIMIT is the current flow through the lowside MOSFET; ILIMIT must be greater than valley inductor Time current which is output current minus the half of inductor ripple current. Figure 1. Soft-Start Interval Over-Current Protection of the PWM Converter ILIMIT > IOUT(MAX) − The over-current function protects the switching converter against over-current or short-circuit conditions. The con- ∆I 2 Where ∆I = output inductor ripple current - The overshoot and transient peak current also should troller senses the inductor current by detecting the drainto-source voltage which is the product of the inductor’s be considered. current and the on-resistance of the low-side MOSFET during it’s on-state. This method enhances the converter’s efficiency and reduces cost by eliminating a current sensing resistor required. Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2013 13 www.anpec.com.tw APW8723 Function Description (Cont.) Under-Voltage Protection the controller into shutdown mode which UGATE and The under-voltage function monitors the voltage on FB LGATE are pulled to PHASE and GND respectively. When the pull-down device is released, the COMP volt- (VFB) by Under-Voltage (UV) comparator to protect the PWM converter against short-circuit conditions. When the VFB age will start to rise. When the COMP voltage rises above the VDISABLE threshold, the APW8723 will begin a new ini- falls below the falling UVP threshold (50% VREF), a fault tialization and soft-start process. signal is internally generated and the device turns off highside and low-side MOSFETs. The device will enters hiccup mode until the UVP is released. Adaptive Shoot-Through Protection of the PWM Converter Over-Voltage Protection (OVP) The over-voltage protection monitors the FB voltage to prevent the output from over-voltage condition. When the The gate drivers incorporate an adaptive shoot-through protection to prevent high-side and low-side MOSFETs output voltage rises above 125% of the nominal output voltage, the APW8723 turns off the high-side MOSFET from conducting simultaneously and shorting the input supply. This is accomplished by ensuring the falling gate and turns on the low-side MOSFET until the output voltage falls below 105%, the OVP comparator is disen- has turned off one MOSFET before the other is allowed to rise. gaged and both high-side and low-side drivers turn off. This OVP scheme only clamps the voltage overshoot and During turn-off the low-side MOSFET, the LGATE voltage is monitored until it is below 1.5V threshold, at which does not invert the output voltage when otherwise activated with a continuously high output from low-side time the UGATE is released to rise after a constant delay. During turn-off of the high-side MOSFET, the UGATE-to- MOSFET driver. It’s a common problem for OVP schemes PHASE voltage is also monitored until it is below 1.5V threshold, at which time the LGATE is released to rise with a latch. Once an over-voltage fault condition is set, it can be reset by releasing COMP or toggling VCC power- after a constant delay. on-reset signal. Reference Voltage Offset Functionr For some special applications like over-clocking Purpose Over-Temperature Protection (OTP) or variety output voltage choice, the APW8723 can provide reference voltage offset function to support these When the junction temperature increases above the rising threshold temperature TOTR, the IC will enter the applications. It must connect OFS pin to REFOUT pin through a resister (ROFFSET) when APW8723 is used. Op- over-temperature protection state that suspends the PWM, which forces the UGATE and LGATE gate drivers erated an installation that can make bi-direction current flow within limits to develop a positive and negative output low. The thermal sensor allows the converters to start a start-up process and regulate the output voltage voltage difference between OFS pin and REFOUT pin, then the APW8723 can adjust reference voltage. It is de- again after the junction temperature cools by 40oC. The OTP is designed with a 40oC hysteresis to lower the av- termined by: erage TJ during continuous thermal overload conditions, which increases lifetime of the APW8723. VOFS = VREFOUT ± (IOFFSET × ROFFSET ) Shutdown and Enable The APW8723 can be shut down or enabled by pulling When this function is inhibited, the R OFFSET should be short to ensure that VOFS equals VREFOUT. low the voltage on COMP. The COMP is a dual-function pin. During normal operation, this pin represents the output of the error amplifier. It is used to compensate the regulation control loop in combination with the FB pin. Pulling the COMP low (VDISABLE = 0.4V maximum) places Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2013 14 www.anpec.com.tw APW8723 Application Information Output Voltage Selection lower output ripple voltage. The ripple current and ripple The output voltage can be programmed with a resistive voltage can be approximated by: IRIPPLE = divider. Use 1% or better resistors for the resistive divider is recommended. The FB pin is the inverter input of the VIN − VOUT VOUT × FSW × L VIN where Fs is the switching frequency of the regulator. error amplifier, and the reference voltage is 0.8V. The output voltage is determined by: ∆VOUT = IRIPPLE x ESR R VOUT = 0.8 × 1 + 1 R2 A tradeoff exists between the inductor’s ripple current and the regulator load transient response time. A smaller inductor will give the regulator a faster load transient re- Where R1 is the resistor connected from VOUT to FB and R2 is the resistor connected from FB to the GND. sponse at the expense of higher ripple current and vice versa. The maximum ripple current occurs at the maxi- Output Capacitor Selection The selection of COUT is determined by the required effec- mum input voltage. A good starting point is to choose the ripple current to be approximately 30% of the maximum tive series resistance (ESR) and voltage rating rather than the actual capacitance requirement. Therefore, selecting output current. Once the inductance value has been chosen, selecting high performance low ESR capacitors is intended for switching regulator applications. In some applications, an inductor is capable of carrying the required peak current without going into saturation. In some types of multiple capacitors have to be paralleled to achieve the desired ESR value. If tantalum capacitors are used, make inductors, especially core that is make of ferrite, the ripple current will increase abruptly when it saturates. This will sure they are surge tested by the manufactures. If in doubt, result in a larger output ripple voltage. consult the capacitors manufacturer. Compensation Input Capacitor Selection The output LC filter of a step down converter introduces a The input capacitor is chosen based on the voltage rating and the RMS current rating. For reliable operation, double pole, which contributes with -40dB/decade gain slope and 180 degrees phase shift in the control loop. A select the capacitor voltage rating to be at least 1.3 times higher than the maximum input voltage. The maximum compensation network between COMP pin and ground should be added. The simplest loop compensation net- RMS current rating requirement is approximately IOUT/2 where IOUT is the load current. During power up, the input work is shown in Figure 5. The output LC filter consists of the output inductor and capacitors have to handle large amount of surge current. If tantalum capacitors are used, make sure they are surge output capacitors. The transfer function of the LC filter is given by: tested by the manufactures. If in doubt, consult the capacitors manufacturer. GAINLC = For high frequency decoupling, a ceramic capacitor between 0.1µF to 1µF can connect between VCC and ground The poles and zero of this transfer function are: FLC = pin. Inductor Selection 1 2 × π × L × COUT FESR = The inductance of the inductor is determined by the output voltage requirement. The larger the inductance, the 1 2 × π × ESR × COUT The FLC is the double poles of the LC filter, and FESR is the zero introduced by the ESR of the output capacitor. lower the inductor’s current ripple. This will translate into Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2013 1 + s × ESR × COUT s2 × L × COUT + s × ESR × COUT + 1 15 www.anpec.com.tw APW8723 Application Information (Cont.) Compensation (Cont.) The compensation circuit is shown in Figure 5. R2 and C2 introduce a zero and C1 introduces a pole to reduce L Output PHASE the switching noise. The transfer function of error amplifier is given by: COUT 1 1 // GAIN AMP = gm × ZO = gm × R2 + sC2 sC1 ESR = gm × 1 s + R2 × C2 s × s + Figure 2. The Output LC Filter C2 + C1 × C1 R2 × C1× C2 The pole and zero of the compensation network are: 1 FP = C1× C2 2 × π × R2 × C1 + C2 1 FZ = 2 × π × R2 × C2 FLC -40dB/dec FESR Gain VOUT -20dB/dec Error Amplifier R1 FB - COMP Frequency R3 Figure 3. The LC Filter Gain & Frequency + R2 VREF The PWM modulator is shown in Figure 4. The input is the output of the error amplifier and the output is the PHASE C1 C2 node. The transfer function of the PWM modulator is given by: GAINPWM = VIN ∆VOSC Figure 5. Compensation Network VIN The closed loop gain of the converter can be written as: Driver GAINLC × GAINPWM × PWM Comparator R3 × GAINAMP R1 + R3 Figure 6 shows the converter gain and the following guidelines will help to design the compensation network. VOSC 1.Select the desired zero crossover frequency FO: Output of Error Amplifier PHASE (1/5 ~ 1/10) x FSW >FO>FZ Use the following equation to calculate R2: R2 = Driver ∆VOSC FESR R1+ R3 FO × × × VIN R3 gm FLC2 Where: gm = 667µA/V Figure 4. The PWM Modulator Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2013 16 www.anpec.com.tw APW8723 Application Information (Cont.) where IOUT is the load current Compensation (Cont.) TC is the temperature dependency of RDS(ON) FSW is the switching frequency 2. Place the zero FZ before the LC filter double poles FLC: FZ = 0.75 x FLC tsw is the switching interval D is the duty cycle Calculate the C2 by the equation: C2 = 1 2 × π × R2 × 0.75 × FLC Note that both MOSFETs have conduction losses while the upper MOSFET includes an additional transition loss. The switching internal, tsw, is the function of the reverse transfer capacitance CRSS. Figure 7 illustrates the switch- 3. Set the pole at the half the switching frequency: FP = 0.5xFSW ing waveform internal of the MOSFET. The (1+TC) term factors in the temperature dependency Calculate the C1 by the equation: C1 = C2 π × R2 × C2 × FSW − 1 of the RDS(ON) and can be extracted from the “RDS(ON) vs Temperature” curve of the power MOSFET. VDS FZ=0.75FLC FP=0.5FSW Voltage across Compensation Gain Gain FLC 20.log VIN ∆VOSC FO FESR PWM & Filter Gain Converter Gain drain and source of MOSFET 20 . log(gm . R2) Frequency tsw Figure 6. Converter Gain & Frequency Figure 7. Switching Waveform Across MOSFET MOSFET Selection Layout Consideration The selection of the N-channel power MOSFETs is deter- In any high switching frequency converter, a correct lay- mined by the RDS(ON), reverse transfer capacitance (CRSS), and maximum output current requirement.The losses in out is important to ensure proper operation of the regulator. With power devices switching at 300kHz,the the MOSFETs have two components: conduction loss and transition loss. For the upper and lower MOSFET, the resulting current transient will cause voltage spike across the interconnecting impedance and parasitic circuit losses are approximately given by the following equations: PUPPER = I 2 OUT Time elements. As an example, consider the turn-off transition of the PWM MOSFET. Before turn-off, the MOSFET is car- (1+ TC)(RDS(ON))D + (0.5)(Iout)(VIN)(tsw)FSW rying the full load current. During turn-off, current stops flowing in the MOSFET and is free-wheeling by the lower PLOWER = IOUT2 (1+ TC)(RDS(ON))(1-D) MOSFET and parasitic diode. Any parasitic inductance of the circuit generates a large voltage spike during the switching interval. In general, using short and wide printed circuit traces should minimize interconnecting imped Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2013 17 www.anpec.com.tw APW8723 Application Information (Cont.) Layout Consideration (Cont.) APW8723 VIN ances and the magnitude of voltage spike. And signal and power grounds are to be kept separate till combined using ground plane construction or single point VCC grounding. Figure 8. illustrates the layout, with bold lines indicating high current paths; these traces must be short BOOT and wide. Components along the bold lines should be placed lose together. Below is a checklist for your layout: - Keep the switching nodes (UGATE, LGATE, and PHASE) away from sensitive small signal nodes since these L O A D UGATE PHASE LGATE ROCSET VOUT nodes are fast moving signals. Therefore, keep traces to these nodes as short as possible. Close to IC - The traces from the gate drivers to the MOSFETs (UG and LG) should be short and wide. Figure 8. Layout Guidelines - Place the source of the high-side MOSFET and the drain of the low-side MOSFET as close as possible. Minimizing the impedance with wide layout plane between the two pads reduces the voltage bounce of the node. Recommended Minimum Footprint - Decoupling capacitor, compensation component, the resistor dividers, and boot capacitors should be close ThermalVia diameter 12mil X 5 0.75mm their pins. (For example, place the decoupling ceramic capacitor near the drain of the high-side MOSFET as 0.30mm close as possible. The bulk capacitors are also placed near the drain). loads. The input capacitor GND should be close to the output capacitor GND and the lower MOSFET GND. - The drain of the MOSFETs (VIN and PHASE nodes) should be a large plane for heat sinking. 2.70mm - The input capacitor should be near the drain of the upper MOSFET; the output capacitor should be near the 0.50mm 1.75mm - The ROCSET resistance should be placed near the IC as close as possible. Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2013 Ground plane for ThermalPAD 0.275mm TDFN3X3 -10 L and Pattern R ecommendation 18 www.anpec.com.tw APW8723 Package Information TDFN3x3-10 A b E D Pin 1 A1 D2 A3 L E2 Pin 1 Corner e S Y M B O L TDFN3x3-10 MILLIMETERS INCHES MIN. MAX. MIN. MAX. A 0.70 0.80 0.028 0.031 A1 0.00 0.05 0.000 0.002 0.30 0.007 0.012 0.122 A3 b 0.20 REF 0.18 0.008 REF D 2.90 3.10 0.114 D2 2.20 2.70 0.087 0.106 0.122 0.069 E 2.90 3.10 0.114 E2 1.40 1.75 0.055 0.50 0.012 e 0.50 BSC L 0.30 K 0.20 0.020 BSC 0.020 0.008 Note : 1. Followed from JEDEC MO-229 VEED-5. Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2013 19 www.anpec.com.tw APW8723 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application TDFN3x3-10 A H T1 C d D 330.0±2.00 50 MIN. 12.4+2.00 -0.00 13.0+0.50 -0.20 W E1 1.5 MIN. 20.2 MIN. P0 P1 P2 D0 D1 T A0 B0 K0 4.0±0.10 8.0±0.10 2.0±0.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 3.30±0.20 3.30±0.20 1.30±0.20 12.0±0.30 1.75±0.10 F 3.5±0.05 (mm) Devices Per Unit Package Type TDFN3x3-10 Unit Tape & Reel Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2013 Quantity 3000 20 www.anpec.com.tw APW8723 Taping Direction Information TDFN3x3-10 USER DIRECTION OF FEED Classification Profile Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2013 21 www.anpec.com.tw APW8723 Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Thickness <2.5 mm ≥2.5 mm Volume mm <350 235 °C 220 °C 3 Volume mm ≥350 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2013 22 Description 5 Sec, 245°C 1000 Hrs, Bias @ Tj=125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA www.anpec.com.tw APW8723 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2013 23 www.anpec.com.tw