ANPEC APW8728QBI-TRG

APW8728
VGA PWM Controller with Differential Voltage Feedback
Features
General Description
•
Adjustable Output Voltage from +0.6V to +3.3V
The APW8728 is a single-phase, constant on-time,
- 0.6V Reference Voltage
synchronous PWM controller, which drives N-channel
MOSFETs. The APW8728 steps down high voltage to
- ±0.6% Accuracy Over-Temperature
•
generate low-voltage chipset or RAM supplies in notebook
computers.
Operates from An Input Battery Voltage Range of
+1.8V to +28V
•
The APW8728 provides excellent transient response and
accurate DC voltage output in either PFM or PWM Mode.
Remote Feedback Sense for Excellent Output
Voltage
•
In Pulse Frequency Mode (PFM), the APW8728 provides
very high efficiency over light to heavy loads with loading-
REFIN Function for Over-clocking Purpose from
0.5V~2.5V range
•
Power-On-Reset Monitoring on VCC pin
•
Excellent line and load transient responses
•
PFM mode for increased light load efficiency
•
Programmable PWM Frequency from 100kHz to
modulated switching frequencies. In PWM Mode, the
converter works nearly at constant frequency for low-noise
requirements. APW8728 is built in remote sense function
for applications that require remote sense.
The APW8728 is equipped with accurate positive current
limit, output under-voltage, and output over-voltage
500kHz
•
protections, perfect for NB applications. The Power-OnReset function monitors the voltage on VCC to prevent
Selectable Forced PWM or automatic PFM/PWM
mode
•
Built in 30A Output current driving capability
•
Integrate MOSFET Drivers
•
Integrated Bootstrap Forward P-CH MOSFET
•
Adjustable Integrated Soft-Start and Soft-Stop
•
Power Good Monitoring
•
70% Under-Voltage Protection
•
125% Over-Voltage Protection
•
TQFN3x3-16 Package
•
Lead Free and Green Devices Available
wrong operation during power-on. The APW8728 has a
1ms digital soft start and built-in an integrated output
discharge device for soft stop. An internal integrated softstart ramps up the output voltage with programmable
slew rate to reduce the start-up current. A soft-stop function
actively discharges the output capacitors.
The APW8728 is available in 16pin TQFN3x3-16 package
respectively.
Simplified Application Circuit
(RoHS Compliant)
VCC=5V
Applications
EN REFIN
UGATE
Table PC
•
Hand-Held Portable
•
AIO PC
Q1
APW8728
Notebook
•
VIN
TON
RPOK
POK
•
RTON
VOUT
RTN
L
PHASE
OCSET
LGATE
VOUT
Q2
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Dec., 2012
1
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APW8728
Pin Configuration
BOOT 13
RTN 14
EN 15
TON 16
VOUT
1
12 UGATE
VCC
2
11 PHASE
FB
3
10 OCSET
POK
4
9
PVCC
7
GND
PGND
LGATE
6
REFIN
8
5
TQFN3x3-16
(TOP VIEW)
Ordering and Marking Information
APW8728
Assembly Meterial
Package Code
QB : TQFN3x3-16
Temperature Range
Handling Code
I : -40 to 85 oC
Handling Code
.
Temperature Range
Assembly Meterial
TR : Tape & Reel
L : Lead Free Device
Package Code
APW8728 QB :
APW
8728
XXXXX
G : Halogen and Lead Free Device
XXXXX - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Dec., 2012
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APW8728
Absolute Maximum Ratings (Note 1)
Symbol
VCC
VBOOT-GND
VBOOT
Rating
Unit
VCC Supply Voltage (VCC to GND)
Parameter
-0.3 ~ 7
V
BOOT Supply Voltage (BOOT to GND or PGND)
-0.3 ~ 37
V
BOOT Supply Voltage (BOOT to PHASE)
-0.3 ~ 7
V
-0.3 ~ VCC+0.3
V
<20ns Pulse Width
>20ns Pulse Width
-5 ~ VBOOT+1.5
-0.3 ~ VBOOT+0.3
V
<20ns Pulse Width
>20ns Pulse Width
-5 ~ VCC+1.5
-0.3 ~ VCC+0.3
V
<20ns Pulse Width
>20ns Pulse Width
-5 ~ 35
-1 ~ 30
V
All Other Pins (VOUT, TON, EN and FB to GND)
UGATE Voltage (UGATE to PHASE)
LGATE Voltage (LGATE to GND)
PHASE Voltage (PHASE to GND)
VPHASE
TJ
Maximum Junction Temperature
TSTG
Storage Temperature
TSDR
Maximum Lead Soldering Temperature(10 Seconds)
150
o
-65 ~ 150
o
260
o
C
C
C
Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Thermal Characteristics
Symbol
θJA
Parameter
Thermal Resistance-Junction to Ambient
Typical Value
Unit
(Note2)
TQFN3x3-16
°C/W
40
Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air.
Recommended Operating Conditions (Note 3)
Symbol
Range
Unit
VIN
Converter Input Voltage
1.8 ~ 28
V
VCC
VCC Supply Voltage
4.5 ~ 5.5
V
VOUT
Converter Output Voltage (external REFIN input)
0.5 ~ 2.5
V
Converter Output Voltage (internal FB setting)
0.6~ 3.3
V
IOUT
TJ
Parameter
Converter Output Current
0~ 30
Junction Temperature
-40 ~ 125
A
o
C
Note 3: Refer to the typical application circuit.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Dec., 2012
3
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APW8728
Electrical Characteristics
Unless otherwise specified, these specifications apply over VCC=5V and TA= -40 to 85 oC. Typical values are at TA=25oC.
Symbol
Parameter
APW8728
Test Conditions
Unit
Min.
Typ.
Max.
VOUT AND VFB VOLTAGE
REFIN Voltage
Output Voltage
External REFIN output voltage
tolerance, REFIN=1V
External REFIN adjustable output
range
Internal FB adjustable output
range
-5
-
5
0.5
-
2.5
0.6
-
3.3
TA = 25 oC
-0.4
-
+0.4
%
TA = -40 oC ~ 85 oC
-0.6
-
+0.6
%
0.02
0.1
µA
20
32
Ω
600
750
µA
-
0
7
µA
VIN=15V, VOUT=1.25V, RTON=1MΩ
267
334
401
ns
80
110
140
ns
350
450
550
ns
V
Reference Voltage
VREF
Regulation Accuracy
IFB
FB Input Bias Current
TDIS
VOUT Discharge Resistance
mV
0.6
FB=0.5V
-
V
SUPPLY CURRENT
IVCC
VCC Input Bias Current
VCC Current, EN=5V,
VFB=0.65V, PHASE=0.5V
IVCC_SHDN
VCC Shutdown Current
EN=GND, VCC=5V
SWITCHING FREQUENCY AND DUTY AND INTERNAL SOFT START
TON
on time
TON(MIN)
Minimum on time
TOFF(MIN)
Minimum off time
VFB=0.55V, VPHASE=-0.1V
Internal Soft Start Time
EN High to VOUT Regulation(95%)
-
1.0
-
ms
UG Pull-Up Resistance
BOOT-UG=0.5V
-
1.5
3
Ω
UG Sink Resistance
UG-PHASE=0.5V
-
0.7
1.8
Ω
LG Pull-Up Resistance
PVCC-LG=0.5V
-
1.0
2.2
Ω
LG Sink Resistance
LG-PGND=0.5V
-
0.5
1.2
Ω
UG to LG Dead time (Note4)
UG falling to LG rising
-
20
-
ns
LG to UG Dead time (Note4)
LG falling to UG rising
-
20
-
ns
Ron
VVCC – VBOOT-GND, IF = 10mA
-
0.3
0.4
V
Reverse Leakage
VBOOT-GND = 30V, VPHASE = 25V,
VVCC = 5V
-
-
0.5
µA
4.25
4.35
4.45
V
-
100
-
mV
4.25
4.35
4.45
V
-
100
-
mV
TSS
GATE DRIVER
BOOTSTRAP SWITCH
VF
IR
VCC POR THRESHOLD
VVCC_THR
Rising VCC POR Threshold
Voltage
VCC POR Hysteresis
VPVCC_THR
Rising PVCC POR
Threshold Voltage
PVCC POR Hysteresis
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Dec., 2012
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APW8728
Electrical Characteristics
Unless otherwise specified, these specifications apply over VCC=5V and TA= -40 to 85 oC. Typical values are at TA=25oC.
Symbol
Parameter
APW8728
Test Conditions
Unit
Min.
Typ.
Max.
CONTROL INPUTS
Shutdown
REFIN Voltage threshold
-
-
0.4
External Reference, VOUT=VREFIN
0.5
-
2.5
Internal Reference, VOUT=FB
setting
2.8
3
3.2
-
0.1
1.0
µA
V
REFIN Leakage
REFIN=0V
REFIN slew rate
Internal rise/fall limit
-
8
-
mV/us
Shutdown
-
-
0.4
V
Hysteresis
-
30
-
mV
Enable
0.5
-
-
V
POK in from Lower (POK Goes
High)
87
90
93
%
POK out from normal (POK Goes
Low) with 30us noise filter
120
125
130
%
-
0.1
1.0
µA
2.5
7.5
-
mA
-
1.6
-
ms
18
20
22
µA
-
4500
-
ppm/ oC
300
mV
EN Voltage threshold
POWER-OK INDICATOR
VPOK
IPOK
POK Threshold
POK Leakage Current
VPOK=5V
POK Sink Current
VPOK=0.5V
POK Enable Delay Time
EN High to POK High
CURRENT SENSE
IOCSET
IOCSET OCP Threshold
IOCSET Sourcing
TCIOCSET
IOCSET Temperature
Coefficient
On The Basis of 25°C
VOCSET
Current Limit Threshold
Setting Range
VOCSET-GND Voltage, Over All
Temperature
Maximum Current Limit
Threshold
ROCSET open
-
0.6
Zero Crossing Comparator
Offset
VGND-PHASE Voltage
-3
0
3
mV
Over current protection
Comparator Offset
(VOCSET-PHASE-VGND-PHASE) Voltage,
VOCSET-GND=60mV
-10
0
10
mV
60
70
80
%
-
16
-
µs
-
1.6
-
ms
30
V
PROTECTION
VUV
UVP Threshold
UVP Debounce Interval
UVP Enable Delay
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Dec., 2012
EN High to POK High
5
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APW8728
Electrical Characteristics
Unless otherwise specified, these specifications apply over VCC=5V and TA= -40 to 85 oC. Typical values are at TA=25oC.
Symbol
Parameter
APW8728
Test Conditions
Unit
Min.
Typ.
Max.
120
125
130
%
-
5
-
%
-
2
-
µs
-
140
-
o
-
25
-
o
PROTECTION
VOVR
OVP Rising Threshold
OVP Hysteresis
OVP Propagation Delay
TOTR
OTP Rising Threshold
OTP Hysteresis
VFB Rising
(Note 4)
(Note 4)
C
C
Remote Sense Amplifier
Bw
Open loop bandwidth (Note4)
-
6
-
MHz
Open loop gain (Note4)
-
86
-
dB
Note4: Guaranteed by design.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Dec., 2012
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APW8728
Pin Description
PIN
NO.
FUNCTION
NAME
TQFN3x3-16
This pin is the positive node of the differential remote voltage sensing.
The VOUT pin should be connected to the remote load voltage sense point directly.
1
VOUT
2
VCC
3
FB
Output Voltage Feedback Pin. In internal mode, this pin is connected to the resistive divider that set
the desired output voltage. The POK, UVP, and OVP circuits detect this signal to report output
voltage status.
4
POK
Power Good Output. POK is an open drain output used to indicate the status of the output voltage.
Connect the POK in to +5V through a pull-high resistor.
5
REFIN
6
GND
7
PGND
Power Ground of The LG Low-side MOSFET Driver. Connect the pin to the Source of the low-side
MOSFET
8
LGATE
Output of The Low-side MOSFET Driver. Connect this pin to Gate of the low-side MOSFET. Swings
from PGND to VCC.
9
PVCC
Supply Voltage Input Pin for The LG Low-side MOSFET Gate Driver. Connect +5V from the PVCC
pin to the PGND pin. Decoupling at least 1µF of a MLCC capacitor from the PVCC pin to the PGND
pin.
10
OCSET
11
PHASE
12
UGATE
13
BOOT
Supply Input for The UGATE Driver and An Internal Level-shift Circuit. Connect to an external
capacitor to create a boosted voltage suitable to drive a logic-level N-channel MOSFET.
14
RTN
This pin is the negative node of the differential remote voltage sensing. The RTN pin should be
connected to the remote GND sense point directly.
15
EN
16
TON
Supply Voltage Input Pin for Control Circuitry. Connect +5V from the VCC pin to the GND.
Decoupling at least 1µF of a MLCC capacitor from the VCC pin to the GND.
Enable/Shutdown Pin or External Reference Selection of The PWM Controller.
Signal Ground for The IC
Current-Limit Threshold Setting Pin. There is an internal source current 10µA through a resistor
from OCSET pin to PHASE. This pin is used to monitor the voltage drop across the Drain and
Source of the low-side MOSFET for current-limit.
Junction Point of The High-side MOSFET Source, Output Filter Inductor and The Low-side
MOSFET Drain. Connect this pin to the Source of the high-side MOSFET. PHASE serves as the
lower supply rail for the UG high-side gate driver.
Output of The High-side MOSFET Driver. Connect this pin to Gate of the high-side MOSFET.
Enable Pin of The PWM Controller. When the EN is above high logic level, the Device is in
automatic PFM/PWM Mode. When the EN is below low logic level, the device is in shutdown and only
low leakage current is taken from VCC and VIN.
This Pin is Allowed to Adjust The Switching Frequency. Connect a resistor RTON=400kΩ ~ 1500kΩ
from TON pin to VIN.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Dec., 2012
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APW8728
Typical Operating Characteristics
Converter Output Voltage vs.
Converter Output Current
0.606
1.020
EXTERNAL MODE
Converter Output Voltage, VOUT (V)
Reference Voltage Accuracy, VREF (V)
Reference Voltage Accuracy vs.
Junction Temperature
0.604
0.602
0.600
0.598
0.596
0.594
1.015
1.010
1.005
1.000
0.995
0.990
VIN=8V
0.985
VIN=19V
0.980
-50 -30 -10 10
30
50 70
2
90 110 130 150
o
Switching Frequency vs.
Converter Output Current
6
7
8
9
10
OCSET Sourcing Current vs.
Junction Temperature
1000
26
VIN=8V,
VOUT =1.05V
OCSET Sourcing Current, IOCSET (µA)
Switching Frequency, FSW (kHz)
5
Converter Output Current, IOUT (A)
Junction Temperature, TJ ( C )
100
10
1
0.1
24
22
20
18
16
14
0.001
0.010
0.100
1.000
10.00
-50 -30
-10
10
30
50
70
90 110 130 150
Converter Output Current, IOUT (A)
Junction Temperature, TJ ( oC )
Efficiency vs Load current
VIN=8V, VOUT=1.05V
Efficiency vs Load current
VIN=19V, VOUT=1.05V
100
100
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
4
3
60
50
40
60
50
40
30
30
20
20
H-Side:SM4370 x1
L-Side:SM4373 x1
10
H-Side:SM4370 x1
L-Side:SM4373 x1
10
0
0
0.01
0.10
1.00
10.00
0.01
100.00
1.00
10.00
100.00
Converter Output Current, IOUT (A)
Converter Output Current, IOUT (A)
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Dec., 2012
0.10
8
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APW8728
Operating Waveforms
Refer to the typical application circuit. The test condition is VIN=19V, TA= 25oC unless otherwise specified.
Enable Before End of Soft-Stop
Enable at Zero Initial Voltage of VOUT
1
1
2
2
3
3
4
4
CH1: VREFIN , 5V/Div, DC
CH1: VREFIN, 5V/Div, DC
CH2: VOUT, 500mV/Div, DC
CH3: VPHASE, 20V/Div, DC
CH4: VPOK, 5V/Div, DC
CH2: VOUT, 500mV/Div, DC
CH3: VPHASE, 20V/Div, DC
CH4: VPOK, 5V/Div, DC
TIME: 500µs/Div
TIME: 500µs/Div
Shutdown at IOUT=20A
Shutdown with Soft-Stop at No Load
1
1
2
3
2
3
4
4
CH1: VREFIN, 5V/Div, DC
CH1: V REFIN, 5V/Div, DC
CH2: VOUT, 500mV/Div, DC
CH3: VPHASE, 20V/Div, DC
CH4: VPOK, 5V/Div, DC
CH2: VOUT, 500mV/Div, DC
CH3: VPHASE, 20V/Div, DC
CH4: V POK, 5V/Div, DC
TIME: 20µs/Div
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Dec., 2012
TIME: 10ms/Div
9
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APW8728
Operating Waveforms
Refer to the typical application circuit. The test condition is VIN=19V, TA= 25oC unless otherwise specified.
Operating at PWM Mode
Operating at PFM Mode
3
3
IL=3A
2
2
1
1
4
4
CH1: V PHASE, 20V/Div, DC
CH2: VLGATE, 5V/Div, DC
CH3: VOUT, 100mV/Div, AC
CH4: IL, 10A/Div, DC
CH1: VPHASE, 20V/Div, DC
CH2: VLGATE , 5V/Div, DC
CH3: VOUT, 100mV/Div, AC
CH4: IL, 10A/Div, DC
TIME: 2μs/Div
TIME: 2μ
s/Div
Under-Voltage Protection
Over-Current Protection
1
2
3
2
1
3
4
4
CH1: VPOK, 5V/Div, DC
CH2: V OUT, 1V/Div, DC
CH3: V PHASE, 20V/Div, DC
CH4: IL, 20A/Div, DC
CH1: VFB , 500mV/Div, DC
CH2: VUGATE , 20V/Div, DC
CH3: VLGATE , 10V/Div, DC
CH4: VPOK, 5V/Div, DC
TIME: 20μs/Div
TIME: 10μs/Div
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Dec., 2012
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APW8728
Operating Waveforms
Refer to the typical application circuit. The test condition is VIN=19V, TA= 25oC unless otherwise specified.
Load Transient
0A->17.5A->0A
When Total Impedance of Line = 20mOhm
Load Transient
5A->20A->5A
When Total Impedance of Line = 20mOhm
3
4
1
2
3
4
1
2
CH1: V OUT_near, 200mV/Div, DC
CH1: VOUT_near, 200mV/Div, DC
CH2: VOUT_remote, 200mV/Div, DC
CH3: IOUT, 10A/Div, DC
CH4: V GND_near-remote , 200mV/Div, DC
CH2: V OUT_remote, 200mV/Div, DC
CH3: IOUT, 10A/Div, DC
CH4: VGND_near -remote, 200mV/Div, DC
TIME: 20μs/Div
TIME: 20μs/Div
Remote Sense
When Total Impedance of Line = 20mOhm
3
1
2
4
CH1: VOUT_near , 200mV/Div, DC
CH2: VOUT_remote, 200mV/Div, DC
CH3: IL, 10A/Div, DC
CH4: VGND_near-remote, 200mV/Div, DC
TIME: 2μs/Div
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Dec., 2012
11
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APW8728
Block Diagram
POK
VOUT
RTN
GND
VREF x 125%
VOUT
PGN
D
Debounce
Time
Sense Low-Side
DIFFOUT
VROCSET
90% VREF
125% VREF
REFIN
EN
OCP
OV
Frequency
Adjustable
Fault
Latch
Logic
UV
BOOT
UGATE
PWM Signal Controller
70% VREF
Thermal
Shutdown
FB
On-Time
Generator
ZC
Error
Comparator
VCC
Digital
Soft Start/Soft Sop
DIFFOUT
VCC
LGATE
VREF
VCC
PHASE
VOUT
PVCC
PHASE
POR
10µA
EN
REFIN
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Dec., 2012
TON
OCSET
12
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APW8728
Typical Application Circuit
FOR External Mode Application
Supply 5 V
VIN
750 k
16
C VCC
1µF
C PV CC
1µ F
POK
4
R POK
100kΩ
REFI
5 N
Enable source
BOOT
PVCC
9
DAC source
TON
VCC
2
R VCC 2R2
15
EN
C IN
13
UGATE
10µF x 2
C BOOT
0.1µF
Q1
APM 4350
L1
12
PHASE
11 R
OCSE
OCSET
10
1
ON
Q3
2N7002
LGATE
14
8
RTN
V+_remote
0 .5µ H
T
VOUT
OFF
VOUT V+_near
Q2
APM 4358
3
C OUT
COUT
MLCC
330µF
22µFx 4
V-_near
L
O
A
D
V-_remote
GND FB PGND 7
6
3
APW8728 (TQFN 3x3-16)
FOR Internal Mode Application
Supply 5 V
R VCC 2R2
C PV CC
1µ F
C VCC
1µF
2
9
DAC source
Enable
source
RPOK
100kΩ
4
5
15
OFF
ON
Q3
2N7002
TON
VCC
BOOT
PVCC
POK
REFI
N
UGATE
PHASE
C IN
10µF x 2
C BOOT
0.1µF
13
Q1
APM 4350
L1
12
11
OCSET
1
LGATE
10
8
RTN
3
Q2
APM 4358
GND FB PGND 7
6
VOUT
0 .5µ H
R OCSET
EN
VOUT
14
VIN
750k
16
3
R TOP
C OUT
10kΩ
330µF
R GND
10 kΩ
APW8728 (TQFN3X3-16)
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Dec., 2012
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APW8728
Function Description
Constant-On-Time PWM Controller with Input Feed-Forward
Where FSW is the nominal switching frequency of the converter in PWM mode.
The constant-on-time control architecture is a pseudofixed frequency with input voltage feed-forward. This ar-
The load current at handoff from PFM to PWM mode is
given by:
chitecture relies on the output filter capacitor’s effective
series resistance (ESR) to act as a current-sense resis-
1 VIN − VOUT
×
× TON−PFM
2
L
V − VOUT
V
1
= IN
×
× OUT
2L
FSW
VIN
ILOAD(PFMtoPWM) =
tor so the output ripple voltage provides the PWM ramp
signal. In PFM operation, the high-side switch on-time is
controlled by the on-time generator is determined solely
by a one-shot whose pulse width is inversely propor-
Power-On-Reset (POR)
tional to the input voltage and directly proportional to the
output voltage. In PWM operation, the high-side switch
A Power-On-Reset (POR) function is designed to prevent
wrong logic controls when the VCC voltage is low. The
on-time is determined by a switching frequency control
circuit in the on-time generator block.
POR function continually monitors the bias supply voltage on the VCC pin if at least one of the enable pins is set
The switching frequency control circuit senses the switching frequency of the high-side switch and keeps regulat-
high. When the rising VCC voltage reaches the rising
POR voltage threshold (4.35V, typical), the POR signal
ing it at a constant frequency in PWM mode. The design
improves the frequency variation and is more outstand-
goes high and the chip initiates soft-start operations.
When this voltage drops lower than 4.25V (typical), the
ing than a conventional constant-on-time controller, which
has large switching frequency variation over input voltage,
POR disables the chip.
output current, and temperature. Both in PFM and PWM,
REFIN Pin Control
the on-time generator, which senses input voltage on
TON pin, provides very fast on-time response to input
The voltage (VREFIN) applied to REFIN pin selects either
enable-shutdown or adjustable external reference. When
VREFIN is above the EN high threshold (2.8V, typical), the
line transients.
Another one-shot sets a minimum off-time (typical:
PWM is enabled. When VREFIN is from 0.5V to 2.5V, the
output voltage can be programmed as same as VREFIN
450ns). The on-time one-shot is triggered if the error comparator is high, the low-side switch current is below the
voltage. When VREFIN is below the EN low threshold, the
chip is in the shutdown and only low leakage current is
current-limit threshold, and the minimum off-time oneshot has timed out.
taken from VCC. Once APW8728 has been operating at
internal mode, it is unable to transform into external mode.
Pulse-Frequency Modulation (PFM)
On the other hand, it is able to transform into internal
mode. The slew rate of VREFIN must be faster than 0.5V/µs
In PFM mode, an automatic switchover to pulse-frequency
modulation (PFM) takes place at light loads. This
switchover is affected by a comparator that truncates the
to avoid wrong output voltage.
low-side switch on-time at the inductor current zero
crossing. This mechanism causes the threshold between
PFM and PWM operation to coincide with the boundary
between continuous and discontinuous inductor-current
operation (also known as the critical conduction point).
The on-time of PFM is given by:
TON −PFM =
V
1
× OUT
FSW
VIN
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Dec., 2012
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APW8728
Function Description (Cont.)
EN Pin Control
When V EN is above the EN high threshold (0.5V,
minimum), the converter is enabled in automatic PFM/
temperature, or shutdown, the chip enables the soft-stop
function. The soft-stop function discharges the output
PWM operation mode. When VEN is below the EN low
threshold (0.4V, maximum), the chip is in the shutdown
voltages to the PGND through an internal 20Ω switch.
Power OK Indicator
and only low leakage current is taken from VCC.
The APW8728 features an open-drain POK pin to indiDigital Soft-Start
The APW8728 integrates digital soft-start circuits to ramp
cate output regulation status. In normal operation, when
the output voltage rises 90% of its target value, the POK
up the output voltage of the converter to the programmed
regulation setpoint at a predictable slew rate. The slew
goes high after 63µs internal delay. When the output voltage outruns 70% or 125% of the target voltage, POK sig-
rate of output voltage is internally controlled to limit the
inrush current through the output capacitors during soft-
nal will be pulled low immediately.
Since the FB pin is used for both feedback and monitor-
start process. The figure 1 shows soft-start sequence.
When the EN pin is pulled above the rising EN threshold
ing purposes, the output voltage deviation can be coupled
directly to the FB pin by the capacitor in parallel with the
voltage, the device initiates a soft-start process to ramp
up the output voltage. The soft-start interval is 1ms (typical)
voltage divider as shown in the typical applications. In
order to prevent false POK from dropping, capacitors need
and independent of the UGATE switching frequency.
to parallel at the output to confine the voltage deviation
with severe load step transient.
1.6ms
Under-Voltage Protection (UVP)
VCC and PVCC
1ms
In the operational process, if a short-circuit occurs, the
output voltage will drop quickly. When load current is big-
VOUT
ger than current-limit threshold value, the output voltage
will fall out of the required regulation range. The under-
REFIN
voltage protection circuit continually monitors the FB voltage after soft-start is completed. If a load step is strong
EN
enough to pull the output voltage lower than the undervoltage threshold, the under-voltage threshold is 70% of
the nominal output voltage, the internal UVP delay counter
starts to count. After 16µs debounce time, the device turns
VPOK
Figure 1. Soft-Start Sequence
off both high-side and low-side MOSEFET with latched
and starts a soft-stop process to shut down the output
During soft-start stage before the POK pin is ready, the
gradually. Toggling enable pin to low or recycling PVCC
or VCC, will clear the latch and bring the chip back to
under-voltage protection is prohibited. The over-voltage
and current-limit protection functions are enabled. If the
output capacitor has residue voltage before start-up, both
low-side and high-side MOSFETs are in off-state until the
internal digital soft-start voltage equals to the VFB voltage.
This will ensure that the output voltage starts from its
existing voltage level.
In the event of under-voltage, over-voltage, over-
operation.
Over-Voltage Protection (OVP)
The over-voltage protection monitors the FB voltage to
prevent the output from over-voltage condition. When the
output voltage rises above 125% of the nominal output
voltage, the APW8728 turns off the high-side MOSFET
and turns on the low-side MOSFET until the output voltage falls below the falling OVP threshold.
Copyright  ANPEC Electronics Corp.
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APW8728
Function Description (Cont.)
Current-Limit
The current-limit circuit employs a “valley” current-sens-
Where R OCSET is the resistor of current-limit setting
ing algorithm (See Figure 2). The APW8728 uses the
low-side MOSFET’s RDS(ON) of the synchronous rectifier
threshold. RDS(ON) is the low side MOSFETs conducive
resistance. ILIMIT is the setting current-limit threshold. ILIMIT
as a current-sensing element. If the magnitude of the
current-sense signal at PHASE pin is above the current-
can be expressed as IOUT minus half of peak-to-peak inductor current.
limit threshold, the PWM is not allowed to initiate a new
cycle. The actual peak current is greater than the current-
The PCB layout guidelines should ensure that noise and
DC errors do not corrupt the current-sense signals at
limit threshold by an amount equals to the inductor ripple
4 current. Therefore, the exact current-limit characteristic
PHASE. Place the hottest power MOSEFTs as close to
the IC as possible for best thermal coupling. When com-
and maximum load capability are the functions of the
sense resistance, inductor value, and input voltage.
bined with the under-voltage protection circuit, this current-limit method is effective in almost every circumstance.
Over-Temperature Protection (OTP)
INDUCTOR CURRENT, IL
IPEAK
When the junction temperature increases above the risIOUT
ing threshold temperature TOTR, the IC will enter the overtemperature protection state that suspends the PWM,
∆I
which forces the UGATE and LGATE gate drivers output
low. The thermal sensor allows the converters to start a
ILIMIT
start-up process and regulate the output voltage again
after the junction temperature cools by 25oC. The OTP is
0
designed with a 25oC hysteresis to lower the average TJ
during continuous thermal overload conditions, which in-
Time
creases lifetime of the APW8728.
Figure 2. Current-Limit Algorithm
The PWM controller uses the low-side MOSFETs on-re-
Programming the On-Time Control and PWM Switching Frequency
sistance R DS(ON) to monitor the current for protection
against shortened outputs. The MOSFET’s RDS(ON) is varied by temperature and gate to source voltage, the user
should determine the maximum RDS(ON) in manufacture’s
The APW828 does not use a clock signal to produce PWM.
The device uses the constant-on-time control architec-
datasheet.
When LG is turned on, the OCSET pin can source 20µA
through an external resistor for adjusting current-limit
threshold. The voltage at OCSET pin is equal to
ture to produce pseudo-fixed frequency with input voltage
feed-forward. The on-time pulse width is proportional to
V PHASE+20µA x R OCSET. The relationship between the
sampled voltage VOCSET and the current-limit threshold
low :
output voltage VOUT and inverses proportional to input voltage VIN. In PWM, the on-time calculation is written as be-
 VOUT 
TON = 4 × 10 −12 × RTON 

 VIN 
ILIMIT is given by:
20µA x ROCSET = ILIMIT x RDS(ON)
Where:
RTON is the resistor connected from TON pin to PHASE
pin. Furthermore, the approximate PWM switching frequency is written as :
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Dec., 2012
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APW8728
Function Description (Cont.)
Programming the On-Time Control and PWM Switching Frequency (Cont.)
TON =
D
⇒ FSW =
FSW
VOUT
VIN
TON
Where:
FSW is the PWM switching frequency.
APW8728 doesn’t have VIN pin to calculate on-time pulse
width. Therefore, monitoring VTON voltage as input voltage
to calculate on-time. And then, use the relationship between ontime and duty cycle to obtain the switching
frequency. The curve below is the relationship between
RTON and the switching frequency FSW .
Romote Sense
APW8728 has a RTN pin for external mode applications
that require remote sense. In some applications where
high current, low voltage and accurate output voltage regulation are needed, RTN can sense the negative terminal
of remote load capacitor directly, and improve output voltage drop which is due to the board interconnection loss.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Dec., 2012
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APW8728
Application Information
Output Voltage Setting
saturation. In some types of inductors, especially core
The output voltage is adjustable from 0.6V to 3.3V with a
resistor-divider connected with FB, GND, and converter’s
that is made of ferrite, the ripple current will increase
abruptly when it saturates. This results in a larger output
output. The voltage (VREFIN) applied to REFIN pin selects
adjustable external reference from 0.5V to 2.5V. Using
ripple voltage. Besides, the inductor needs to have low
DCR to reduce the loss of efficiency.
1% or better resistors for the resistor-divider is
recommended. The output voltage is determined by:
Output Capacitor Selection
RTOP 

VOUT = 0.6 × 1 +

R
GND 

Output voltage ripple and the transient voltage deviation are factors which have to be taken into consideration when selecting an output capacitor. Higher capaci-
Where 0.6 is the reference voltage, RTOP is the resistor
connected from converter’s output to FB, and RGND is the
tor value and lower ESR reduce the output ripple and
the load transient drop. Therefore, selecting high per-
resistor connected from FB to GND. Suggested RGND is in
the range from 1k to 20kΩ. To prevent stray pickup, locate
formance low ESR capacitors is recommended for
switching regulator applications. In addition to high
resistors RTOP and RGND close to APW8728. Similarly,
when VREFIN is from 0.5V to 2.5V, the output voltage can be
frequency noise related to MOSFET turn-on and turnoff, the output voltage ripple includes the capacitance
programmed as same as VREFIN voltage.
Output Inductor Selection
The duty cycle (D) of a buck converter is the function of the
input voltage and output voltage. Once an output voltage
is fixed, it can be written as:
V
D = OUT
VIN
The inductor value (L) determines the inductor ripple
current, IRIPPLE, and affects the load transient reponse.
voltages can be represented by:
IRIPPLE
8COUTFSW
= IRIPPLE × RESR
∆VCOUT =
∆VESR
These two components constitute a large portion of the
total output voltage ripple. In some applications, multiple
capacitors have to be paralleled to achieve the desired
Higher inductor value reduces the inductor’s ripple current and induces lower output ripple voltage. The ripple
ESR value. If the output of the converter has to support
another load with high pulsating current, more capaci-
current and ripple voltage can be approximated by:
VIN - VOUT VOUT
×
VIN
FSW × L
is the switching frequency of the regulator.
IRIPPLE =
Where FSW
voltage drop ∆VCOUT and ESR voltage drop ∆VESR caused
by the AC peak-to-peak inductor’s current. These two
tors are needed in order to reduce the equivalent ESR
and suppress the voltage ripple to a tolerable level. A
Although the inductor value and frequency are increased
and the ripple current and voltage are reduced, a tradeoff
small decoupling capacitor (1µF) in parallel for bypassing the noise is also recommended, and the voltage rat-
exists between the inductor’s ripple current and the regulator load transient response time.
A smaller inductor will give the regulator a faster load
ing of the output capacitors are also must be considered.
To support a load transient that is faster than the switching frequency, more capacitors are needed for reducing
the voltage excursion during load step change. Another
transient response at the expense of higher ripple current.
Increasing the switching frequency (F SW ) also reduces
aspect of the capacitor selection is that the total AC current going through the capacitors has to be less than the
the ripple current and voltage, but it will increase the
switching loss of the MOSFETs and the power dissipa-
rated RMS current specified on the capacitors in order to
prevent the capacitor from over-heating.
tion of the converter. The maximum ripple current occurs
at the maximum input voltage. A good starting point is to
Input Capacitor Selection
choose the ripple current to be approximately 30% of the
maximum output current. Once the inductance value has
The input capacitor is chosen based on the voltage rating
and the RMS current rating. For reliable operation, select-
been chosen, selecting an inductor which is capable of
carrying the required peak current without going into
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Dec., 2012
ing the capacitor voltage rating to be at least 1.3 times
18
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APW8728
Application Information (Cont.)
2
Input Capacitor Selection (Cont.)
Phigh-side = IOUT (1+ TC)(RDS(ON))D + (0.5)( IOUT)(VIN)( tSW)FSW
higher than the maximum input voltage. The maximum
Plow-side = IOUT (1+ TC)(RDS(ON))(1-D)
RMS current rating requirement is approximately IOUT/2,
where IOUT is the load current. During power-up, the input
Where
I
is the load current
2
OUT
capacitors have to handle great amount of surge current.
For low-duty notebook appliactions, ceramic capacitor is
TC is the temperature dependency of RDS(ON)
FSW is the switching frequency
recommended. The capacitors must be connected between the drain of high-side MOSFET and the source of
tSW is the switching interval
D is the duty cycle
Note that both MOSFETs have conduction losses while
the high-side MOSFET includes an additional transition loss.
low-side MOSFET with very low-impeadance PCB layout.
MOSFET Selection
The application for a notebook battery with a maximum
The switching interval, tSW , is the function of the reverse
transfer capacitance CRSS. The (1+TC) term is a factor in
voltage of 24V, at least a minimum 30V MOSFETs should
be used. The design has to trade off the gate charge with
the temperature dependency of the RDS(ON) and can be
extracted from the “RDS(ON) vs. Temperature” curve of the
the RDS(ON) of the MOSFET:
For the low-side MOSFET, before it is turned on, the body
power MOSFET.
Layout Consideration
diode has been conducting. The low-side MOSFET driver
will not charge the miller capacitor of this MOSFET.
In any high switching frequency converter, a correct layout
In the turning off process of the low-side MOSFET, the
load current will shift to the body diode first. The high dv/
is important to ensure proper operation of the regulator.
With power devices switching at higher frequency, the
dt of the phase node voltage will charge the miller capacitor through the low-side MOSFET driver sinking current
resulting current transient will cause voltage spike across
the interconnecting impedance and parasitic circuit
path. This results in much less switching loss of the lowside MOSFETs. The duty cycle is often very small in high
elements. As an example, consider the turn-off transition
of the PWM MOSFET. Before turn-off condition, the
battery voltage applications, and the low-side MOSFET
will conduct most of the switching cycle; therefore, when
MOSFET is carrying the full load current. During turn-off,
current stops flowing in the MOSFET and is freewheeling
using smaller RDS(ON) of the low-side MOSFET, the converter can reduce power loss. The gate charge for this
by the low side MOSFET and parasitic diode. Any parasitic
inductance of the circuit generates a large voltage spike
MOSFET is usually the secondary consideration. The
high-side MOSFET does not have this zero voltage switch-
during the switching interval. In general, using short and
wide printed circuit traces should minimize interconnect-
ing condition; in addition, it conducts for less time compared to the low-side MOSFET, so the switching loss
ing impedances and the magnitude of voltage spike.
Besides, signal and power grounds are to be kept sepa-
tends to be dominant. Priority should be given to the
MOSFETs with less gate charge, so that both the gate
rating and finally combined using ground plane construction or single point grounding. The best tie-point between
driver loss and switching loss will be minimized.
The selection of the N-channel power MOSFETs are
the signal ground and the power ground is at the negative side of the output capacitor on each channel, where
determined by the R DS(ON), reversing transfer capacitance (CRSS) and maximum output current requirement.
there is less noise. Noisy traces beneath the IC are not
recommended. Below is a checklist for your layout:
The losses in the MOSFETs have two components:
conduction loss and transition loss. For the high-side
• Keep the switching nodes (UGATE, LGATE, BOOT,
and PHASE) away from sensitive small signal nodes
and low-side MOSFETs, the losses are approximately
given by the following equations:
since these nodes are fast moving signals.
Therefore, keep traces to these nodes as short as
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Dec., 2012
19
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APW8728
Application Information (Cont.)
Recommended Minimum Footprint
Layout Consideration (Cont.)
possible and there should be no other weak signal
3mm
traces in parallel with theses traces on any layer.
• The signals going through theses traces have both
high dv/dt and high di/dt with high peak charging and
discharging current. The traces from the gate drivers
to the MOSFETs (UGATE and LGATE) should be short
• Place the source of the high-side MOSFET and the
0.5mm *
0.24mm
drain of the low-side MOSFET as close as possible.
Minimizing the impedance with wide layout plane between the two pads reduces the voltage bounce of
0.5mm
the node. In addition, the large layout plane between
the drain of the MOSFETs (VIN and PHASE nodes) can
1.66 mm
and wide.
0.508mm
3mm
1.66mm
0.162mm
get better heat sinking.
• The PGND is the current sensing circuit reference
ground and also the power ground of the LGATE lowside MOSFET. On the other hand, the PGND trace
* Just Recommend
should be a separate trace and independently go to
the source of the low-side MOSFET. Besides, the current sense resistor should be close to OCSET pin to
avoid parasitic capacitor effect and noise coupling.
• Decoupling capacitors, the resistor-divider, and boot
capacitor should be close to their pins. (For example,
place the decoupling ceramic capacitor close to the
drain of the high-side MOSFET as close as possible.)
• The input bulk capacitors should be close to the drain
of the high-side MOSFET, and the output bulk capacitors should be close to the loads. The input capacitor’s ground should be close to the grounds of the
output capacitors and low-side MOSFET.
• Locate the resistor-divider close to the FB pin to minimize the high impedance trace. In addition, FB pin
traces can’t be close to the switching signal traces
(UGATE, LGATE, BOOT, and PHASE).
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Dec., 2012
20
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APW8728
Package Information
TQFN3x3-16
A
b
E
D
Pin 1
D2
A1
A3
L K
E2
Pin 1
Corner
e
S
Y
M
B
O
L
TQFN3x3-16
INCHES
MILLIMETERS
MIN.
MAX.
MIN.
MAX.
A
0.70
0.80
0.028
0.031
A1
0.00
0.05
0.000
0.002
A3
0.20 REF
0.008 REF
b
0.18
0.30
0.007
0.012
D
2.90
3.10
0.114
0.122
D2
1.50
1.80
0.059
0.071
E
2.90
3.10
0.114
0.122
E2
1.50
1.80
0.059
0.071
e
0.50 BSC
L
0.30
K
0.20
0.020 BSC
0.012
0.50
0.020
0.008
Note : Follow JEDEC MO-220 WEED-4.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Dec., 2012
21
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APW8728
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
A
OD1 B
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
TQFN3x3-16
A
H
T1
C
d
D
330±2.00
50 MIN.
12.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
P0
P1
P2
D0
D1
T
A0
B0
K0
2.0±0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
3.30±0.20
3.30±0.20
1.30±0.20
4.0±0.10
8.0±0.10
W
E1
12.0±0.30 1.75±0.10
F
5.5±0.05
(mm)
Devices Per Unit
Package Type
TQFN3x3-16
Unit
Tape & Reel
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Dec., 2012
Quantity
3000
22
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APW8728
Taping Direction Information
TQFN3x3-16
USER DIRECTION OF FEED
Classification Profile
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Dec., 2012
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APW8728
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
3 °C/second max.
3 °C/second max.
183 °C
60-150 seconds
217 °C
60-150 seconds
See Classification Temp in table 1
See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc)
20** seconds
30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
Liquidous temperature (TL)
Time at liquidous (tL)
Peak package body Temperature
(Tp)*
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Package
Thickness
<2.5 mm
≥2.5 mm
Volume mm
<350
235 °C
220 °C
3
Volume mm
≥350
220 °C
220 °C
3
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
1.6 mm – 2.5 mm
≥2.5 mm
Volume mm
<350
260 °C
260 °C
250 °C
3
Volume mm
350-2000
260 °C
250 °C
245 °C
3
Volume mm
>2000
260 °C
245 °C
245 °C
3
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TCT
HBM
MM
Latch-Up
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD-22, A115
JESD 78
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Dec., 2012
24
Description
5 Sec, 245°C
1000 Hrs, Bias @ Tj=125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV
VMM≧200V
10ms, 1tr≧100mA
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APW8728
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Dec., 2012
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