BELLING BL55077

zip: 200233
BL55077
Shanghai Belling Corp., Ltd
Tel: 86-021-64850700 Fax: 86-021-64855865
LCD Driver for 160 Display Units BL55077
1 General Description
The BL55077 is a general LCD driver IC for 160 units LCD panel. It features a wide
operating supply voltage range, incorporates simple communication interface with
microcomputer and is suitable for multiple application.
2 Features
Advanced low power CMOS Technology
Selection of 1/2 or 1/3 bias, selection of 1/2 or 1/3 or 1/4 duty.
Operation voltage: 2.5~5.5V
Serial data interface
160(40x4) Display Units
Low power dissipation design: Power saving mode: Idd=14uA at 5V and Idd=9uA at
3.3V; Sleeping mode: Idd<2uA
Maybe cascaded up to 16PCs for large LCD applications
On-chip RC oscillator
VLCD for adjusting LCD operating voltage
Excellent EMC immunity
Compatible with general microcomputer
3 Pin Assignment
Fig 1
1
4
Shanghai Belling Corp., Ltd
Tel: 86-021-64850700 Fax: 86-021-64855865
zip: 200233
BL55077
Pin Description
Pin No.
Pin name
Function
10
11
12
13
14
15
16-18
19
20
21
25-28
SDA
SCI
SYNC
CLK
Vdd
OSC
A0、A1、A2
SA0
Vss
Vlcd
Com0、Com2、Com1、Com3
29-32、
、34-37、
、49-64、
、2-7
1、
、8、
、9、
、22、
、23、
、24、
、33、
、48
S0——S39
NC
Serial data input/output
Serial clock input
Cascade synchronization clock
External clock input
Supply voltage
Oscillator input
Subaddress inputs
Slave address input;bit0
ground
LCD supply voltage
Common terminal driving
output
Segment terminal driving output
Unused
Tab.1
5
Function Description
1.function circuit
The BL550077 has all function circuits that can directly drive any static or multiplexed
LCD containing up to four commons and up to 40 segments. The function circuits
include:Power-on reset, LCD bias generator, LCD voltage selector, Oscillator, display RAM,
Timing, Display latch, Shift register, Common/segment outputs, input/output bank selector,
Blinker, Data pointer, Subaddress counter,etc.
2.display function decription
The display RAM is a static 40x 4-bit RAM which stores LCD data. A logic 1 in the
RAM bit-map indicates the on state of the corresponding LCD segment; similarly, a logic 0
indicates the off state. There is a one-to-one correspondence between the RAM addresses and
the segment outputs, and between the individual bits of a RAM word and the common
outputs. (see Fig.2).
Display RAM address and SEGMENT(
(S0~S39)
)output
0
COM
(Com0~
Com3)
输出
1
2
3
。
。
。
。
36
37
38
39
0
1
2
3
Fig2
When display data is transmitted to the BL55077, the display bytes received are stored
in the display RAM in accordance with the selected LCD drive mode. To illustrate the filling
order, an example of a 7-segment numeric display showing all drive modes is given in Fig.3;
the RAM filling organization depicted applies equally to other LCD types.
2
BL55077
zip: 200233
Shanghai Belling Corp., Ltd
Tel: 86-021-64850700 Fax: 86-021-64855865
Fig 3
I2C-bus protocol
Two I2C-bus slave addresses (0111000 and 0111001) are reserved for the BL55077.
The least significant bit of the slave address that a BL55077 will respond to is defined by the
level tied at its input SA0. Therefore, two types of BL55077 can be distinguished on the same
I2C-bus which allows:
1. Up to 16 BL55077 on the same I2C-bus for very large LCD applications.
2. The use of two types of LCD multiplex on the same I2C-bus.
The I2C-bus protocol is shown in Fig.4. The sequence is initiated with a START
condition (S) from the I2C-bus master which is followed by one of the two BL55077 slave
addresses available. All BL55077s with the corresponding SA0 level acknowledge in parallel
with the slave address but all BL55077s with the alternative SA0 level ignore the whole
I2C-bus transfer. After acknowledgement, one or more command bytes (m) follow which
define the status of the addressed BL55077s. The last command byte is tagged with a cleared
most significant bit, the continuation bit C. The command bytes are also acknowledged by all
addressed BL55077s on the bus. After the last command byte, a series of display data bytes(n)
may follow. These display bytes are stored in the display RAM at the address specified by the
data pointer and the subaddress counter. Both data pointer and subaddress counter are
automatically updated and the data is directed to the intended BL55077 device. The
acknowledgement after each byte is made only by the (A0, A1 and A2) addressed BL55077.
After the last display byte, the I2C-bus master issues a STOP condition (P).
3.
3
BL55077
zip: 200233
Shanghai Belling Corp., Ltd
Tel: 86-021-64850700 Fax: 86-021-64855865
Fig 4
4. command decoder
The command decoder identifies command bytes that arrive on the I2C-bus. All
available commands carry a continuation bit C in their most significant bit position. The five
commands available to the BL55077 are defined in Fig 5.
4
zip: 200233
BL55077
Shanghai Belling Corp., Ltd
Tel: 86-021-64850700 Fax: 86-021-64855865
Fig 5
6
Absolute Maximum Rating
Parameter
Symbol
Rating
Unit
Supply voltage
LCD operating voltage
Input voltage
Output voltage
Vdd,Vss,Vlcd current
Maximum power consumption
Operating temperature
Storage temperature
Vdd
Vlcd
Vi
Vo
Idd,Iss,Ilcd
Ptot
Topr
Tstg
-0.5~+6.0
0~ Vdd
Vss-0.5~Vdd+0.5
Vlcd-0.5~Vdd+0.5
-50~+50
400
-40~ +75
-65~ +150
V
V
V
V
mA
mW
o
C
o
C
7
DC Characteristic
Symbol Parameter
Vdd
Idd1
IC Operating
voltage
LCD operating
voltage
Supply current
Idd2
Supply current
Idd3
Supply current
Idd4
Supply current
Vlcd
ISL
Sleep current
Test Condition
Min
Vdd=5V,VLCD=0V,Normal
mode,internal oscillator
Vdd=5V,VLCD=0V,power saving
mode,internal oscillator
Vdd=3.3V,VLCD=0V,Normal
mode,internal oscillator
Vdd=3.3V,VLCD=0V,power saving
mode,internal oscillator
Vdd=5V,VLCD=0V
Typ
Max
Unit
2.5
-
5.5
V
0
-
Vdd-2
V
-
25
50
uA
-
14
30
uA
-
16
30
uA
-
9
15
uA
-
1.5
2
uA
ViL
Low voltage input
SDA,SCL
Vss
-
0.3Vdd
V
ViH
High voltage
input
Pull high resister
SDA,SCL
0.7Vdd
-
6.0
V
30
60
100
kΩ
Rph
SYNC
5
zip: 200233
BL55077
8
Shanghai Belling Corp., Ltd
Tel: 86-021-64850700 Fax: 86-021-64855865
Ta=25oC
AC Characteristic
Symbol Parameter
Test Condition
Min
Typ
Max
Unit
Fclk
Vdd=5V,normal mode
125
180
300
KHz
Vdd=3.3V, power saving
mode
21
31
48
KHz
1
-
3
uA
Tclk
Oscillator
frequency
Oscillator
frequency
Half oscillator cycle
Tsh1
CS start hold time
5
-
us
Tsh2
SCL start hold time
5
-
us
tlow
High time
5
-
us
thig
Low time
4
-
us
thd
SCL hold time
250
Fclk
Fig 6
9
Typical Application Circuit
Note:1/ when I2C are idle mode,SDA and SCL must be connect to high level(by pull up
resistor),otherwise the device maybe can not go into power saving mode.
2/
In power-saving mode, SCL frequency must be less than 21KHz.
3/
Work at 1/3 bias, Vdd – Vlcd must be more than 2.9V。
。
1/ single application
6
ns
BL55077
2/ cascade application
zip: 200233
Shanghai Belling Corp., Ltd
Tel: 86-021-64850700 Fax: 86-021-64855865
Fig 7
10
Unit
mm(tolerance)
Package Outline LQFP64
D
10.0(0.1)
E
12.0(0.15)
e
0.5
b
0.22(0.05)
7
f
1.25(0.2)
m
1.0
n
0.6(0.15)