NSC LM4934

LM4934
3D Audio Sub-System with Stereo Speaker, OCL/SE
Stereo Headphone, Earpiece and Mono Line Level
Outputs
General Description
Key Specifications
The LM4934 is an integrated audio sub-system designed for
stereo cell phone applications. Operating on a 3.3V supply, it
combines a stereo speaker amplifier delivering 520mW per
channel into an 8Ω load, a stereo headphone amplifier delivering 36mW per channel into a 32Ω load, a mono earpiece
amplifier delivering 55mW into a 32Ω load, and a line output
for an external powered handsfree speaker. It integrates the
audio amplifiers, volume control, mixer, power management
control, and National 3D enhancement all into a single package. In addition, the LM4934 routes and mixes the stereo
and mono inputs into multiple distinct output modes. The
LM4934 features an I2S serial interface for full range audio
and an I2C/SPI compatible interface for control.
Boomer audio power amplifiers are designed specifically to
provide high quality output power with a minimal amount of
external components.
j POUT, Stereo BTL, 8Ω, 3.3V,
1% THD+N
j POUT HP, 32Ω, 3.3V, 1% THD+N
520mW (typ)
36mW (typ)
j POUT Mono Earpiece, 32Ω, 3.3V,
1% THD+N
j Shutdown current
j DAC SNR
55mW (typ)
0.6µA (typ)
95dB (typ)
Features
n
n
n
n
n
n
n
n
n
n
n
18-bit stereo DAC
Multiple distinct output modes
Stereo speaker amplifier
Stereo headphone amplifier
Mono earpiece amplifier
Mono Line Output for external handsfree carkit
Independent Left, Right, headphone and Mono speaker
volume controls
National 3D enhancement with programmable effect
level
I2C/SPI (selectable) compatible interface
Ultra low shutdown current
Click and Pop Suppression circuit
Applications
n Cell Phones
n PDAs
Boomer ® is a registered trademark of National Semiconductor Corporation.
© 2006 National Semiconductor Corporation
DS201669
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LM4934 3D Audio Sub-System with Stereo Speaker, OCL/SE Stereo Headphone, Earpiece and
Mono Line Level Outputs
February 2006
LM4934
Block Diagram
20166949
FIGURE 1. Audio Sub-System Block Diagram with OCL HP Outputs
201669J7
FIGURE 2. Audio Sub-System with SE HP Outputs
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2
LM4934
Connection Diagrams
42-Bump Micro SMDxt
20166958
Top View (Bump Side Down)
Order Number LM4934RL
See NS Package Number RLA42
Top Marking Drawing
201669B7
Top View
XY — 2 Digit Date Code
TT — Traceability
G — Boomer Family
G9 — LM4934RL
I — Pin 1 Marking
Pin Descriptions
PIN
PIN NAME
D/A
I/O
DESCRIPTION
A1
DGND
D
P
DIGITAL GROUND
A2
MCLK
D
I
MASTER CLOCK
A3
I2S_WS
D
I/O
I2S WORD SELECT
A4
GPIO
D
O
TEST PIN (MUST BE LEFT FLOATING)
A5
ADDR/ENB
D
I
I2C_ADDR OR SPI_ENB DEPENDING ON I2C or SPI MODE SELECT
A6
DVDD
D
P
DIGITAL SUPPLY VOLTAGE
B1
PLLVDD
D
P
PLL SUPPLY VOLTAGE
B2
I2S_SDI
D
I
I2S SERIAL DATA INPUT
B3
I2S_CLK
D
I/O
I2S CLOCK SIGNAL
B4
MODE
D
I
SELECTS BETWEEN SPI AND I2C CONTROL INTERFACE
B5
I2C_VDD
D
P
I2C SUPPLY VOLTAGE
B6
VDDIO
D
P
I/O SUPPLY VOLTAGE
C1
PLL_IN
D
I
PLL FILTER INPUT
C2
PLL_OUT
D
O
PLL FILTER OUTPUT
C3
PLLGND
D
P
PLL GND
C4
SDA/SDI
D
I/O
I2C SDA OR SPI SDI
C5
SCL/SCK
D
I
I2C_SCL OR SPI_SCK
C6
AVDD
A
P
ANALOG SUPPLY VOLTAGE
3
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LM4934
Pin Descriptions
(Continued)
D1
AGND
A
P
ANALOG GROUND
D2
RIN
A
I
RIGHT ANALOG IN
D3
NC
A
D4
BYPASS
A
I
HALF-SUPPLY BYPASS
D5
LINEOUT
A
O
MONO LINE OUT
D6
RHP
A
O
RIGHT HEADPHONE OUTPUT
E1
EP-
A
O
MONO EARPIECE OUT-
E2
MIN
A
I
MONO ANALOG IN
E3
LIN
A
I
LEFT ANALOG IN
E4
R3DOUT
A
I
RIGHT CHANNEL 3D OUTPUT
E5
LHP
A
O
LEFT HEADPHONE OUTPUT
HEADPHONE CENTER PIN OUTPUT (1/2 VDD)
NO CONNECT
E6
CHP
A
O
F1
AGND
A
P
ANALOG GND
F2
EP+
A
O
MONO EARPIECE OUT+
F3
L3DIN
A
I
LEFT CHANNEL 3D INPUT
F4
L3DOUT
A
I
LEFT CHANNEL 3D OUTPUT
F5
R3DIN
A
I
RIGHT CHANNEL 3D INPUT
F6
AGND
A
P
ANALOG GND
G1
LLS-
A
O
LEFT SPEAKER OUT-
G2
AVDD
A
P
ANALOG SUPPLY VOLTAGE
G3
LLS+
A
O
LEFT SPEAKER OUT+
G4
RLS-
A
O
RIGHT SPEAKER OUT-
G5
AVDD
A
P
ANALOG SUPPLY VOLTAGE
G6
RLS+
A
O
RIGHT SPEAKER OUT+
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4
θJA (RLA42)
See AN-1279
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Analog Supply Voltage
6.0V
Digital Supply Voltage
6.0V
Storage Temperature
Operating Ratings
Temperature Range
TMIN ≤ TA ≤ TMAX
-65˚C to +150˚C
Power Dissipation (Note 3)
Internally Limited
ESD Susceptibility (Note 4)
2000V
ESD Susceptibility(Note 5)
200V
Junction Temperature
−40˚C ≤ TA ≤ +85˚C
Supply Voltage
-0.3V to VDD +0.3V
Input Voltage
61˚C/W
2.7V ≤ AVDD ≤ 5.5V
2.7V ≤ DVDD ≤ 4.0V
2.4V ≤ I2CVDD ≤ 4.0V
150˚C
Thermal Resistance
Audio Amplifier Electrical Characteristics AVDD = 3.0V, DVDD = 3.0V (Notes 1,
2)
The following specifications apply for the circuit shown in Figure 1 with all programmable gain set at 0dB, unless otherwise
specified. Limits apply for TA = 25˚C.
Symbol
IDD
ISD
PO
VFS DAC
THD+N
VOS
Parameter
Supply Current
Conditions
VIN = 0, No Load
All Amps On + DAC, OCL
18.5
26.5
Headphone Mode Only, OCL
5.6
8
mA (max)
Stereo Speaker Mode Only
12
19.5
mA (max)
Mono Speaker Mode Only
5.9
8
mA (max)
DAC Off, All Amps On, OCL
14.6
22
mA (max)
0.6
2
µA (max)
Speaker; THD = 1%;
f = 1kHz, 8Ω BTL
420
370
mW (min)
Headphone; THD = 1%;
f = 1kHz, 32Ω SE
27
24
Earpiece; THD = 1%;
f = 1kHz, 32Ω BTL
45
40
Full Scale DAC Output
Total Harmonic Distortion
Offset Voltage
Units
(Limits)
Limits
(Notes
7, 8)
Shutdown Current
Output Power
LM4934
Typical
(Note 6)
mA (max)
mW (min)
mW (min)
2.4
Vpp
Speaker; PO = 200mW;
f = 1kHz, 8Ω BTL
0.04
%
Headphone; PO = 10mW;
f = 1kHz, 32Ω SE
0.01
%
Earpiece; PO = 20mW;
f = 1kHz, 32Ω BTL
0.04
%
Line Out; VO = 1Vrms; f = 1kHz, 10kΩ SE
0.004
%
Speaker
8
55
mV (max)
Earpiece
8
50
mV (max)
HP (OCL)
8
40
mV
∈O
Output Noise
A = weighted; 0dB gain;
See Table 1
PSRR
Power Supply Rejection Ratio
f = 217Hz; Vripple = 200mVP-P
CB = 2.2µF; See Table 2
5
Table 1
Table 2
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LM4934
Absolute Maximum Ratings (Notes 1, 2)
LM4934
Audio Amplifier Electrical Characteristics AVDD = 3.0V, DVDD = 3.0V
(Notes 1,
2) (Continued)
The following specifications apply for the circuit shown in Figure 1 with all programmable gain set at 0dB, unless otherwise
specified. Limits apply for TA = 25˚C.
Symbol
Parameter
Conditions
LM4934
Typical
(Note 6)
Xtalk
TWU
Crosstalk
Wake-Up Time
Limits
(Notes
7, 8)
Units
(Limits)
Loudspeaker; PO= 200mW
f = 1kHz
–84
dB
Headphone; PO= 10mW
f = 1kHz; SE
–85
dB
Headphone; PO= 10mW
f = 1kHz; OCL
–60
dB
CB = 2.2µF, CD6 = 0
35
ms
CB = 2.2µF, CD6 = 1
85
ms
Audio Amplifier Electrical Characteristics AVDD = 5.0V, DVDD = 3.3V
(Notes 1,
2)
The following specifications apply for the circuit shown in Figure 1 with all programmable gain set at 0dB, unless otherwise
specified. Limits apply for TA = 25˚C.
Symbol
Parameter
Conditions
LM4934
Typical
(Note 6)
IDD
ISD
PO
VFS DAC
THD+N
VOS
∈O
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Supply Current
24
Headphone Mode Only
5.8
mA
Stereo Speaker Mode Only
17
mA
Mono Speaker Mode Only
7
mA
DAC Off, All Amps On
19
mA
1.6
µA
Speaker; THD = 1%;
f = 1kHz, 8Ω BTL
1.2
W
Headphone; THD = 1%;
f = 1kHz, 32Ω SE
80
Earpiece; THD = 1%;
f = 1kHz, 32Ω BTL
175
Full Scale DAC Output
Total Harmonic Distortion
Offset Voltage
Output Noise
Units
(Limits)
VIN = 0, No Load
All Amps On - DAC
Shutdown Current
Output Power
Limits
(Notes
7, 8)
mA (max)
mW
mW
2.4
Vpp
Speaker; PO = 500mW;
f = 1kHz, 8Ω BTL
0.03
%
Headphone; PO = 30mW;
f = 1kHz, 32Ω SE
0.01
%
Earpiece; PO = 40mW;
f = 1kHz, 32Ω BTL; CD4 = 0
0.04
%
Line Out; VO = 1Vrms; f = 1kHz, 10kΩ SE
0.003
%
Speaker
8
mV
Earpiece
8
mV
HP (OCL)
8
mV
A = weighted; 0dB gain;
See Table 1
6
Table 1
(Notes 1,
2) (Continued)
The following specifications apply for the circuit shown in Figure 1 with all programmable gain set at 0dB, unless otherwise
specified. Limits apply for TA = 25˚C.
Symbol
Parameter
Conditions
LM4934
Typical
(Note 6)
PSRR
Xtalk
TWU
Power Supply Rejection Ratio
Crosstalk
Wake-Up Time
f = 217Hz; Vripple = 200mVP-P
CB = 2.2µF; See Table 3
Limits
(Notes
7, 8)
Units
(Limits)
Table 3
Loudspeaker; PO= 400mW
f = 1kHz
–86
dB
Headphone; PO= 15mW
f = 1kHz; OCL
–56
dB
Headphone; PO= 15mW
f = 1kHz, SE
–80
dB
CB = 2.2µF, CD6 = 0
45
ms
CB = 2.2µF, CD6 = 1
130
ms
Volume Control Electrical Characteristics (Notes 1, 2)
The following specifications apply for 3V ≤ AVDD ≤ 5V and 2.7V ≤ DVDD ≤ 4.0V, unless otherwise specified. Limits apply for TA
= 25˚C.
Symbol
Parameter
Conditions
LM4934
Typical
(Note 6)
PGR
VCR
∆ACH-CH
AMUTE
Stereo or Mono Analog Inputs
PreAmp Gain Setting Range
Output Volume Control for Stereo
Speakers, Headphone Output, or
Mono Output Range
minimum gain setting
–6
maximum gain setting
15
minimum gain setting, Vol = 00001
–56
maximum gain setting
Stereo Channel to Channel Gain
Mismatch
Mute Attenuation
Units
(Limits)
–6.5
dB (min)
–5.5
dB (max)
15.5
dB (max)
14.5
dB (min)
–56.5
dB (min)
–55.5
dB (max)
4.5
dB (min)
5.5
dB (max)
0.3
dB
< -90
< -90
dB
Vin = 1Vrms, Gain = 0dB
with load, Vol = 00000
Headphone
Line Out
RINPUT
5
Limits
(Notes
7, 8)
MIN, LIN and RIN Input Impedance
23
7
dB
18
kΩ (min)
28
kΩ (max)
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LM4934
Audio Amplifier Electrical Characteristics AVDD = 5.0V, DVDD = 3.3V
LM4934
Digital Section Electrical Characteristics (Notes 1, 2)
The following specifications apply for 3V ≤ AVDD ≤ 5V and 2.7V ≤ DVDD ≤ 4.0V, unless otherwise specified. Limits apply for TA
= 25˚C.
Symbol
DISD
Parameter
Digital Shutdown Current
DIDD
Digital Power Supply Current
PLLIDD
PLL Quiescent Current
Conditions
LM4934
Units
(Limits)
Typical
(Note 6)
Limits
(Notes
7, 8)
0.01
1
µA
ALL MODES EXCEPT 0
5.3
8
mA
fMCLK = 12MHz, DVDD = 3.0V
4.8
6
mA
Mode 0, DVDD = 3.0V
No MCLK
fMCLK = 12MHz, DVDD = 3.0V
Audio DAC (Typical numbers are with 6.144MHz audio clock and 48kHz sampling frequency
RDAC
Audio DAC Ripple
20Hz - 20kHz through headphone output
PBDAC
Audio DAC Passband width
-3dB point
SBADAC
Audio DAC Stop band Attenuation
Above 24kHz
Audio DAC Dynamic Range
DC - 20kHz, –60dBFS; AES17 Standard
See Table 4
Audio DAC-AMP Signal to Noise
Ratio
A-Weighted, Signal = VO at 0dBFS, f =
1kHz
Noise = digital zero, A-weighted, See
Table 4
Internal DAC SNR
A-weighted (Note 10)
DRDAC
SNR
SNRDAC
+/-0.1
dB
22.6
kHz
76
dB
Table 4
dB
Table 4
dB
95
dB
PLL
fIN
Input Frequency on MCLK pin
12
10
26
MHz
SPI/I2C
fSPI
Maximum SPI Frequency
4000
kHz (max)
tSPISETD
SPI Data Setup Time
100
ns (max)
tSPISETENB
SPI ENB Setup Time
100
ns (max)
tSPIHOLDD
SPI Data Hold Time
100
ns (max)
tSPIHOLDENB
SPI ENB Hold Time
100
ns (max)
tSPICL
SPI Clock Low Time
125
ns (max)
tSPICH
SPI Clock High Time
125
ns (max)
fCLKI2C
I2C_CLK Frequency
400
kHz (max)
tI2CHOLD
I2C_DATA Hold Time
100
ns (max)
100
ns (max)
tI2CSET
VIH
VIL
2
I C_DATA Setup Time
I2C/SPI Input High Voltage
I2CVDD
I2C/SPI Input Low Voltage
0
0.7 x
I2CVDD
V (min)
0.3 x
I2CVDD
V (max)
I2S
fCLKI2S
I2S_RES = 0
1536
6144
I2S_RES = 1
3072
12288
50
40
%
Digital Input High Voltage
0.7 x
DVDD
V (min)
Digital Input Low Voltage
0.3 x
DVDD
V (max)
I2S_CLK Frequency
I2S_WS Duty Cycle
VIH
VIL
Note 1: All voltages are measured with respect to the GND pin unless otherwise specified.
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8
kHz (max)
Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX ,θJA, and the ambient temperature, TA. The maximum
allowable power dissipation is PDMAX = (TJMAX – TA) / θ JA or the number given in Absolute Maximum Ratings, whichever is lower.
Note 4: Human body model: 100pF discharged through a 1.5kΩ resistor.
Note 5: Machine model: 220pF - 240pF discharged through all pins.
Note 6: Typicals are measured at 25˚C and represent the parametric norm.
Note 7: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 8: Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.
Note 9: Shutdown current is measured in a normal room environment.
Note 10: Internal DAC only with DAC modes 00 and 01.
TABLE 1. Output Noise
Output Noise AVDD = 5V and AVDD = 3V. All gains set to 0dB. Units in µV. A - weighted
MODE
EP
LS
HP OCL or SE
Lineout
Units
1
22
22
11
9
µV
2
22
22
11
9
µV
3
22
22
11
9
µV
4
68
88
46
35
µV
5
38
48
24
20
µV
6
29
34
18
15
µV
7
38
48
24
20
µV
TABLE 2. PSRR AVDD = 3V
PSRR AVDD = 3V. f = 217Hz; Vripple = 200mVp-p; CB = 2.2µF.
MODE
EP
(Typ)
LS
(Typ)
1
69
71
2
69
71
3
69
71
4
63
5
69
6
7
LS
(Limit)
HP OCL or
SE
(Typ)
HP OCL or
SE
(Limit)
Lineout
(Typ)
Units
70
dB
72
67
72
68
70
dB
72
70
dB
62
55
68
dB
68
61
69
dB
69
70
64
70
dB
69
68
61
69
dB
TABLE 3. PSRR AVDD = 5V
PSRR AVDD = 5V. All gains set to 0dB. f = 217Hz; Vripple = 200mVp-p; CB = 2.2µF
MODE
EP
(Typ)
LS
(Typ)
HP OCL or SE
(Typ)
Lineout
(Typ)
Units
1
68
72
71
70
dB
2
68
72
71
70
dB
3
68
72
71
70
dB
4
68
66
69
70
dB
5
68
69
70
70
dB
6
69
72
71
71
dB
7
68
69
70
70
dB
TABLE 4. Dynamic Range and SNR
Dynamic Range and SNR. 3V ≤ AVDD ≤ 5V. All programmable gain set to 0dB. Units in dB.
DR (Typ)
SNR (Typ)
Units
LS
95
85
dB
Lineout
100
87
dB
9
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LM4934
Note 2: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which
guarantee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit
is given, however, the typical value is a good indication of device performance.
LM4934
TABLE 4. Dynamic Range and SNR (Continued)
Dynamic Range and SNR. 3V ≤ AVDD ≤ 5V. All programmable gain set to 0dB. Units in dB.
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DR (Typ)
SNR (Typ)
Units
HP
95
85
dB
EP
97
87
dB
10
The LM4934 is controlled via either a three wire SPI or a two wire I2C compatible interface, selectable with the MODE pin. When
MODE is cleared the device is in I2C mode, when MODE is set the device is in SPI mode. This interface is used to configure the
operating mode, interfaces, data converters, mixers and amplifiers. The LM4934 is controlled by writing 8 bit data into a series
of write-only registers, the device is always a slave for both type of interfaces.
THREE WIRE, SPI INTERFACE (MODE = 1)
Three Wire Mode Write Bus Transaction
20166959
Three Wire Mode Write Bus Timing
20166960
FIGURE 3. Three Wire Mode Write Bus
When the part is configured as an SPI device and the enable (ENB) line is lowered the serial data on SDI is clocked in on the
rising edge of the SCK line. The protocol used is 16bit, MSB first. The upper 8 bits (15:8) are used to select an address within
the device, the lower 8 bits (7:0) contain the updated data for this register.
TWO WIRE I2C COMPATIBLE INTERFACE (MODE = 0)
Two Wire Mode Write Bus Transaction
201669J6
Two Wire Mode Write Bus Timing
20166962
FIGURE 4. Two Wire Mode Write Bus
11
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LM4934
System Control
LM4934
System Control
(Continued)
When the part is configured as an I2C device then the LM4934 will respond to one of two addresses, according to the ADDR input.
If ADDR is low then the address portion of the I2C transaction should be set to write to 0010000. When ADDR is high then the
address input should be set to write to 1110000.
TABLE 5. Chip Address
A6
A5
A4
A3
A2
A1
A0
Chip Address
EC
EC
1
0
0
0
0
ADR = 0
0
0
1
0
0
0
0
ADR = 1
1
1
1
0
0
0
0
EC — Externally configured by ADR pin
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12
Mono Volume Control 0
Loud Speaker
LeftVolume and 3D
Gain
Loud Speaker
RightVolume and 3D
Control
Headphone Left
Volume Control
Headphone Right
Volume Control
Analog R & L Input
Gain Control
Analog Mono & DAC 0
Input Gain Control
Clock Configu
ration
PLL M Divider
PLL N Divider
PLL N_MOD Divider
and Dither Level
PLL_P Divider
DAC Setup
Interface
COMPENSATION _C COMP0_7
OEFF0_LSB
COMPENSATION _C COMP0_15 COMP0_14
OEFF0_MSB
COMPENSATION _C COMP1_7
OEFF1_LSB
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
PLL_N_6
PLL_M_6
R_DIV_2
DIG_R_
GAIN_1
0
0
0
3D_MODE
3D_LEVEL_1
0
0
0
0
0
COMP1_6
COMP0_6
0
CUST_COMP
0
VCO_FAST PLL_DITH_LEV_1
PLL_N_7
0
R_DIV_3
0
0
0
0
0
0
CD_6
Output Control
D6
01h
0
Mode Control
D7
Register
00h
(Continued)
Address
System Control
COMP1_5
COMP0_13
COMP0_5
0
DITHER_ALW_ON
0
PLL_DITH_LEV_0
PLL_N_5
PLL_M_5
R_DIV_1
DIG_R_
GAIN_0
ANA_R_
GAIN_2
0
0
3D_ENABLE
3D_LEVEL_0
0
HP_R_
OUTPUT
0
D5
COMP1_4
COMP0_12
COMP0_4
0
DITHER_OFF
0
PLL_N_MOD_4
PLL_N_4
PLL_M_4
R_DIV_0
DIG_L_
GAIN_1
ANA_R_
GAIN_1
HP_R_VOL_4
HP_L_VOL_4
LS_R_VOL_4
LS_L_VOL_4
MONO_VOL_4
HP_L_
OUTPUT
OCL
D4
TABLE 6. Control Registers
LS_L_
OUTPUT
CD_2
D2
PLL_N_2
PLL_M_2
AUDIO
_CLK_SEL
MONO_IN_
GAIN_2
ANA_L_
GAIN_2
HP_R_VOL_2
HP_L_VOL_2
LS_R_VOL_2
LS_L_VOL_2
COMP1_3
COMP0_11
COMP0_3
I2C_FAST
MUTE_R
PLL_P_3
COMP1_2
COMP0_10
COMP0_2
I2S_MODE
MUTE_L
PLL_P_2
PLL_N_MOD_3 PLL_N_MOD_2
PLL_N_3
PLL_M_3
PLL_
ENABLE
DIG_L_
GAIN_0
ANA_R_
GAIN_0
HP_R_VOL_3
HP_L_VOL_3
LS_R_VOL_3
LS_L_VOL_3
MONO_VOL_3 MONO_VOL_2
LS_R_
OUTPUT
CD_3
D3
D0
LINEOUT_
OUTPUT
CD_0
PLL_N_0
PLL_M_0
FAST_
CLOCK
MONO_IN_
GAIN_0
ANA_L
_GAIN_0
HP_R_VOL_0
HP_L_VOL_0
LS_R_VOL_0
LS_L_VOL_0
PLL_P_0
COMP1_1
COMP0_9
COMP0_1
I2S_RESOL
COMP1_0
COMP0_8
COMP0_0
I2S_M/S
DAC_MODE_1 DAC_MODE_0
PLL_P_1
PLL_N_MOD_1 PLL_N_MOD_0
PLL_N_1
PLL_M_1
PLL_INPUT
MONO_IN_
GAIN_1
ANA_L
_GAIN_1
HP_R_VOL_1
HP_L_VOL_1
LS_R_VOL_1
LS_L_VOL_1
MONO_VOL_1 MONO_VOL_0
MONO_
OUTPUT
CD_1
D1
LM4934
13
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14
COMPENSATION _C COMP2_7
OEFF2_LSB
COMPENSATION _C COMP2_15 COMP2_14
OEFF2_MSB
TEST_
REGISTER
14h
15h
16h
Note: All registers default to 0 on initial power-up.
RESERVED RESERVED
COMP2_6
COMPENSATION _C COMP1_15 COMP1_14
OEFF1_MSB
D6
13h
D7
Register
(Continued)
Address
System Control
RESERVED
COMP2_13
COMP2_5
COMP1_13
RESERVED
COMP2_12
COMP2_4
COMP1_12
D4
RESERVED
COMP2_11
COMP2_3
COMP1_11
D3
TABLE 6. Control Registers (Continued)
D5
RESERVED
COMP2_10
COMP2_2
COMP1_10
D2
RESERVED
COMP2_9
COMP2_1
COMP1_9
D1
RESERVED
COMP2_8
COMP2_0
COMP1_8
D0
LM4934
LM4934
System Controls
TABLE 7. Stereo or Mono, Left or Right Volume Control
MONO_VOL_4,
LS_L_VOL_4,
LS_R_VOL_4,
HP_L_VOL_4,
HP_R_VOL_4
MONO_VOL_3,
LS_L_VOL_3,
LS_R_VOL_3,
HP_L_VOL_3,
HP_R_VOL_3
MONO_VOL_2,
LS_L_VOL_2,
LS_R_VOL_2,
HP_L_VOL_2,
HP_R_VOL_2
MONO_VOL_1,
LS_L_VOL_1,
LS_R_VOL_1,
HP_L_VOL_1,
HP_R_VOL_1
MONO_VOL_0,
LS_L_VOL_0,
LS_R_VOL_0,
HP_L_VOL_0,
HP_R_VOL_0
Gain (dB)
0
0
0
0
0
Mute
0
0
0
0
1
–56
0
0
0
1
0
–52
0
0
0
1
1
–48
0
0
1
0
0
–45
0
0
1
0
1
–42
0
0
1
1
0
–39
0
0
1
1
1
–36
0
1
0
0
0
–33
0
1
0
0
1
–30
0
1
0
1
0
–28
0
1
0
1
1
–26
0
1
1
0
0
–24
0
1
1
0
1
–22
0
1
1
1
0
–20
0
1
1
1
1
–18
1
0
0
0
0
–16
1
0
0
0
1
–14
1
0
0
1
0
–12
1
0
0
1
1
–10
1
0
1
0
0
–8
1
0
1
0
1
–6
1
0
1
1
0
–4
1
0
1
1
1
–3
1
1
0
0
0
–2
1
1
0
0
1
–1
1
1
0
1
0
0
1
1
0
1
1
+1
1
1
1
0
0
+2
1
1
1
0
1
+3
1
1
1
1
0
+4
1
1
1
1
1
+5
15
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LM4934
System Controls
(Continued)
TABLE 8. Mixer Code Control
Mode
CD3
CD2
CD1
CD0
Mono
Lineout
Mono
Earpiece
0
0
0
0
0
SD
SD
SD
SD
SD
SD
1
1
0
0
1
M
M
M
M
M
M
2
1
0
1
0
AL+AR
AL+AR
AL
AR
AL
AR
3
1
0
1
1
M+AL+AR
M+AL+AR
M+AL
M+AR
M+AL
M+AR
4
1
1
0
0
DL+DR
DL+DR
DL
DR
DL
DR
5
1
1
0
1
DL+DR+
AL+AR
DL+DR+
AL+AR
DL+AL
DR+AR
DL+AL
DR+AR
6
1
1
1
0
M+DL+AL+
DR+AR
M+DL+AL+ M+DL+AL M+DR+AR M+DL+AL
DR+AR
7
1
1
1
1
M+DL+DR
M+DL+DR
SD — Shutdown
M — Mono Input
AL — Analog Left Channel
AR — Analog Right Channel
DL — I2S DAC Left Channel
DR — I2S DAC Right Channel
MUTE — Mute
Note: Power-On Default Mode is Mode 0
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16
LoudLoud- Headphone
Speaker L Speaker R
L
M+DL
M+DR
M+DL
Headphone
R
M+DR+AR
M+DR
LM4934
System Controls
(Continued)
TABLE 9. Output Control (01h)
Loudspeaker Left Channel
Loudspeaker Right Channel
Headphone Left Channel
LS_L_OUTPUT = 1
LS_L_OUTPUT = 0
Output On
Output Off
LS_R_OUTPUT = 1
LS_R_OUTPUT = 0
Output On
Output Off
HP_L_OUTPUT = 1
HP_L_OUTPUT = 0
Output On
OCL = 1, Output Mute
HP_R_OUTPUT = 1
Headphone Right Channel
HP_R_OUTPUT = 0
Output On
Mono Speaker Output
Lineout
Headphone Output Mode
All Outputs
OCL = 0, Output Mute
OCL = 1, Output Mute
OCL = 0, Output Mute
MONO_OUTPUT = 1
MONO_OUTPUT = 0
Output On
Output Off
LINEOUT_OUTPUT = 1
LINEOUT_OUTPUT = 0
Output On
Output Mute
OCL = 1
OCL = 0
Headphone Output set to Capless
(CHP = 1/2 AVDD)
Headphone Output Set to Cap-coupled
CD3 = 1
CD3 = 0
Outputs Toggled Via Register Control
All Outputs Off
TABLE 10. National 3D Enhancement Level Select (03h)
3D_LEVEL_1
3D_LEVEL_0
MIX RATIO
0
0
25%
0
1
40%
1
0
55%
1
1
70%
TABLE 11. National 3D Mode Control (04h)
3D_MODE
MODE
0
3D type 1
1
3D type 2
3D type 1: ROUT = Ri - G * LOUT3D, LOUT = Li - G * ROUT3D
3D type 2: ROUT = −Ri - G * LOUT3D, LOUT = Li + G * ROUT3D
Ri = Right Input
Li = Left Input
G = 3D gain level (Mix Ratio)
ROUT3D = Ri through the high-pass filter R3D and C3D
LOUT3D = Li through the high-pass filter R3D and C3D
17
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LM4934
System Controls
(Continued)
TABLE 12. Analog Input Amplifier Gain Select
MONO_IN_GAIN_2
ANA_L_GAIN_2
ANA_R_GAIN_2
MONO_IN_GAIN_1
ANA_L_GAIN_1
ANA_R_GAIN_1
MONO_IN_GAIN_0
ANA_L_GAIN_0
ANA_R_GAIN_0
Input Gain Setting
0
0
0
–6dB
0
0
1
–3dB
0
1
0
0dB
0
1
1
3dB
1
0
0
6dB
1
0
1
9dB
1
1
0
12dB
1
1
1
15dB
TABLE 13. DAC Gain Select
DIG_L_GAIN_1
DIG_R_GAIN_1
DIG_L_GAIN_1
DIG_R_GAIN_1
Input Gain Setting
0
0
–3dB
0
1
0dB
1
0
3dB
1
1
6dB
PLL Configuration Registers
PLL M DIVIDER CONFIGURATION REGISTER
This register is used to control the input divider of the PLL.
PLL_M (0Ah) (Set = logic 1, Clear = logic 0)
Bits
Register
Description
6:0
PLL_M
Programs the PLL input divider to select:
PLL_M
Divide Ratio
0
Divider Off
1
1
2
1.5
3
2
4
...
2.5
3→
126
63.5
127
64
NOTES:
The M divider should be set such that the output of the divider is between 0.5 and 5MHz. See the PLL setup section for details.
The divider of the M divider is derived from PLL_M as such:
M = (PLL_M+1) / 2
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18
LM4934
PLL Configuration Registers
(Continued)
PLL N DIVIDER CONFIGURATION REGISTER
This register is used to control PLL N divider.
PLL_N (0Bh) (Set = logic 1, Clear = logic 0)
Bits
Register
Description
7:0
PLL_N
Programs the PLL feedback divider:
PLL_N
Divide Ratio
0
1 → 10
Divider Off
11
11
12
12
10
...
...
248
248
249
250 → 255
249
250
NOTES:
The divider should be set such that the output of the divider is between 0.5 and 5MHz. See the PLL setup section for details. The N divider should never be set so
that (Fin/M) * N > 55MHz (or 80MHz if FAST_VCO is set in the PLL_N_MOD register).
The non-sigma-delta division of the N divider is derived from the PLL_N as such:
N = PLL_N
Fin /M is often referred to as Fcomp (Frequency of Comparison) or Fref (Reference Frequency). In this document, Fcomp is used.
PLL P DIVIDER CONFIGURATION REGISTER
This register is used to control the PLL’s P divider.
PLL_P (0Dh) (Set = logic 1, Clear = logic 0)
Bits
Register
Description
3:0
PLL_P
Programs the PLL input divider to select:
PLL_P
Divide Ratio
0
Divider Off
1
1
2
1.5
3
2
...
– > 2.5
13
7
14
7.5
15
8
NOTES:
The division of the P divider is derived from PLL_P as such:
P = (PLL_P+1) / 2
19
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LM4934
PLL Configuration Registers
(Continued)
PLL N MODULATOR AND DITHER SELECT CONFIGURATION REGISTER
This register is used to control the Fractional component of the PLL.
PLL_N_MOD (0Ch) (Set = logic 1, Clear = logic 0)
Bits
Register
Description
4:0
PLL_N_MOD
This programs the PLL N Modulator’s fractional component:
6:5
7
DITHER_LEVEL
FAST_VCO
PLL_N_MOD
Fractional Addition
0
0/32
1
→
2
30
1/32
2/32 → 30/32
31
31/32
Allows control over the dither used by the N Modulator
DITHER_LEVEL
DAC Sub-system Input Source
00
Medium (32)
01
Small (16)
10
Large (48)
11
Off
If set the VCO maximum and minimum frequencies are raised:
FAST_VCO
Maximum FVCO
0
40–55MHz
1
55–80MHz
NOTES:
The complete N divider is a fractional divider as such:
N = PLL_N + (PLL_N_MOD/32)
If the modulus input is zero, then the N divider is simply an integer N divider. The output from the PLL is determined by the following formula:
Fout = (Fin * N) / (M * P)
Please see over for more details on the PLL and common settings.
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20
The sigma-delta PLL is designed to drive audio circuits requiring accurate clock frequencies of up to 25MHz with frequency errors
noise-shaped away from the audio band. The 5 bits of modulus control provide exact synchronization of 48kHz and 44.1kHz
sample rates from any common clock source when the oversampling rate of the audio system is 125fs. In systems where 128x
oversampling must be used (for example with an isochronous I2S data stream) a clock synchronous to the sample rate should
be used as input to the PLL (typically the I2S clock). If no isochronous source is available then the PLL can be used to obtain a
clock that is accurate to within typical crystal tolerances of the real sample rate.
20166963
Example Of Pll Settings For 48Khz Sample Rates
f_in (MHz)
fsamp (kHz)
M
N
P
PLL_M
PLL_N
PLL_N_MOD
PLL_P
f_out (MHz)
11
48
11
60
5
21
60
0
9
12
12
48
5
25
5
9
25
0
9
12
12.288
48
4
19.53125
5
7
19
17
9
12
13
48
13
60
5
25
60
0
9
12
14.4
48
9
37.5
5
17
37
16
9
12
16.2
48
27
100
5
53
100
0
9
12
16.8
48
14
50
5
27
50
0
9
12
19.2
48
13
40.625
5
25
40
20
9
12
19.44
48
27
100
6
53
100
0
11
12
19.68
48
20.5
62.5
5
40
62
16
9
12
19.8
48
16.5
50
5
32
50
0
9
12
Example Pll Settings For 44.1Khz Sample Rates
f_in (MHz)
fsamp (kHz)
11
44.1
11
M
55.125
N
P
PLL_M
PLL_N
PLL_N_MOD
PLL_P
f_out (MHz)
5
21
55
4
9
11.025000
11.2896
44.1
8
39.0625
5
15
39
2
9
11.025000
12
44.1
5
22.96875
5
9
22
31
9
11.025000
13
44.1
13
55.125
5
25
55
4
9
11.025000
14.4
44.1
12
45.9375
5
23
45
30
9
11.025000
16.2
44.1
9
30.625
5
17
30
20
9
11.025000
16.8
44.1
17
55.78125
5
33
55
25
9
11.025000
19.2
44.1
16
45.9375
5
31
45
30
9
11.025000
19.44
44.1
13.5
38.28125
5
26
38
9
9
11.025000
19.68
44.1
20.5
45.9375
4
40
45
30
7
11.025000
19.8
44.1
11
30.625
5
21
30
20
9
11.025000
These tables cover the most common applications, obtaining clocks for sample rates such as 22.05kHz and 192kHz should be
done by changing the P divider value or the R divider in the clock configuration diagram.
If the user needs to obtain a clock unrelated to those described above, the following method is advised. An example of obtaining
11.2896 from 12.000MHz is shown below.
21
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LM4934
Further Notes on PLL Programming
LM4934
Further Notes on PLL Programming
(Continued)
Choose a small range of P so that the VCO frequency is swept between 45 and 55MHz (or 60-80MHz if VCOFAST is used).
Remembering that the P divider can divide by half integers. So for P = 4.0 → 7.0 sweep the M inputs from 2.5 → 24. The most
accurate N and N_MOD can be calculated by:
N = FLOOR(((Fout/Fin)*(P*M)),1)
N_MOD = ROUND(32*((((Fout)/Fin)*(P*M)-N),0)
This shows that setting M = 11.5, N = 75 N_MOD = 47 P = 7 gives a comparison frequency of just over 1MHz, a VCO frequency
of just under 80MHz (so VCO_FAST must be set) and an output frequency of 11.289596 which gives a sample rate of
44.099985443kHz, or accurate to 0.33 ppm.
Care must be taken when synchronization of isochronous data is not possible, i.e. when the PLL has to be used in the above
mode. The I2S should be master on the LM4934 so that the data source can support appropriate SRC as required. This method
should only be used with data being read on demand to eliminate sample rate mismatch problems.
Where a system clock exists at an integer multiple of the required DAC clock rate it is preferable to use this rather than the PLL.
The LM4934 is designed to work in 8,12,16,24,32, and 48kHz modes from a 12MHz clock without the use of the PLL. This saves
power and reduces clock jitter.
Clock Configuration Register
This register is used to control the multiplexers and clock R divider in the clock module.
CLOCK (09h) (Set = logic 1, Clear = logic 0)
Bits
Register
0
FAST_CLOCK
1
Description
If set master clock is divided by two.
FAST_CLOCK
MCLK Frequency
0
Normal
1
Divided by 2
PLL_INPUT
Programs the PLL input multiplexer to select:
PLL_INPUT
PLL Input Source
0
MCLK
1
I2S Input Clock
Selects which clock is passed to the audio sub-system
DAC_CLK_SEL
2
AUDIO_CLK_SEL
DAC Sub-system
Input Source
0
PLL Input
1
PLL Output
3
PLL_ENABLE
If set enables the PLL. (MODES 4–7 only)
7:4
R_DIV
Programs the R divider
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R_DIV
Divide Value
0000
1
0001
1
0010
1.5
22
0011
2
0100
2.5
0101
3
0110
3.5
0111
4
1000
4.5
1001
5
1010
5.5
1011
6
1100
6.5
1101
7
1110
7.5
1111
8
LM4934
Clock Configuration Register
(Continued)
20166953
By default the stereo DAC operates at 250*fs, i.e. 12.000MHz (at the clock generator input clock) for 48kHz data. It is expected
that the PLL be used to drive the audio system unless a 12.000MHz master clock is supplied. The PLL can also use the I2S clock
input as a source. In this case, the audio DAC uses the clock from the output of the PLL.
Common Clock Settings for the DAC
The DAC can work in 4 modes, each with different oversampling rates, 125,128,64 & 32. In normal operation 125x oversampling
provides for the simplest clocking solution as it will work from 12.000MHz (common in most systems with Bluetooth or USB) at
48kHz exactly. The other modes are useful if data is being provided to the DAC from an uncontrollable isochronous source (such
as a CD player, DAB, or other external digital source) rather than being decoded from memory. In this case the PLL can be used
to derive a clock for the DAC from the I2S clock.
The DAC oversampling rate can be changed to allow simpler clocking strategies, this is controlled in the DAC SETUP register but
the oversampling rates are as follows:
DAC MODE
Oversampling Ratio Used
00
125
01
128
10
64
11
32
The following table describes the clock required at the clock generator input for various clock sample rates in the different DAC
modes:
Fs (kHz)
DAC Oversampling Ratio
Required CLock at DAC Clock Generator Input (MHz)
8
125
2
8
128
2.048
11.025
125
2.75625
11.025
128
2.8224
12
125
3
12
128
3.072
16
125
4
16
128
4.096
22.05
125
5.5125
22.05
128
5.6448
24
125
6
24
128
6.144
32
125
8
32
128
8.192
23
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LM4934
Common Clock Settings for the DAC
(Continued)
Fs (kHz)
DAC Oversampling Ratio
44.1
125
Required CLock at DAC Clock Generator Input (MHz)
11.025
44.1
128
11.2896
48
125
12
48
128
12.288
88.2
64
11.2896
96
64
12.288
176.4
32
22.5792
192
32
24.576
Methods for producing these clock frequencies are described in the PLL section.
The R divider can be used when the master clock is exactly 12.00 MHz in order to generate different sample rates. The Table
below shows different sample rates supported from 12.00MHz by using only the R divider and disabling the PLL. In this way we
can save power and the clock jitter will be low.
R_DIV
Divide Value
DAC Clock Generator Input Frequency < MHz >
Sample Rate Supported < KHz >
11
6
2
8
9
5
2.4
9.6
7
4
3
12
5
3
4
16
4
2.5
4.8
19.2
3
2
6
24
2
1.5
8
32
0
1
12
48
The R divider can also be used along with the P divider in order to create the clock needed to support low sample rates.
DAC Setup Register
This register is used to configure the basic operation of the stereo DAC.
DAC_SETUP (0Eh)
(Set = logic 1, Clear = logic 0)
Bits
Register
Description
1:0
DAC_MODE
The DAC used in the LM4934 can operate in one of 4 oversampling modes.
The modes are described as follows:
DAC_MODE
Oversampling
Rate
Typical FS
Clock Required
00
125
48KHz
12.000MHz (USB
Mode)
01
128
44.1KHz
48KHz
11.2896MHz
12.288MHz
10
64
96KHz
12.288MHz
32
192KHz
24.576MHz
11
2
MUTE_L
Mutes the left DAC channel on the next zero crossing.
3
MUTE_R
Mutes the right DAC channel on the next zero crossing.
4
DITHER_OFF
If set the dither in DAC is disabled.
5
DITHER
ALWAYS_ON
If set the dither in DAC is enabled all the time.
6
CUST_COMP
If set the DAC frequency response can be programmed manually via a 5 tap FIR
“compensation” filter. This can be used to enhance the frequency response of
small loudspeakers or provide a crude tone control. The compensation
Coefficients can be set by using registers 10h to 15h.
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24
LM4934
Interface Control Register
This register is used to control the I2S and I2C compatible interface on the chip.
INTERFACE (0Fh) (Set = logic 1, Clear = logic 0)
Bits
Register
Description
0
I2S_MASTER_SLAVE
If set the LM4934 acts as a master
for I2S, so both I2S clock and I2S
word select are configured as
outputs. If cleared the LM4934 acts
as a slave where both I2S clock and
word select are configured as inputs.
1
I2S_RESOLUTION
If set the I2S resolution is set to 32
bits. If clear, resolution is set to 16
bits. This bit only affects the I2S
Interface in master mode. In slave
mode the I2S Interface can support
any I2S compatible resolution. In
master mode the I2S resolution also
depends on the DAC mode as the
note below explains.
2
I2S_MODE
If set the I2S is configured in left
justified mode timing. If clear, the
I2S interface is configured in normal
I2S mode timing.
3
I2C_FAST
If set enables the I2C to run in fast
mode with an I2C clock up to
3.4MHz. If clear the I2C speed gets
its default value of a maximum of
400kHz
NOTES:
The master I2S format depends on the DAC mode. In USB mode the number of bits per word is 25 (i.e. 2.4MHz for a 48kHz sample rate). The duty cycle is 40/60.
In non-USB modes the format is 32 or 16 bits per word, depending on I2S_RESOLTION and the duty cycle is always 50-50. In slave mode it will decode any I2S
compatible data stream.
201669A9
I2S Mode Timing
25
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LM4934
Interface Control Register
(Continued)
201669B0
Left Justified Mode Timing
FIR Compensation Filter
Configuration Registers
These registers are used to configure the DAC’s FIR compensation filter. Three 16 bit coefficients are required and
must be programmed via the I2C/SPI Interface in bytes as
follows:
COMP_COEFF (10h → 15h) (Set = logic 1, Clear = logic 0)
Address
Register
Description
10h
COMP_COEFF0_LSB
Bits [7:0] of the 1st and 5th FIR tap (C0 and C4)
11h
COMP_COEFF0_MSB
Bits [15:8] of the 1st and 5th FIR tap (C0 and C4)
12h
COMP_COEFF1_LSB
Bits [7:0] of the 2nd and 4th FIR tap (C1 and C3)
13h
COMP_COEFF1_MSB
Bits [15:8] of the 2nd and 4th FIR tap (C1 and C3)
14h
COMP_COEFF2_LSB
Bits [7:0] of the 3rd FIR tap (C2)
15h
COMP_COEFF2_MSB
Bits [15:8] of the 3rd FIR tap (C2)
NOTES:
The filter must be phase linear to ensure the data keeps the correct stereo imaging so the second half of the FIR filter must be the reverse of the 1st half.
20166955
If the CUST_COMP option in register 0Eh is not set the FIR filter will use its default values for a linear response from the DAC
into the analog mixer, these values are:
DAC_OSR
C0, C4
C1, C3
C2
00
68
–412
28526
01, 10, 11
112
–580
27551
If using 96 or 192kHz data then the custom compensation
may be required to obtain flat frequency responses above
24kHz. The total power of any custom filter must not exceed
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that of the above examples or the filters within the DAC will
clip. The coefficient must be programmed in 2’s complement.
26
LM4934
Typical Performance Characteristics
THD+N vs Frequency
3V EP Out, RL = 32Ω, PO = 20mW
THD+N vs Frequency
3V Lineout, RL = 10kΩ, VO = 850mV
20166920
20166921
THD+N vs Frequency
3V LS Out, RL = 8Ω, PO = 200mW
THD+N vs Frequency
3V HP Out, RL = 16Ω, PO = 20mW
20166922
20166923
THD+N vs Frequency
5V HP Out, RL = 16Ω, PO = 60mW
THD+N vs Frequency
5V EP, RL = 32Ω, PO = 40mW
20166924
20166926
27
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LM4934
Typical Performance Characteristics
(Continued)
THD+N vs Frequency
5V HP Out, RL = 32Ω, PO = 30mW
THD+N vs Frequency
5V LS Out, RL = 8Ω, PO = 500mW
20166929
20166930
THD+N vs Output Power
3V EP Out, RL = 32Ω, f = 1kHz
THD+N vs Output Power
3V EP Out, RL = 16Ω, f = 1kHz
201669J8
201669J9
THD+N vs Output Power
3V HP Out, RL = 32Ω, f = 1kHz
THD+N vs Output Power
3V HP Out, RL = 16Ω, f = 1kHz
201669K0
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201669K1
28
LM4934
Typical Performance Characteristics
(Continued)
THD+N vs Output Power
3V LS Out, RL = 8Ω, f = 1kHz
THD+N vs Output Power
5V EP Out, RL = 16Ω, f = 1kHz
20166975
201669K2
THD+N vs Output Power
5V HP Out, RL = 16Ω, f = 1kHz
THD+N vs Output Power
5V EP Out, RL = 32Ω, f = 1kHz
201669K3
201669K4
THD+N vs Output Power
5V LS Out, RL = 8Ω, f = 1kHz
THD+N vs Output Power
5V HP Out, RL = 32Ω, f = 1kHz
201669I9
201669K5
29
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LM4934
Typical Performance Characteristics
(Continued)
THD+N vs I2S Level
EP Out
THD+N vs I2S Level
HP Out
201669B2
201669B1
THD+N vs I2S Level
Line Out
THD+N vs I2S Level
LS Out
201669B4
201669B3
PSRR vs Frequency
3V EP Out Mode 1
PSRR vs Frequency
3V EP Out Mode 4
20166904
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20166905
30
LM4934
Typical Performance Characteristics
(Continued)
PSRR vs Frequency
3V HP Out Mode 2
PSRR vs Frequency
3V HP Out Mode 4
20166906
20166908
PSRR vs Frequency
3V Line Out Mode 1
PSRR vs Frequency
3V Line Out Mode 4
20166909
20166910
PSRR vs Frequency
3V LS Out Mode 2
PSRR vs Frequency
3V LS Out Mode 4
20166911
20166912
31
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LM4934
Typical Performance Characteristics
(Continued)
PSRR vs Frequency
5V HP Out Mode 2
PSRR vs Frequency
5V HP Out Mode 4
20166913
20166914
PSRR vs Frequency
5V Line Out Mode 1
PSRR vs Frequency
5V Line Out Mode 4
20166915
20166916
PSRR vs Frequency
5V LS Out Mode 4
PSRR vs Frequency
5V LS Out Mode 2
20166917
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20166918
32
LM4934
Typical Performance Characteristics
(Continued)
XTalk vs Frequency
5V HP Out Mode 2, RL = 32Ω, 1VRMS, SE
XTalk vs Frequency
5V LS Out Mode 2, RL = 8Ω, 1VRMS
201669B5
201669B6
Output Power vs Supply Voltage
HP Out, RL = 32Ω, 1% THD+N
Output Power vs Supply Voltage
EP Out, RL = 32Ω, 1% THD+N
201669J1
201669J0
Output Power vs Supply Voltage
LS Out, RL = 8Ω, 1% THD+N
201669J2
33
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LM4934
Application Information
I 2S
The LM4934 supports both master and slave I2S transmission at either 16 or 32 bits per word at clock rates up to 3.072MHz
(48kHz stereo, 32bit). The basic format is shown below:
20166907
FIGURE 5.
NATIONAL SEMICONDUCTOR 3D AUDIO ENHANCEMENT
The LM4934 utilizes a programmable gain version of National Semiconductor’s 3D audio enhancement circuit. This allows 3D
gain only (not frequency response) to be controlled via I2C/SPI in the National 3D Enhancement Level Select registers (3D1 and
3D0). Also, this circuit uses the same 3D path for both the headphone and stereo loudspeaker outputs, so the 3D effect remains
constant when switching from headphone to stereo loudspeaker outputs unless changed in the registers. An added benefit of this
is that the gain of the original signal is unaffected when 3D is turned on/off.
3D gain is established internally with R3D (approximately 30kΩ) and externally with C3D. Typical values for C3D are around 0.22µF,
but may varied for altered 3D response.
Gain Considerations
When using the mixer and 2,3,4, or 5 channels are summed into the stereo output (headphone or speaker), the gain of each
individual input is automatically reduced by 1/N, where N is the number of channels being summed. This has the effect of
maintaining the total signal output level for different modes (i.e.; when LIN and RIN are summed for a mono output, gain for RIN
and LIN will each be reduced by 6dB). This is not true for mono output modes, like EP and lineout. For these cases, stereo inputs
are treated as one input with a –6dB gain for each input before summing this with a mono input. An example of relative output
levels for each mode is given below:
Mode
Mono Out
Stereo R Out
1
M
M
Stereo L Out
M
2
(AL/2)+(AR+2)
AR
AL
3
[M+(AL/2)+(AR/2)]/2
(M+AR)/2
(M+AL)/2
4
(DL/2)+(DR/2)
DR
DL
5
[(AL/2)+(AR/2)+(DL/2)+(DR/2)]/2
(AR+DR)/2
(AL+DL)/2
6
[M+(AL/2)+(AR/2)+(DL/2)+(DR/2)]/2
(M+AR+DR)/3
(M+AL+DL)/3
7
[M+(DL/2)+(DR/2)]/2
(M+DR)/2
(M+DL)/2
LM4934 DEMOBOARD OPERATION
BOARD LAYOUT
DIGITAL SUPPLIES
JP14 — Digital Power DVDD
JP14 — I/O Power IOVDD
JP14 — PLL Supply PLLVDD
JP14 — USB Board Supply BBVDD
JP14 — I2C VDD
All supplies may be set independently. All digital ground is common. Jumpers may be used to connect all the digital supplies
together.
S9 – connects VDD_PLL to VDD_D
S10 – connects VDD_D to VDD_IO
S11 – connects VDD_IO to VDD_I2C
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34
LM4934
Application Information
(Continued)
S12 – connects VDD_I2C to Analog VDD
S17 – connects BB_VDD to USB3.3V (from USB board)
S19 – connects VDD_D to USB3.3V (from USB board)
S20 – connects VDD_D to SPDIF receiver chip
ANALOG SUPPLY
JP11 — Analog Supply
S12 — connects Analog VDD with Digital VDD (I2C_VDD)
S16 — connects Analog Ground with Digital Ground
S21 — connects Analog VDD to SPDIF receiver chip
INPUTS
Analog Inputs
JP2 — Mono Input
JP6 — Left Input
JP7 — Right Input
Digital Inputs
JP19 — Digital Interface
Pin 1 — MCLK
Pin 2 — I2S_CLK
Pin 3 — I2S_SDI
Pin 4 — I2S_WS
JP20 — Toslink SPDIF Input
JP21 — Coaxial SPDIF Input
Coaxial and Toslink inputs may be toggled between by use of S25. Only one may be used at a time. Must be used in conjunction
with on-board SPDIF receiver chip.
OUTPUTS
JP4 — Right BTL Loudspeaker Output
JP5 — Left BTL Loudspeaker Output
JP1 — Left Headphone Output (Single-Ended or OCL)
JP3 — Right Headphone Output (Single-Ended or OCL)
P1 — Stereo Headphone Jack (Same as JP1, JP2, Single-Ended or OCL)
JP12 — Mono BTL Earpiece Output
JP8 — Single-Ended Line Level Output
CONTROL INTERFACE
X1, X2 – USB Control Bus for I2C/SPI
X1
Pin 9 – Mode Select (SPI or I2C)
X2
Pin
Pin
Pin
Pin
Pin
Pin
1 – SDA
3 – SCL
15 – ADDR/END
14 – USB5V
16 – USB3.3V
16 – USB GND
35
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LM4934
Application Information
(Continued)
MISCELLANEOUS
I2S BUS SELECT
S23, S24, S26, S27 – I2S Bus select. Toggles between on-board and external I2S (whether on-board SPDIF receiver is used).
All jumpers must be set the same. Jumpers on top two pins selects external bus (JP19). Jumpers on bottom two pins selects
on-board SPDIF receiver output.
HEADPHONE OUTPUT CONFIGURATION
Jumpers S1, S2, S3, and S4 are used to configure the headphone outputs for either cap-coupled outputs or output capacitorless
(OCL) mode in addition to the register control internal to the LM4934 for this feature. Jumpers S1 and S3 bypass the output DC
blocking capacitors when OCL mode is required. S2 connects the center amplifer HPCOUT to the headphone ring when in OCL
mode. S4 connects the center ring to GND when cap-coupled mode is desired. S4 must be removed for OCL mode to function
properly. Jumper settings for each mode:
OCL
S1 = ON
S2 = ON
S3 = ON
S4 = OFF
Cap-Coupled
S1 = OFF
S2 = OFF
S3 = OFF
S4 = ON
PLL FILTER CONFIGURATION
The LM4934 demo board comes with a simple filter setup by connecting jumpers S5 and S6. Removing these and connecting
jumpers S7 and S8 will allow for an alternate PLL filter configuration to be used at R2 and C23.
ON-BOARD SPDIF RECEIVER
The SPDIF receiver present on the LM4934 demo board allows quick demonstration of the capabilities of the LM4934 by using
the common SPDIF output found on most CD/DVD players today. There are some limitations in its useage, as the receiver will
not work with digital supplies of less than 3V and analog supplies of less than 4V. This means low analog supply voltage testing
of the LM4934 must be done on the external digital bus.
The choice of using on-board or external digital bus is made usign jumpers S23, S24, S26, and S27 as described above.
S25 selects whether the Toslink or Coaxial SPDIF input is used. The top two pins connects the toslink, the bottom two connect
the coaxial input.
Power on the digital side is routed through S20 (connecting to the other digital supplies), while on the analog side it is interrupted
by S21. Both jumpers must be in place for the receiver to function. The part is already configured for I2S standard outputs. Jumper
S28 allows the DATA output to be pulled either high or low. Default is high (jumper on right two pins).
It may be necessary to quickly toggle S29 to reset the receiver and start it working upon initial power up.. A quick short across
S29 should clear this condition.
LM4934 I2C/SPI INTERFACE SOFTWARE
Convenient graphical user interface software is available for demonstration purposes of the LM4934. It allows for either SPI or I2C
control via either USB or parallel port connections to a Windows computer. Control options include all mode and output settings,
volume controls, PLL and DAC setup, FIR setting and on-the-fly adjustment by an easy to use graphical interface. An advanced
option is also present to allow direct, register-level commands. Software is available from www.national.com and is compatible
with Windows operating systems of Windows 98 or more (with USB support) with the latest .NET updates from Microsoft.
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36
Demonstration Board Schematic
20166956
LM4934
37
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LM4934
Revision History
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Rev
Date
Description
1.0
9/22/05
Started D/S by copying LM4931
(DS201009). Did major edits.
1.1
9/27/05
Input some text/Typical/Limits on the EC
tables.
1.2
10/6/05
Added table 1, 2, and 3. Input some text
edits also.
1.3
10/11/05
Input more edits.
1.4
10/12/05
First WEB release of the D/S.
1.5
10/13/05
D/S was taken out of the WEB per
Daniel.
1.6
10/19/05
Text edits and curves.
1.7
10/21/05
Added K6 (by Diane T.), will release to
the per Daniel.
1.8
10/24/06
Fixed typos, then released to the WEB.
1.9
11/10/05
Added the internal DAC SNR (with 95dB
typ) under Key Spec and into the Digital
EC table.
2.0
11/15/05
Added the SNR DAC, then re-webd per
Daniel.
2.1
12/14/05
Removed the WL package and replaced it
with the RL.
2.2
12/19/05
Removed the WL package and replaced it
with the RL package (per Veronica and
Daniel A.), then released D/S to the WEB.
2.3
1/19/06
Edited 20166956 (board schem, changed
WL to RL), X1, X2,and X3 values.
2.4
2/13/06
Switched the labels of B3 and B2 on the
Demo Board Schematic (pg 37) per
Daniel.
38
inches (millimeters) unless otherwise noted
42-Bump micro SMDxt
Order Number LM4934RL
NS Package Number RLA42MPA
X1 = 3.245 ± 0.030mm, X2 = 3.796 ± 0.030mm, X3 = 0.650 ± 0.075mm
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and whose failure to perform when
properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result
in a significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
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National Semiconductor manufactures products and uses packing materials that meet the provisions of the Customer Products
Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain
no ‘‘Banned Substances’’ as defined in CSP-9-111S2.
Leadfree products are RoHS compliant.
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LM4934 3D Audio Sub-System with Stereo Speaker, OCL/SE Stereo Headphone, Earpiece and
Mono Line Level Outputs
Physical Dimensions