ETC FAH4840L8X

FAH4840
Haptic Driver for Linear Resonant Actuators (LRAs)
Features
Description


Direct Drive of LRA (Linear Resonant Actuator)



Internal Motor Enable / Disable Input
The FAH4840 is a high-performance amplifier for
mobile phones and other hand-held devices. The
haptic driver takes a single-ended PWM input signal to
control a Linear Resonant Actuator (LRA). The device
utilizes an external 10 kHz to 250 kHz PWM signal
capable of meeting the wide range of resonant
frequencies needed for an LRA haptics applications.
The FAH4840 register map is accessible through an
2
I C serial communication port.







Low Shutdown Current: < 5 nA
External PWM Input (10 kHz to 250 kHz)
with Divider
Auto Resonant Tracking
LDO Provides Stable Haptic Effect with
Battery Depletion
Fast Wake-Up Time
Applications
Nearly Rail-to-Rail Output Swing



Thermal Shutdown, Over-Current Shutdown
2
Register-Based Control by I C
Mobile Phones
Handheld Devices
Any Key pad interface
Immersion TouchSense® 3000 Certified
Package: 8- Lead MicroPak™ MLP
All trademarks are the property of their respective owners.
Ordering Information
Part Number Top Mark Operating Temperature Range
FAH4840L8X
YB
© 2013 Fairchild Semiconductor Corporation
FAH4840 • Rev. 1.0.0
-40°C to +85°C
Package
MicroPak™ MLP
Packing Method Quantity
Reel
5000
www.fairchildsemi.com
FAN4840 — Haptic Driver for Linear Resonant Actuators (LRAs)
October 2013
VDD
Bandgap
Reference
UVLO
OTP
OCP
MDP
PWM
Control Logic and Register
with
Back EMF Detection
HEN
VCM
GND
Driver
DIFF AMP
MDN
EN
SCL
Serial I2C
Interface
SDA
Programmable
LDO
POR
Isen*Ro
COMP
VCM
PWM
Detection
Figure 1.
Block Diagram
Pin Configuration
Figure 2.
FAH4840 — Haptic Driver For Linear Resonant Actuators (LRAs)
Block Diagram
Pin Assignments (MicroPak MLP)
Pin Definitions
Name
Pin #
Type
Description
2
SDA
1
Input
VDD
2
Power
I C data input
Power
MDN
3
Output
Negative motor driver output
MDP
4
Output
Positive motor driver output
Ground
GND
5
Power
PWM
6
Input
PWM input
SCL
7
Input
I C clock input
HEN
8
Input
Haptic motor enable/disable (HIGH: enable, LOW: disable)
© 2013 Fairchild Semiconductor Corporation
FAH4840 • Rev. 1.0.0
2
www.fairchildsemi.com
2
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
Max.
Unit
VDD
DC Supply Voltage
-0.3
6.0
V
VIO
Analog and Digital I/O (All Input and Output Pins)
-0.3
VCC+0.3
V
Typ.
Max.
Unit
+150
°C
+150
°C
Max.
Unit
Reliability Information
Symbol
TJ
TSTG
Parameter
Min.
Junction Temperature
Storage Temperature Range
-65
Electrostatic Discharge Information
Symbol
ESD
Latch-Up
Parameter
Human Body Model, ANSI/ESDA/JEDEC JS-001-2012
4
Charged Device Model, JESD22-C101
1
Test Condition for Latch-Up Current
±150
kV
mA
FAH4840 — Haptic Driver For Linear Resonant Actuators (LRAs)
Absolute Maximum Ratings
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Min.
Typ.
Max.
Unit
TA
Operating Temperature Range
-40
+85
°C
VDD
Supply Voltage Range
2.5
3.3
4.3
V
Load impedance
15
25
50
Ω
ZLOAD
Dissipation Ratings
This thermal data is measured with a high-K board (four-layer board, according to the JESD51-7 JEDEC standard.)
Package
8-Lead MicroPak MLP
© 2013 Fairchild Semiconductor Corporation
FAH4840 • Rev. 1.0.0
ϴJA
Unit
280
°C/W
www.fairchildsemi.com
3
TA = 25°C, VDD = 3.3 V, VREG=2.0 V, unless otherwise noted.
Symbol
fIPWM
Parameter
Conditions
Min.
Typ.
10
Max.
Unit
PWM Input Frequency
Square Wave Input
250
kHz
IIHPWM
Input Current
PWM = 1.8 V
1
3
µA
IIHHEN
Input Current
HEN = 1.8 V
1
3
µA
IILPWM
Input Current
PWM = 0 V
1
3
µA
IILHEN
Input Current
HEN = 0 V
1
3
µA
VIH
Input Logic HIGH (HEN, PWM)
VIL
Input Logic LOW (HEN, PWM)
CIN
Input Capacitance
PWM Capacitance to GND or 1.8 V
VOL
Output Voltage
VDD=3.3 V, RL=15 Ω, VOL=VOL(measure)(VCM-VREG/2), See Waveforms Below
0.02
mV
VOH
Output Voltage
VDD=3.3 V, RL=15 Ω, VOH=VOH(measure)(VCM-VREG/2), See Waveforms Below
1.95
V
IOUT
Output Drive Current
VDD=3.3 V, VREG=3.0 V, RL = 15 Ω
200
mA
Short-Circuit Protection
VDD=3.3 V, VREG=3.0 V, MDP and
MDN Shorted Together and Each
Shorted to Ground
350
400
mA
IDD1
Supply Current
PWM=22.4 kHz 50% Duty, HEN =
HIGH, RL= No Load
2
5
mA
IDD2
Supply Current
PWM=22.4 kHz 90/10% Duty, HEN =
HIGH, RL= 25 Ω
77
mA
IDD3
Supply Current
PWM,HEN = 0 V, RL= 25 Ω
15
µA
IDD4
Supply Current
PWM, HEN=0 V, VDD=2.5 V, Address
0 Bit 7 Set to Zero
2.0
nA
VREG
Output Voltage Range
Measure VREG , VDD per Table
1.4
VREGA
Output Voltage Accuracy
Measure VREG
-2.5
IOUTSCP
1.15
V
6
2.0
0.5
V
10
pF
3.2
V
2.5
%
FAH4840 — Haptic Driver For Linear Resonant Actuators (LRAs)
DC Electrical Characteristics
MDP
MDN
Figure 3.
© 2013 Fairchild Semiconductor Corporation
FAH4840 • Rev. 1.0.0
Output Waveforms
www.fairchildsemi.com
4
TA = 25°C, VDD = 3.3 V, VREG=2.0 V, unless otherwise noted.
Symbol
Parameter
Conditions
Min.
tWU
Wake-Up Time
PWM=80/20% Duty Cycle, HEN/PWM LOW
to HIGH, Measurement Point PWM = 50%,
Output Point = 90%
tSD
Shutdown Time
PWM=80/20% Duty Cycle, HEN HIGH to
LOW, Measurement Point HEN = 50%,
Output Point = 90%
Auto Resonance Tracking
PWM=22.4 kHz 80/20% Duty, RL= 25 Ω
Restrk
Max.
Unit
1
150
µs
0.2
150.0
µs
2.5
Hz
-2.5
tWU
tSD
Figure 4.
Table 1.
Typ.
Haptic Enable / Disable Functional Timing
FAH4840 — Haptic Driver For Linear Resonant Actuators (LRAs)
AC Electrical Characteristics
VDD vs. VREG Supply Values
VDD (V)
VREG_OUT
(Programmed Voltage)
2.5
2.7
3.0
3.3
1.4
1.4
1.4
1.4
1.6
1.6
1.6
1.6
1.8
1.8
1.8
1.8
2.0
2.0
2.0
2.0
2.2
2.2
2.2
2.2
2.4
2.4
2.4
2.4
2.6
2.6
2.6
2.8
2.8
3.0
3.2
© 2013 Fairchild Semiconductor Corporation
FAH4840 • Rev. 1.0.0
www.fairchildsemi.com
5
TA = 25°C, VDD = 3.3 V, VREG=2.0 V, unless otherwise noted.
Symbol
Fast Mode (400 kHz)
Parameter
Min.
Max.
Unit
0.6
V
VIL
Low-Level Input Voltage
-0.3
VIH
High-Level Input Voltage
1.3
VOL
Low-Level Output Voltage at 3 mA Sink Current (Open-Drain or
Open-Collector)
0
0.4
V
IIH
High-Level Input Current of Each I/O Pin, Input Voltage=VSVDD
-1
1
µA
IIL
Low-Level Input Current of Each I/O Pin, Input Voltage=0 V
-1
1
µA
V
I2C AC Electrical Characteristics
TA = 25°C, VDD = 3.3 V, VREG=2.0 V, unless otherwise noted.
Symbol
fSCL
Fast Mode (400 kHz)
Parameter
SCL Clock Frequency
Min.
Max.
Unit
0
400
kHz
Hold Time (Repeated) START Condition
0.6
µs
tLOW
Low Period of SCL Clock
1.3
µs
tHIGH
High Period of SCL Clock
0.6
µs
tSU;STA
Set-up Time for Repeated START Condition
0.6
tHD;DAT
Data Hold Time
tHD;STA
tSU;DAT
µs
0
(1)
Data Set-up Time
0.9
100
tr
Rise Time of SDA and SCL Signals
tf
Fall Time of SDA and SCL Signals
(2)
(2)
µs
ns
20+0.1Cb
300
ns
20+0.1Cb
300
ns
Set-up Time for STOP Condition
0.6
µs
tBUF
BUS-Free Time between STOP and START Conditions
1.3
µs
tSP
Pulse Width of Spikes that Must Be Suppressed by the Input Filter
tSU;STO
0
50
FAH4840 — Haptic Driver For Linear Resonant Actuators (LRAs)
I2C DC Electrical Characteristics
ns
Notes:
2
2
1. A Fast-Mode I C Bus® device can be used in a Standard-Mode I C bus system, but the requirement tSU;DAT
≥250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the
2
Serial Data (SDA) line tr_max + tSU;DAT=1000 + 250=1250 ns (according to the Standard-Mode I C Bus
specification) before the SCL line is released.
2. Cb equals the total capacitance of one bus line in pf. If mixed with High-Speed Mode devices, faster fall times are
2
allowed according to the I C specification.
2
Figure 5. Definition of Timing for Full-Speed Mode Devices on the I C Bus
© 2013 Fairchild Semiconductor Corporation
FAH4840 • Rev. 1.0.0
www.fairchildsemi.com
6
address matches the address of the FAH4840, the
FAH4840 sends an ACK after receiving the read/write
bit by pulling the SDA line LOW for one clock cycle.
I2C Control
Writing to and reading from registers is accomplished
2
2
via the I C interface. The I C protocol requires that one
device on the bus initiates and controls all read and
write operations. This device is called the “master”
device. The master device generates the SCL signal,
which is the clock signal for all other devices on the bus.
All other devices on the bus are called “slave” devices.
The FAH4840 is a slave device. Both the master and
slave devices can send and receive data on the bus.
Setting the Pointer
For all operations, the pointer stored in the command
register must be pointing to the register that is going to
be written or read. To change the pointer value in the
command register, the read/write bit following the
address must be 0. This indicates that the master writes
new information into the command register.
2
During I C operations, one data bit is transmitted per
2
clock cycle. All I C operations follow a repeating nineclock-cycle pattern that consists of eight bits (one byte)
of transmitted data followed by an acknowledge (ACK)
or not acknowledge (NACK) from the receiving device.
There are no unused clock cycles during any operation;
therefore, there must be no breaks in the stream of data
and ACKs/NACKs during data transfers.
After the FAH4840 sends an ACK in response to
receiving the address and read/write bit, the master
must transmit an appropriate 8-bit pointer value, as
2
explained in the I C Registers section. The FAH4840
sends an ACK after receiving the new pointer data.
The pointer set operation is illustrated in Figure 8 and
Figure 9. Any time a pointer set is performed, it must be
immediately followed by a read or write operation. The
command register retains the current pointer value
between operations; therefore, once a register is
indicated, subsequent read operations do not require a
pointer set cycle. Write operations always require the
pointer be reset.
2
For most operations, I C protocol requires the SDA line
to remain stable (unmoving) whenever SCL is HIGH; i.e.
transitions on the SDA line can only occur when SCL is
LOW. The exceptions to this rule are when the master
device issues a START or STOP condition. The slave
device cannot issue a START or STOP condition.
Reading
START Condition: This condition occurs when the SDA
line transitions from HIGH to LOW while SCL is HIGH.
The master device uses this condition to indicate that a
data transfer is about to begin.
If the pointer is already pointing to the desired register,
the master can read from that register by setting the
read/write bit (following the slave address) to 1. After
sending an ACK, the FAH4840 begins transmitting data
during the following clock cycle. The master should
respond with a NACK, followed by a STOP condition
(see Figure 6).
STOP Condition: This condition occurs when the SDA
line transitions from LOW to HIGH while SCL is HIGH.
The master device uses this condition to signal the end
of a data transfer.
FAH4840 — Haptic Driver For Linear Resonant Actuators (LRAs)
Functional Description
The master can read multiple bytes by responding to the
data with an ACK instead of a NACK and continuing to
send SCL pulses, as shown in Figure 7, then the
FAH4840 increments the pointer by one and sends the
data from the next register. The master indicates the
last data byte by responding with a NACK, followed by a
STOP condition.
Acknowledge and Not Acknowledge: When data is
transferred to the slave device, the slave device sends
acknowledge (ACK) after receiving every byte of data.
The receiving device sends an ACK by pulling SDA
LOW for one clock cycle.
When the master device is reading data from the slave
device, the master sends an ACK after receiving every
byte of data. Following the last byte, a master device
sends a “not acknowledge” (NACK) instead of an ACK,
followed by a STOP condition. A NACK is indicated by
leaving SDA HIGH during the clock after the last byte.
To read from a register other than the one currently
indicated by the command register, a pointer to the
desired register must be set. Immediately following the
pointer set, the master must perform a repeated START
condition (see Figure 9), which indicates to the
FAH4840 that a new operation is about to occur. If the
repeated START condition does not occur, the
FAH4840 assumes that a write is taking place and the
selected register is overwritten by the upcoming data on
the data bus. After the START condition, the master
must again send the device address and read/write bit.
This time, the read/write bit must be set to 1 to indicate
a read. The rest of the read cycle is the same as
described in the previous paragraphs for reading from a
preset pointer location.
Slave Address
Each slave device on the bus must have a unique
address so the master can identify the device sending
or receiving data. The FAH4840 slave address is
0000110X binary or 06 HEX where “X” is the read/write
bit. Master write operations are indicated when X=0.
Master read operations are indicated when X=1.
Writing to and Reading from the FAH4840
All read and write operations must begin with a START
condition generated by the master. After the START
condition, the master must immediately send a slave
address (7 bits), followed by a read/write bit. If the slave
© 2013 Fairchild Semiconductor Corporation
FAH4840 • Rev. 1.0.0
www.fairchildsemi.com
7
the FAH4840 to acknowledge receiving the byte. The
write operation should be terminated by a STOP
condition from the master (see Figure 8).
Writing
All writes must be preceded by a pointer set, even if the
pointer is already pointing to the desired register.
As with reading, the master can write multiple bytes by
continuing to send data. The FAH4840 increments the
pointer by one and accepts data for the next register.
The master indicates the last data byte by issuing a
STOP condition.
Immediately following the pointer set, the master must
begin transmitting the data to be written. After
transmitting each byte of data, the master must release
the Serial Data (SDA) line for one clock cycle to allow
Read / Write Diagrams
SCL
SDA
A7
A6
A5
START
(from Master)
A4
A3
A2
Slave Address
(from Master)
A1
R/W ACK
D7
D6
D5
D4
ACK
(from Slave)
D3
D2
D1
D0 NACK
NACK
(from Master)
Data
(from Slave)
STOP
(from Master)
2
Figure 6.
I C Read
SCL
SDA
A7
A6
A5
A4
A3
A2
R/W ACK
D7
D6
D5
ACK
(from Slave)
Slave Address
(from Master)
START
(from Master)
A1
D4
D3
D2
D1
D0
ACK
D7
D6
D5
ACK
(from Master)
Data
(from Slave)
D4
D3
D2
D1
D0 NACK
NACK
(from Master)
Data
(from Slave)
STOP
(from Master)
2
Figure 7.
I C Multiple Byte Read
SCL
SDA
A7
A6
A5
START
(from Master)
A4
A3
A2
Slave Address
(from Master)
A1
R/W
ACK
P7
P6
P5
ACK
(from Slave)
P4
P3
P2
P1
P0
ACK
D7
D6
D5
ACK
(from Slave)
Pointer
(from Master)
D4
D3
D2
D1
D0
ACK
ACK
(from Slave)
Data
(from Master)
STOP
(from Master)
2
Figure 8.
I C Write
SCL
SDA
A7
A6
START
(from Master)
A5
A4
A3
A2
Slave Address
(from Master)
A1
R/W
ACK
P7
P6
ACK
(from Slave)
P5
P4
P3
P2
Slave Address
(from Master)
A2
P0
A7
ACK
ACK
(from Slave)
Pointer
(from Master)
A3
P1
A1
R/W
ACK
A6
A5
Repeat START
(from Master)
D7
ACK
(from Slave)
D6
D5
D4
D3
Data
(from Slave)
A4
Slave Address
(from Master)
D2
D1
D0 NACK
NACK
(from Master)
STOP
(from Master)
Figure 9.
© 2007 Fairchild Semiconductor Corporation
2
I C Write Followed by Read
www.fairchildsemi.com
Register Map Table
Adrs Register Type
Reset
Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EN_LPF
SE
VREG_
VCM
00H
CTRL1
R/W
10000000
HAPTIC_
Reserved Reserved
EN
01H
CTRL2
R/W
00110011
IN_RES[2:0]
02H
STATUS1
R
Xxxx111x
03H
CTRL_DIV1
R/W
01010011
PWM_DIV[7:0]
04H
CTRL_DIV2
R/W
00000000
PWM_DIV[15:8]
05H
CTRL_CALI
B1
R/W
00000011
06H
CTRL_CALI
B2
R/W
xxxx0011
07H
CTRL_THR
R/W
00000100
08H
CALIB_STA
TUS1
R
X001000
09H
CALIB_STA
TUS2
R
00000000
FIRST_TAG[7:0]
0AH
CALIB_STA
TUS3
R
00000000
FIRST_TAG[15:8]
0BH
CALIB_STA
TUS4
R
00000000
PWM_DIVISOR_A[7:0]
0CH
CALIB_STA
TUS5
R
00000000
PWM_DIVISOR_A[15:8]
0DH
CALIB_STA
TUS6
R
00000000
PWM_DIVISOR_B[7:0]
0EH
CALIB_STA
TUS7
R
00000000
PWM_DIVISOR_B[15:8]
0FH
CALIB_STA
TUS8
R
00000000
PWM_DIVISOR[7:0]
10H
CALIB_STA
TUS9
R
00000000
PWM_DIVISOR[15:8]
11H
CALIB_STA
TUS10
R
00000000
CNT_H[7:0]
12H
CALIB_STA
TUS11
R
00000000
CNT_L[7:0]
13H
CALIB_STA
TUS12
R
00000000
CNT_ZX[7:0]
14H
CTRL3
W/R
Xxxxxxx0
Reserved Reserved Reserved Reserved Reserved Reserved Reserved SW_RST
© 2013 Fairchild Semiconductor Corporation
FAH4840 • Rev. 1.0.0
Reserved
EN_PW
M_DET
VREG_OUT[3:0]
Reserved Reserved Reserved Reserved VDD_G
VREG_
OUT_G
MEAS_DELAY
[1:0]
RESONANCE_MARGIN[3:0]
Reserved Reserved Reserved
Reserved
CALIB_
FAIL
CALIB_
FIRST
VOT
Reserved
EN_TEMP CALIB_
_REG
EN
SEL_
AVRG
PULSE_NUM[2:0]
Z_X_NUM[7:0]
Reserved
LAST_
LEVEL
CALIB_STATE[3:0]
FAH4840 — Haptic Driver For Linear Resonant Actuators (LRAs)
Table 2.
www.fairchildsemi.com
9
CTRL1
Address:
0x00
Reset Value:
1xxxx000
Bit #
Name
Type
7
HAPTIC_EN
R/W
1: Haptic Drive Enable Mode
0: Power-Down Mode
6:3
Reserved
2
EN_LPF
R/W
1: Enable internal 20 kHz LPF
0: Disable internal LPF
1
SE
R/W
1: Single-Ended Mode
0: Differential Mode
0
VREG_VCM
R/W
1: Outputs use VREG/2 as VCMO
0: Outputs use VDD/2 as VCMO
Table 4.
CTRL2
Address:
0x01
Reset Value:
00110011
Bit #
Name
Function
Type
Function
7:5
IN_RES[2:0]
R/W
Input Resistance.
000: 8 kΩ
001: 10 kΩ
010: 12 kΩ
011: 14 kΩ
100: 16 kΩ
101: 18 kΩ
110: 20 kΩ
111: 22 kΩ
4
EN_PWM_DET
R/W
1: Enable PWM detection circuit
0: Disable PWM detection circuit
R/W
0000 1.4 V
0001 1.6 V
0010 1.8 V
0011 2.0 V
0100 2.2 V
0101 2.4 V
0110 2.6 V
0111 2.8 V
1000 3.0 V
1001 3.2 V
During LRA calibration stage 1, VREG_OUT is always 2.0 V.
3:0
VREG_OUT[3:0
]
© 2013 Fairchild Semiconductor Corporation
FAH4840 • Rev. 1.0.0
FAH4840 — Haptic Driver For Linear Resonant Actuators (LRAs)
Table 3.
www.fairchildsemi.com
10
STATUS1
Address:
0x02
Reset Value:
xxxx111x
Bit #
Name
Type
Function
7:4
Reserved
3
VDD_G
R
0: Input voltage is not good (less UVLO), Input voltage is less than 2.3 V
(rising), 2.1 V (falling)
1: Input voltage is good (over UVLO)
2
VREG_OUT_
G
R
0: Regulator output is not good (VREG_OUT is less than 70% of VREG_OUT
programmed)
(3)
1: Regulator output is good
1
VOT
R
0: Over temperature protection is tripped
1: Over temperature protection is not tripped
0
Reserved
Note:
3. HEN must be HIGH for VREG_OUT to be enabled.
Table 6.
CTRL_DIV1
Address:
0x03
Reset Value:
01010011
Bit #
7:0
Name
PWM_DIV[7:0]
Type
Function
R/W
LSB of the PWM divisor. For example, if the intended resonance frequency is
175 Hz and the PWM input clock frequency is 40 kHz, program the
PWM[15:0] register as:
PWM_DIV[15:0] = (1/175)/(1/40 kHz) = 228(decimal) = E4(HEX)
PWM_DIV[15:8] = 00
PWM_DIV[7:0] = E4
Counter range is from 01 to E4.
Default is 83
Table 7.
CTRL_DIV2
Address:
0x04
Reset Value:
00000000
Bit #
Name
Type
7:0
PWM_DIV[15:8]
R/W
© 2013 Fairchild Semiconductor Corporation
FAH4840 • Rev. 1.0.0
FAH4840 — Haptic Driver For Linear Resonant Actuators (LRAs)
Table 5.
Function
MSB of the PWM divisor.
Default is 0
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11
CTRL_CALIB1
Address:
0x05
Reset Value:
00000011
Bit #
7:4
Name
RESONANCE
_MARGIN
[3:0]
Type
Function
R/W
This is the % (of programmed PWM_DIV[15:0]) margin that is acceptable.
The measured resonance frequency is ± compared against this margin. If within
± margins, the measured resonance frequency is accepted, else it is discarded.
0000 No limit
0001 1/256 * 100 = %0.39
0010 1/128 * 100 = %0.78
0011 1/64 * 100 = %1.56
0100 1/32 * 100 = %3.12
0101 1/16 * 100 = %6.25
0110 1/8 * 100 = %12.5
0111 1/4 * 100 = %25.0
3:2
MEAS_DELA
Y[1:0]
R/W
Delay the zero crossing detection by a number of PWM clock cycles, which is
calculated by below ratio multiple PWM_DIV. For example, if set to 00, the delay
number is (PWM_DIV*1/8).
00: 1/8
01: 1/16
10: 1/32
11: 1/64
1
EN_TEMP_
REG
R/W
If set to 1, the detected PWM divisor value is stored in a Temp register and used
at the starting of the next haptic event.
If set to 0, haptic cycles always use the initial set PWM_DIV.
0
CALIB_EN
R/W
If set to 1, the part performs calibration, else no calibration.
Table 9.
CTRL_CALIB2
Address:
0x06
Reset Value:
xxxx0011
Bit #
Name
7:4
Reserved
Type
Function
3:1
PULSE_NUM
[2:0]
R/W
Determines the pulse number in stage 1 when calibration at beginning.
The pulse number is #(PULSE_NUM+1).
000: pulse number 1
001: pulse number 2
010: pulse number 3
011: pulse number 4
100: pulse number 5
101: pulse number 6
110: pulse number 7
111: pulse number 8
0
SEL_AVRG
R/W
1: select average value of two periods as final LRA period result.
0: select the detected first period as final LRA period result.
© 2013 Fairchild Semiconductor Corporation
FAH4840 • Rev. 1.0.0
FAH4840 — Haptic Driver For Linear Resonant Actuators (LRAs)
Table 8.
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12
CTRL_THR
Address:
0x07
Reset Value:
00000100
Bit #
Name
7:0
Z_X_NUM[7:0]
Type
Function
R/W
Threshold for transition region around zero-crossing point. It represents the jitter
width around the zero-crossing point. When accumulative comparator result for
one level (HIGH or LOW) around the transition edge reaches the threshold, zerocrossing point is thought to be found.
The threshold is programmed referring to PWM_DIV. To be safe, set the threshold
a bit larger than the real transition region.
Table 11.
CALIB_STATUS1
Address:
0x08
Reset Value:
x0010000
Bit #
Name
Type
Function
7
Reserved
6
CALIB_FAIL
R
After the measurement delay period passes, count period of 3*PWM_DIV. During
this time, if the four zero-crossing points are not found, calibration fails.
5
LAST_LEVEL
R
Indicate the last level (HIGH or LOW) for detecting next zero-crossing point.
4
CALIB_FIRST
R
Indicate whether current resonant detection is the first after power on reset or not.
3:0
CALIB_STATE
R
Resonant detection state machine.
Table 12.
CALIB_STATUS2
Address:
0x09
Reset Value:
00000000
Bit #
Name
Type
7:0
FIRST_TAG[7:0]
R
Table 13.
CALIB_STATUS3
Address:
0x0A
Reset Value:
00000000
Bit #
Name
Type
7:0
FIRST_TAG[15:8]
R
Table 14.
CALIB_STATUS4
Address:
0x0B
Reset Value:
00000000
Bit #
Name
Type
7:0
PWM_DIVISOR_A[7:0]
R
© 2013 Fairchild Semiconductor Corporation
FAH4840 • Rev. 1.0.0
FAH4840 — Haptic Driver For Linear Resonant Actuators (LRAs)
Table 10.
Function
LSB bits of the tag for the first found zero-crossing edge.
Function
MSB bits of the tag for the first found zero-crossing edge.
Function
LSB bits of the resonant period calculated by the first zero-crossing
point and third point.
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13
CALIB_STATUS5
Address:
0x0C
Reset Value:
00000000
Bit #
Name
Type
7:0
PWM_DIVISOR_A[15:8]
R
Table 16.
CALIB_STATUS6
Address:
0x0D
Reset Value:
00000000
Function
MSB bits of the resonant period calculated by the first zero-crossing
point and third point.
Bit #
Name
Type
Function
7:0
PWM_DIVISOR_B[7:0]
R
LSB bits of the resonant period calculated by the second zero-crossing
point and the fourth point.
Table 17.
CALIB_STATUS7
Address:
0x0E
Reset Value:
00000000
Bit #
Name
Type
Function
7:0
PWM_DIVISOR_B[15:8]
R
MSB bits of the resonant period calculated by the second zero-crossing
point and the fourth point.
Type
Function
Table 18.
CALIB_STATUS8
Address:
0x0F
Reset Value:
00000000
Bit #
7:0
Name
PWM_DIVISOR[7:0]
R
Table 19.
CALIB_STATUS9
Address:
0x10
Reset Value:
00000000
Bit #
Name
Type
7:0
PWM_DIVISOR[15:8]
R
Table 20.
CNT_H
Address:
0x11
Reset Value:
00000000
Bit #
Name
Type
7:0
CNT_H[7:0]
R
© 2013 Fairchild Semiconductor Corporation
FAH4840 • Rev. 1.0.0
FAH4840 — Haptic Driver For Linear Resonant Actuators (LRAs)
Table 15.
LSB bits of the final resonant period.
PWM_DIVISOR may comes from initial PWM_DIV, or
PWM_DIVISOR_A, or the average value of PWM_DIVISOR_A and
PWM_DIVISOR_B.
Function
MSB bits of the final resonant period.
Function
High level counter during first edge detection.
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14
CNT_L
Address:
0x12
Reset Value:
00000000
Bit #
Name
Type
7:0
CNT_L[7:0]
R
Table 22.
CNT_H
Address:
0x13
Reset Value:
00000000
Bit #
Name
Type
7:0
CNT_ZX[7:0]
R
Table 23.
CTRL3
Address:
0x14
Reset Value:
xxxxxxx0
Bit #
Name
7:1
Reserved
0
SW_RST
© 2013 Fairchild Semiconductor Corporation
FAH4840 • Rev. 1.0.0
Function
Low level counter during first edge detection.
Function
Level counter used for zero-crossing points detection.
Type
W/R
Function
Software reset bit, default is zero.
When this bit is set 1, a negative pulse is generated and all the ongoing
operation is stopped and all registers reset to default values.
This bit is self-clearing and changes back to HIGH after the negative pulse.
FAH4840 — Haptic Driver For Linear Resonant Actuators (LRAs)
Table 21.
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15
FAH4840
HOST
VDD
SDA
SDA
SCL
SCL
GND
MDP
GPIO
HEN
M
PWM
PWM
PWM
Figure 10.
Figure 11.
© 2013 Fairchild Semiconductor Corporation
FAH4840 • Rev. 1.0.0
System Block Diagram
MDN
FAH4840 — Haptic Driver For Linear Resonant Actuators (LRAs)
Applications Information
LRA System Block Diagram
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16
MDN
PWM
Host
SCL
Actuator
FAH4840
SDA
MDP
GPIO
Figure 12.
Table 24.
EN
GND
LRA System Block Diagram
LRA Resonant Actuator Function
PWM Duty Cycle
(4)
LRA Drive Voltage at Resonant Frequency
VDD
VDD
MDP
90/10%
PWM
Duty
Cycle
MDN
GND
GND
VDD
VDD
50/50%
PWM
Duty
Cycle
FAH4840 — Haptic Driver For Linear Resonant Actuators (LRAs)
VDD
MDP
MDN
GND
GND
VDD
VDD
MDN
10/90%
PWM
Duty
Cycle
MDP
GND
GND
Note:
2
4. PWM frequency is a multiple of the LRA resonant frequency. This is controlled by I C registers CTRL_DIV1 and
CTRL_DIV2. For example, if the LRA resonant frequency is 175 Hz, the PWM frequency would be 14.5 kHz and
2
the I C CTRL_DIV1 and CTRL_DIV2 registers would be programmed to 1/83.
© 2013 Fairchild Semiconductor Corporation
FAH4840 • Rev. 1.0.0
www.fairchildsemi.com
17
Thermal Shutdown
The internal LDO is designed for adjustable output
2
voltage (VREG_OUT), controlled by a 16-step I C register.
This provides flexibility, convenience, and configuration
for low-power consumption. The LDO includes an
internal circuit for short-circuit current protection.
The device has thermal shutdown capability. If the
junction temperature is above 150°C, the temperature
control block shuts down and remains off until the
temperature goes below 134°C. The register values are
kept, so re-initialization is not required.
Serial Interface
Over-Current Limitation
The driver includes a current-limitation block to protect
against an over-current condition. This is mainly a
protection against a stuck spring condition. Over-current
shutdown is at 350 mA typically.
2
The I C registers allow the user to program the motor
type, PWM dividing ratio, power-down, and other
2
functions. The device needs to function without any I C
input signals connected.
Status Registers
The status register set monitors LDO input voltage,
regulator output voltage, and over-temperature status.
2000
1800
1600
1400
1200
1000
800
600
400
200
0
2.5
2.6
2.7
2.8
2.9
3
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
4
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
5
5.1
5.2
nA
FAH4840 shut down current, software disable ON, HEN=0.
PWM=0
FAH4840 — Haptic Driver For Linear Resonant Actuators (LRAs)
Internal LDO
Vcc
Figure 13.
© 2013 Fairchild Semiconductor Corporation
FAH4840 • Rev. 1.0.0
Typical Performance Characteristics
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18
FAH4840 — Haptic Driver For Linear Resonant Actuators (LRAs)
Physical Dimensions
0.10
2X
C
A
1.6
B
1.6
INDEX AREA
0.10
2X
C
TOP VIEW
0.55 MAX
0.05
0.05
0.00
DETAIL A
8X(0.09)
C
8X
0.05
Recommended Landpattern
C
(0.20)
1.0
2
1
4 (0.1)
C
8
0.35
0.25
3X(0.2)
0.35
0.25
0.5
3
4
7
6
5
(0.15)
0.15 8X
0.25
0.35
0.25
0.10
0.05
C A B
C
DETAIL A
PIN #1 TERMINAL
SCALE: 2X
BOTTOM VIEW
Notes:
1. PACKAGE CONFORMS TO JEDEC MO-255 VARIATION UAAD
2. DIMENSIONS ARE IN MILLIMETERS
3. DRAWING CONFORMS TO ASME Y.14M-1994
4. PIN 1 FLAG, END OF PACKAGE OFFSET
5. DRAWING FILE NAME: MKT-MAC08AREV4
MAC08AREV4
Figure 14.
8-Lead, MicroPak MLP
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/dwg/MA/MAC08A.pdf.
For current packing container specifications, visit Fairchild Semiconductor’s online packaging area:
http://www.fairchildsemi.com/package/packageDetails.html?id=PN_MLLF5-008
© 2013 Fairchild Semiconductor Corporation
FAH4840 • Rev. 1.0.0
www.fairchildsemi.com
19
FAH4840 — Haptic Driver For Linear Resonant Actuators (LRAs)
© 2013 Fairchild Semiconductor Corporation
FAH4840 • Rev. 1.0.0
www.fairchildsemi.com
20
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