ETC IQX160

IQX Family Data Sheet
FEATURES
DESCRIPTION
• SRAM-based, in-system programmable
• Switch Matrix
— Non-Blocking
— Identical and predictable delays
— One-to-one, one-to-many and many-to-one connections
The IQX family of SRAM-based bit-oriented switching devices is
manufactured using a 0.6µ m CMOS process. These devices
offer clock speeds of up to 133 MHz and pin-to-pin delay as low
as 7.5 ns.
The IQX devices are used in applications requiring dynamic
switching and flexible routing / interconnection of signals. These
applications include communication switches, network systems,
DSP / image processing engines and file/video servers.
• RapidConfigure™ parallel interface for fast, incremental
configuration of Switch Matrix and I/O Port attributes
— 100% JTAG compliant
• Clocked, Latched and Flow-through Dataflow Modes
— As low as 7.5 ns pin-to-pin delay in flow-through mode
and 133 MHz clock rate in registered mode
• I/O Ports
— Individually programmable as input, output or
bidirectional
— For each I/O Port, clock, clock enable, input enable and
output enable can be selected independently from a large
pool of common control signals
— 12 mA current drive
— Separated I/O power pins for easy interfacing between
5V and 3.3V signals
At the heart of IQX devices is a non-blocking Switch Matrix. A
line in the Switch Matrix can be connected to one or more other
lines. The Switch Matrix lines are connected to I/O Ports with
programmable functional attributes.
The RapidConfigure parallel interface allows connections in the
Switch Matrix to be changed quickly and incrementally. This
interface can also be used to configure I/O Port attributes
individually and incrementally. In either case, data integrity is
maintained on all unchanged signal paths through the device.
The IQX devices support the industry standard JTAG (IEEE
1149.1) interface for boundary scan testing. The same interface
can also used for serially downloading the configuration bit
stream into the devices.
Dedicated
I/O Control Signals
Shared with
I/O Control
Signals
I/O Port
I/O Port
I/O
Control
I/O Port
I/O Port
Signal
Ports
Switch Matrix
[Crossbar Array]
I/O Port
Shared with
RapidConfigure
Interface Signals
I/O Port
I/O Port
RapidConfigure
Interface
JTAG Configuration Control
TDO TDI TMS TCK TRST*
Figure 1. IQX Functional Block Diagram
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IQX Family Data Sheet
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Contents
Features ........................................................................................................................................................1
Description...................................................................................................................................................1
1.0 Architecture ..........................................................................................................................................9
1.1 Non-blocking Switch Matrix ..........................................................................................................9
1.1.1 Switch Control ......................................................................................................................9
1.2 Programmable I/O Port .................................................................................................................10
1.2.1 Programmable Pull-up Current ............................................................................................10
1.2.2 Pin and Array Side Trickle Current .....................................................................................10
1.2.3 I/O Port Functional Mode ....................................................................................................10
1.3 I/O Control Signals .......................................................................................................................14
1.3.1 Clock Control.......................................................................................................................15
1.3.2 Tristate Control ....................................................................................................................15
1.3.3 Neighboring I/O Port As A Control Source.........................................................................15
1.3.4 Key Control Pins as a Control Source .................................................................................15
1.3.5 Default Values for Control Signals......................................................................................15
1.4 RapidConfigure (RC) Interface ....................................................................................................15
1.4.1 Switch Matrix Connection Changes ....................................................................................16
1.4.2 I/O Port Configuration .........................................................................................................18
1.4.3 I/O Port Configuration Holding Register.............................................................................18
1.4.4 I/O Port Configuration Register Contents ...........................................................................21
1.4.5 Reset Commands .................................................................................................................21
1.5 JTAG-based Configuration Controller .........................................................................................22
1.5.1 JTAG Interface ....................................................................................................................22
1.5.2 I/O Port Configuration .........................................................................................................22
1.5.3 Switch Matrix Configuration ...............................................................................................22
1.5.4 Mode Control Register Configuration .................................................................................22
2.1 Device Reset .................................................................................................................................23
2.2 Mixed Voltage Operation .............................................................................................................23
2.3 Power Pin VDD.X..........................................................................................................................23
2.4 Mode Control Register..................................................................................................................24
3.0 In System Configuration Using JTAG-based Configuration Controller ............................................25
3.1 Bit Stream Generation ..................................................................................................................25
3.2 Bit Stream Downloading ..............................................................................................................25
3.3 Configuring Multiple IQX Devices ..............................................................................................26
4.0 Pin Summary.......................................................................................................................................27
5.0 Electrical Specifications .....................................................................................................................29
5.1 Absolute Maximum Ratings (1) ................................................................................................29
5.2 Recommended Operating Conditions ........................................................................................29
5.3 Capacitance (3) ..........................................................................................................................29
5.4 DC Electrical Specifications .........................................................................................................30
5.5 AC Electrical Specifications for IQX320 and IQX240B..............................................................31
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Contents
5.6 AC Electrical Specifications for IQX160 and IQX128B..............................................................33
5.7 Parameter De-rating For One-to-Many Connections....................................................................35
5.8 Test Circuit and Timing Diagrams ...............................................................................................36
6.0 Pinout ..................................................................................................................................................43
6.1 IQX320 [PBGA/416L] Package Pinout by Name ........................................................................43
6.2 IQX320 [PBGA/416L] Package Pinout by Location ...................................................................44
6.3 IQX320 [PBGA/416L] Package Footprint ...................................................................................45
6.4 IQX240B [PQFP/304L] Package Pinout by Name.......................................................................46
6.5 IQX240B [PQFP/304L] Package Pinout by Location ..................................................................47
6.6 IQX240B [PQFP/304L] Package Pinout ......................................................................................48
6.7 IQX160 [PQFP/208L] Package Pinout by Name .........................................................................49
6.8 IQX160 [PQFP/208L] Package Pinout by Location ....................................................................50
6.9 IQX160 [PQFP/208L] Package Pinout.........................................................................................51
6.10 IQX128B [PQFP/184L] Package Pinout by Name.....................................................................52
6.11 IQX128B [PQFP/184L] Package Pinout by Location ................................................................53
6.12 IQX128B [PQFP/184L] Package Pinout ....................................................................................54
7.0 Mechanical Specification....................................................................................................................55
7.1 IQX320 [PBGA/416L] Package Dimensions ...............................................................................55
7.2 PQFP Package Dimensions .........................................................................................................56
8.0 Package Thermal Characteristics........................................................................................................57
9.0 Tables for Determining Die Pad to I/O Port Pin Mapping and Locations of Real SRAM Cell ....... 58
10.0 Component Availability and Ordering Information .........................................................................62
11.0 IQX Family at a Glance ....................................................................................................................63
12.0 Product Status Definitions ................................................................................................................64
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Figures
Figure 1. IQX Functional Block Diagram ..................................................................................................1
Figure 2. Switch Matrix Structure ..............................................................................................................9
Figure 3. Switch Matrix Control...............................................................................................................10
Figure 4. Programmable I/O Port .............................................................................................................10
Figure 5. IQX Output Driver and Pull-Up Current...................................................................................10
Figure 6. I/O Control ................................................................................................................................14
Figure 7. IQX RapidConfigure System Interface .....................................................................................16
Figure 8. Reset Circuit ..............................................................................................................................23
Figure 9. Off-line Bit Stream Generation .................................................................................................25
Figure 10. Embedded Bit Stream Generation ...........................................................................................25
Figure 11. Configuring Multiple IQX Devices.........................................................................................26
Figure 12. Test Circuit and Waveform Definition....................................................................................36
Figure 13. Registered Input and Registered Output Mode Timing (ICLK, OCLK Synchronized)..........36
Figure 14. Registered Input Mode Timing ...............................................................................................36
Figure 15. Registered Output Mode Timing.............................................................................................37
Figure 16. I/O Port Timing (Flow–through Mode)...................................................................................37
Figure 17. Input Enable Timing (Flow–through Mode) ...........................................................................37
Figure 18. Output Enable Timing (Flow–through Mode) ........................................................................38
Figure 19. Latched Input Mode Timing....................................................................................................38
Figure 20. Latched Output Mode Timing .................................................................................................38
Figure 21. Key Timing for Register Input, Clock Enable (CKE).............................................................39
Figure 22. Key Timing for Register Output, Clock Enable (CKE) ..........................................................39
Figure 23. Key Timing for Input Enable ..................................................................................................39
Figure 24. Key Timing for Output Enable................................................................................................40
Figure 25. Key Timing for Latch Input, Enable (CKE)............................................................................40
Figure 26. Key Timing for Latch Output, Enable (CKE) .........................................................................40
Figure 27. Key Counter Timing................................................................................................................41
Figure 28. RapidConfigure Timing ..........................................................................................................41
Figure 29. JTAG Timing ..........................................................................................................................42
Figure 30. IQX320 [PBGA/416L] Package Footprint..............................................................................45
Figure 31. IQX240B [PQFP/304L] Package Pinout ..................................................................................48
Figure 32. IQX160 [PQFP/208L] Package Pinout ...................................................................................51
Figure 33. IQX128B [PQFP/184L] Package Pinout.................................................................................54
Figure 34. IQX320 [PBGA/416L] Package Dimensions..........................................................................55
Figure 35. PQFP Package Dimensions .....................................................................................................56
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Tables
Table 1. Summary of Programmable I/O Attributes for IQX Devices .....................................................11
Table 2. RapidConfigure Interface Pin Count ..........................................................................................16
Table 3. RapidConfigure Options .............................................................................................................16
Table 4. Changing Switch Matrix Connections Using RapidConfigure ..................................................17
Table 5. Configuring I/O Ports Using RapidConfigure Interface.............................................................18
Table 6. I/O Port Configuration Bits ........................................................................................................19
Table 7. I/O Configuration Register Contents ..........................................................................................21
Table 8. RapidConfigure Reset Commands .............................................................................................22
Table 9. Device Reset ...............................................................................................................................23
Table 10. Mode Control Register Bit Assignment ...................................................................................24
Table 11. Number of JTAG Cycles and Configuration Time (using a 10 MHz JTAG Clock) ................26
Table 12. IQX Pin Summary ...................................................................................................................27
Table 13. Supply Voltage Source .............................................................................................................28
Table 14. Absolute Maximum Ratings .....................................................................................................29
Table 15. Recommended Operating Conditions.......................................................................................29
Table 16. Capacitance...............................................................................................................................29
Table 17. DC Electrical Specifications.....................................................................................................30
Table 18. AC Electrical Specifications for IQX320 and IQX240B..........................................................31
Table 19. AC Electrical Specifications for IQX160 and IQX128B..........................................................33
Table 20. Parameter De-rating For One-to-Many Connections................................................................35
Table 21. IQX320 [PBGA/416L] Package Pinout by Name ....................................................................43
Table 22. IQX320 [PBGA/416L] Package Pinout by Location ...............................................................44
Table 23. IQX240B [PQFP/304L] Package Pinout by Name ..................................................................46
Table 24. IQX240B [PQFP/304L] Package Pinout by Location..............................................................47
Table 25. IQX160 [PQFP/208L] Package Pinout by Name .....................................................................49
Table 26. IQX160 [PQFP/208L] Package Pinout by Location ................................................................50
Table 27. IQX128B [PQFP/184L] Package Pinout by Name ..................................................................52
Table 28. IQX128B [PQFP/184L] Package Pinout by Location..............................................................53
Table 29. PQFP Package Dimensions ......................................................................................................56
Table 30. Package Thermal Coefficients ..................................................................................................57
Table 31. IQX320 and IQX240B I/O Port Pin Mapping ..........................................................................59
Table 32. IQX160 and IQX128B I/O Port Pin Mapping ..........................................................................61
Table 33. Component Availability............................................................................................................62
Table 34. Ordering Information................................................................................................................62
Table 35. IQX Family at a Glance ............................................................................................................63
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IQX Family Data Sheet
1.0 ARCHITECTURE
IQX devices are SRAM-based bit-oriented switching matrices.
The devices can be configured and controlled in-system by
storing appropriate data into the internal SRAM cells and
configuration registers. As shown in Figure 1, the main functional
blocks of the device are the non-blocking Switch Matrix,
Programmable I/O Ports, I/O Control signal block,
RapidConfigure Configuration Interface and a JTAG-based
Configuration Controller.
Pass
Transistors
SRAM
Cells
Permanent
Connections
The full-featured programmable I/O Ports are connected to the
corresponding lines in the Switch Matrix. The I/O Port control
signals such as clock, clock enable, input enable, and output
enable are used to control the flow of data through the I/O Ports.
Signal
Lines
The JTAG-based configuration controller is used to download the
configuration bit stream serially into the I/O Port configuration
registers and Switch Matrix SRAM cells, thereby establishing the
desired functional attributes for the I/O Ports and connections
among them through the Switch Matrix. Alternatively, the
RapidConfigure parallel interface may be used to load the
configuration data in the I/O Port Configuration Registers and
Switch Matrix SRAM cells. The use of RapidConfigure interface
enables quick configuration changes.
0
Programmable I/O Buffers
1 2
3 4 5 6 7
I/O Port Pins
Figure 2. Switch Matrix Structure
1.1 Non-blocking Switch Matrix
1.1.1 Switch Control
The Switch Matrix is an x-y routing structure (or grid). Each
horizontal signal trace is hardwired to a corresponding vertical
signal trace as shown by the junction dots in Figure 2. An I/O
Port pin connects to this horizontal-vertical trace pair through a
programmable buffer. Signal paths through the Switch Matrix are
very well balanced, resulting in predictable and uniform pin-topin delays.
A pass transistor whose ON/OFF state is controlled by a
dedicated SRAM cell is placed at the intersection of two different
signal lines. Signal multicasting/broadcasting operation is
supported by allowing a Switch Matrix line carrying an incoming
signal to be connected to multiple Switch Matrix lines carrying
outgoing signals. Signal multiplexing is supported by allowing
multiple Switch Matrix lines carrying incoming signals (controlled
using input enable signals) to be connected to the same Switch
Matrix line carrying an outgoing signal. It is also possible to
create a common internal node among multiple Switch Matrix
lines by making all pair-wise connections among these signal
lines, and driving such a node by configuring the corresponding
I/O Ports in the Bus Repeater mode. Refer to the section on “I/O
Port Functional Mode” for more details.
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As shown in Figure 3, there are two possible switch and SRAM
cell locations for a connection between any two Switch Matrix
lines. For example, the two possible switch (and SRAM cell)
locations controlling a connection between signal lines i and j are
row i (word i) and column j (bit j), or row j and column i. Only one
location is populated with a switch and the controlling SRAM
cell. This location is called the real location while the other one
is referred to as the ghost location. The real cell locations form a
unique pattern on the device die as described in Appendix A.
The section on “RapidConfigure Interface” explains how this
knowledge can be used to reduce the time it takes to change
Switch Matrix connections.
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IQX Family Data Sheet
1.2.1 Programmable Pull-up Current
CA0 CA1
As shown in Figure 5, the I/O Port contains several n-channel
pull-up devices. The normal pull-up current is supplied by a
device which is switched on/off by internally generated control
signal.
CAm-1
Column (bit)
Address
RA1
Row (word)
Address
(j, i)
Pj
I/O Port Buffers
RA0
Row (word) Address Decoder
Column (bit) Address Decoder
(i, j)
An additional static pull-up current (IPU-WK) or (IPU-SG) can be
programmed at each I/O Port pin. This additional pull-up current
is primarily used for but not restricted to the Bus Repeater (BR)
mode.
VDD.PAD
RAm-1
PU
B
C
D
I/O Port Buffers
I/O Port
Pi
PD
Figure 3. Switch Matrix Control
A
A)Pull Down
B)Normal Pull Up
C)Additional Weak Pullup
D)Additional Strong Pullup
1.2 Programmable I/O Port
Each signal line in the Switch Matrix is connected to a
programmable I/O Port. The functional attributes of individual I/O
Ports can be programmed independently. The I/O Port attributes
include its signal direction (in, out or bidirectional), data flow
mode (flow-through, registered or latched), and pull-up current.
Figure 4 shows the structure of the programmable I/O Port. The
sources for the four control signals: clock (CLK), clock enable
(CKE), input enable (IE), and output enable (OE) are also
programmable and are described later in the section “I/O Control
Signals.”
E
Delay
E
Figure 5. IQX Output Driver and Pull-Up Current
1.2.2 Pin and Array Side Trickle Current
N-channel devices are used as a trickle current source
(nominally 10µ A) on the pin side and array side for each I/O
Port. Upon reset, these current sources are turned ON. They
can be turned OFF by configuring the I/O Port.
1.2.3 I/O Port Functional Mode
Table 1 describes the various modes of the I/O Port and the
specification used by the I-Cube Development System Software
for proper bit stream generation.
IE
REG
E CK
LAT
I/O Port
NC
NC
BR
Switch
Matrix
LAT
CK E
Legend:
Ax -Switch Matrix Signal
Px -I/O Port Signal
IE -Input Enable
OE -Output Enable
CLK -Clock
CKE - Clock Enable
REG
E
CLK
CKE
OE
Figure 4. Programmable I/O Port
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IQX Family Data Sheet
Symbol
Ax
Px
I/O Port Function
Mnemonic
Input - The external signal is buffered from the I/O Port pin to the corresponding Switch Matrix
line. In this mode an optional input enable (IE) can be selected. Either polarity can be selected
for IE. The default level is a logic 1.
IN
Registered Input (with variable length shift register and inversion) - The external signal at the
I/O Port pin is registered into a 7-bit edge-triggered shift register within the I/O Port. An 8-to-1
mux selects either the input (bit 0) or one of the 7 output bits of the shift register and connects
it to the corresponding signal line in the Switch Matrix through a register. Any tap on the shift
register can be selected. The true or complement of the incoming signal can be selected. The
default is bit 0, true value. A clock source is required in this mode. Either edge of CLK can be
selected. The default for CLK is rising edge. A clock enable (CKE) and input enable (IE) are
also available but not required. Either polarity can be selected for IE and CKE. The default
level for IE and CKE is a logic 1. The outputs of the shift register are unknown after hardware
reset (TRST* = 0).
RI&
[bit = value]&
[INV = value]
Latched Input - The external signal at the I/O Port pin is latched by a level-sensitive flip-flop
within the I/O Port. A latch enable source is required in this mode. The latch enable source is
composed of CLK and CKE, and at least one must be specified. An input enable (IE) is also
available but not required. Either polarity can be selected for CLK, CKE and IE. The default
level for all three is a logic 1. The output of the flip-flop is unknown after hardware reset
(TRST* = 0).
LI
Output - The internal signal is buffered from the corresponding Switch Matrix line to the I/O
Port pin. In this mode an optional output enable (OE) can be selected. Either polarity can be
selected for OE. The default level is a logic 0.
OP
Latched Output- The internal signal on the Switch Matrix line is latched by a level-sensitive
flip-flop within the I/O Port. A latch enable source is required in this mode. The latch enable
source is composed of CLK and CKE, and at least one must be specified. An output enable
(OE) is also available but not required. Either polarity can be selected for CLK and CKE. The
default level for both is a logic 1. Either polarity can be selected for OE. The default level is a
logic 0. The output of the flip-flop is unknown after hardware reset (TRST* = 0).
LO
Registered Output - The internal signal on the Switch Matrix line is registered by an edgetriggered flip-flop within the I/O Port. A clock source is required in this mode. Either edge of
CLK can be selected. The default for CLK is rising edge. A clock enable (CKE) and output
enable (OE) are also available but not required. Either polarity can be selected for CKE and
OE. The default level for CKE is a logic 1 and the default level for OE is a logic 0. The output
of the flip-flop is unknown after hardware reset (TRST* = 0).
RO
Bidirectional Transceiver - In this mode, the I/O buffer acts as a bidirectional transceiver
between the I/O Port pin and the corresponding Switch Matrix line. This mode requires an
input enable (IE) and output enable (OE). Either polarity can be selected for each but the
default level for IE is a logic 1 and the default level for OE is a logic 0. When the same source
(with default polarities) is used for IE and OE, it effectively acts as direction control. When the
same control signal (with one polarity inverted) is used for IE and OE, it effectively acts as a
Bus Repeater (BR) (see below) when both are enabled, and as No Connect (NC) when neither
is enabled.
BT
IE
IE
0
0
Px
Ax
D Q
1
7
0
7
CLK
CKE
CE
Px
D
Ax
Q
CLK
IE
LE
CKE
Px
Ax
OE
Ax
D
Px
Q
CLK
LE
CKE
Ax
OE
D
Px
Q
CLK
CKE
OE
CE
IE
Px
Ax
OE
Table 1. Summary of Programmable I/O Attributes for IQX Devices
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IQX Family Data Sheet
Symbol
Px
Ax
OE
D
Q
CLK
IE
LE
I/O Port Function
Mnemonic
Bidirectional Transceiver with Latched Input - This mode combines Latched Input (LI) and
output buffer (OP). A latch enable source is required in this mode. The latch enable source is
composed of CLK and CKE, and at least one must be specified. Either polarity can be selected
for CLK and CKE. The default level for both is a logic 1. This mode also requires an input
enable (IE) and output enable (OE). Either polarity can be selected for IE and OE. The default
level for IE is a logic 1 and the default level for OE is a logic 0. The output of the flip-flop is
unknown after hardware reset (TRST* = 0).
BT&LI
CKE
0
OE
D Q
1
IE
0
7
Px
0
Bidirectional Transceiver with Registered Input - This mode combines Registered Input
with programmable tap and inversion (RI) and buffered Output (OP). A clock source is required
in this mode. Either edge of CLK can be selected. The default for CLK is rising edge. A clock
Ax
enable (CKE) is available but not required. Either polarity can be selected. The default level for
CKE is a logic 1. This mode also requires an input enable (IE) and output enable (OE). Either
polarity can be selected for each. The default level for IE is a logic 1 and the default level for
OE is a logic 0. The output of the flip-flop is unknown after hardware reset (TRST* = 0).
BT&RI&
[bit = value]&
[INV = value]
7
CLK
CKE
CE
Ax
Px
IE
D
Q
CLK
Bidirectional Transceiver with Latched Output - This mode combines Latched Output (LO)
and input buffer (IN). A latch enable source is required in this mode. The latch enable source
is composed of CLK and CKE. At least one must be specified. Either polarity can be selected
for CLK and CKE. The default level for both is a logic 1. This mode also requires an input
enable (IE) and output enable (OE). Either polarity can be selected for IE and OE. The default
level for IE is a logic 1 and the default level for OE is a logic 0. The output of the flip-flop is
unknown after hardware reset (TRST* = 0).
BT&LO
Bidirectional Transceiver with Registered Output - This mode combines Registered Output
(RO) and buffered Input (IN). A clock source is required in this mode. Either edge of CLK can
be selected although the default is rising edge. A clock enable (CKE) is available but not
required. Either polarity can be selected but the default level is a logic 1. This mode also
requires an input enable (IE) and output enable (OE). Either polarity can be selected for IE and
OE. The default level for IE is a logic 1 and the default level for OE is a logic 0. The output of
the flip-flop is unknown after hardware reset (TRST* = 0).
BT&RO
Bidirectional Transceiver with Registered I/O- This mode is a combination of Registered
Input (RI) with programmable tap and inversion, and Registered Output (RO). A clock source
is required in this mode. Either edge of CLK can be selected. The default is rising edge. A
clock enable (CKE) is available but not required. Either polarity can be selected for CKE. The
default level is a logic 1. This mode also requires an input enable (IE) and output enable (OE).
Either polarity can be selected for IE and OE. The default level for IE is a logic 1 and the
default level for OE is a logic 0. The output of the flip-flops is unknown after hardware reset
(TRST* = 0).
BT&RI&
[bit = value]&
[INV = value]
&RO
OE
LE
CKE
Ax
Px
IE
D
Q
CLK
CKE
OE
CE
IE
0
DI
1
0
Px
QI
7
0
7
CLK
CKE
Ax
CE
Q O DO
OE
Other BT Modes- Other combinations of I/O Port modes (not covered in this table) are less
likely but can be used. The mnemonic is BT [&RI | &LI] [&RO | &LO], where the specification
inside the brackets “[ ]” is optional and “|” stands for either or. Insure that control signal
requirements are met. In these modes, the output of the flip-flops is unknown after hardware
reset (TRST* = 0).
Table 1. Summary of Programmable I/O Attributes for IQX Devices (Continued)
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IQX Family Data Sheet
Symbol
Ax
Px
Px
Px
Ax
Ax
Ax
Px
Ax
Px
Px
Ax
I/O Port Function
Mnemonic
Bus Repeater - In the Bus Repeater mode, the I/O Port behaves as a wire (with a non-zero
propagation delay). This unique feature patented by I-Cube incorporates a self-sensing circuit
to determine signal direction and does not require a direction control signal.
When multiple I/O Ports, configured as “Bus Repeater”, are connected together through the
Switch Matrix to form a single internal node, an (open collector or tristatable) external signal
appearing at any one of the I/O Ports gets repeated (or broadcast) to other I/O Ports.
The Bus Repeater mode requires a pull-up current source (see section on “Programmable
Pull-Up Current”) to operate properly. For more details, refer to the Technical Note: “The Bus
Repeater Mode.”
BR
Array Side Force 0 - In this input mode, the Switch Matrix line is forced low (logic 0),
regardless of the signal on the corresponding I/O Port. In this mode an optional input enable
(IE) can be selected. Either polarity can be selected for IE. The default level is a logic 1.
A0
Array Side Force 1 - In this input mode, the Switch Matrix line is forced high (logic 1),
regardless of the signal on the corresponding I/O Port. In this mode an optional input enable
(IE) can be selected. Either polarity can be selected for IE. The default level is a logic 1.
A1
Pin Side Force 0 - In this output mode, the I/O Port pin is forced low (logic 0), regardless of
the signal on the corresponding Switch Matrix line. In this mode an optional output enable (OE)
can be selected. Either polarity can be selected for OE. The default level is a logic 0.
F0
Pin Side Force 1 - In this output mode, the I/O Port pin is forced high (logic 1), regardless of
the signal on the corresponding Switch Matrix line. In this mode an optional output enable (OE)
can be selected. Either polarity can be selected for OE. The default level is a logic 0.
F1
No Connect - In this mode, the I/O Port pin is isolated from the Switch Matrix. This is done by
tristating both the input and output part of the I/O buffer.
NC
Table 1. Summary of Programmable I/O Attributes for IQX Devices (Continued)
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IQX Family Data Sheet
1.3 I/O Control Signals
The IQX family has a structure that gives the user a lot of flexibility in controlling the behavior of each I/O Port. As shown in Figure 6
and described below, Clock (CLK), Clock Enable (CKE), Input Enable (IE) and Output Enable (OE) signals for each I/O Port can be
selected from multiple sources. The control polarity can also be individually selected.
PORTX+1
IOBX+1
13
SEG 2
GC0-GC12
13
0-12
GT0-GT12
0
13
14
1
CLKX
15
SEG 3
Common to
All I/O Ports
0-12
0
13
14
1
CKEX
15
SEG 0
K0-K4
5
COUNTER
K0/KCLK
K1/KCKE
K2/KRST
K3/KCLR
KCLK
0-12
0
14
5
Count 5
KCKE
5
KRST
KCLR
1
1
0
IEX
15
SEG 1
1
0-12
1 1111
0
13
5-Bit
Terminal Count
K4/K1F
0
13
14
1
OEX
15
Match = 1
C
O
M
P
A
R
E
From Mode
Control Register
5
SEG 4
5-Bit
Tag
PORTX
= Programming Bits
= External Pins
GC Bus
GT Bus
KEY Bus
IOBX
IOBX-1
Included in
Each I/O Ports
Figure 6. I/O Control
14
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IQX Family Data Sheet
1.3.1 Clock Control
An I/O Port can be individually programmed to select its clock
(CLK) and clock enable (CKE) signals from sixteen sources. The
source can either be the two (four for IQX320 only) dedicated
pins - GC0 and GC1 (GC0 through GC3 for IQX320), 11 (9 for
IQX320) clock pins that are shared with signal I/O pins - GC2
through GC12 (GC4 through GC12 for IQX320), the nearest
neighboring I/O Port, or the MATCH signal generated using Key
Control (K0 - K4) pins.
1.3.2 Tristate Control
An I/O Port can be individually programmed to select its Input
Enable (IE) and Output Enable (OE) signals from sixteen
signals. The source can either be the four (five for IQX320 only)
dedicated tristate pins - GT0 through GT3 (GT0 through GT4 for
IQX320), nine (eight for IQX320) tristate pins that are shared
with signal I/O pins - GT4 through GT12 (GT5 through GT12 for
IQX320), the nearest neighboring I/O Port, or the MATCH signal
generated using Key Control (K0 - K4) pins.
1.3.3 Neighboring I/O Port As A Control Source
A physically adjacent I/O Port on the die can be used as a
source for any of the I/O control signals. Port 1 is the control
source for Port 0, Port 2 is the control source for Port 1 and so
on. Port 0 is the control source for the highest number I/O Port
on the device die. Note that due to bondout restrictions the
neighboring I/O Port may not always be brought out to a
package pin on the IQX240B and IQX128B devices.
1.3.4 Key Control Pins as a Control Source
The Key Control feature on the IQX devices allows the user to
encode mutually exclusive control signals for use as I/O control
signals. The Key pins, K0 through K4 are shared with I/O Ports.
This feature, shown schematically in Figure 6, works as follows:
Each I/O Port contains a 5-bit tag which can be programmed
with a unique value when the I/O Ports are configured. A
comparator in each I/O Port continuously compares the
programmed tag value with the signals present on the Key pins
or the output of the internal 5-bit counter. The output of the
comparator, which produces a logic 1 on a match, can be
selected as a control signal.
The Key Control is intended for use with level sensitive signals
such as IE, OE, CKE (in registered modes only). If Key Control
is used in situations where a short glitch on the internal “Match”
signal is unacceptable (i.e., using the Key Port for CLK in
registered modes and CLK and/or CKE in latched modes), it is
recommended that one of the Key pins be used as a qualifier
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and its value changed after the other Key pins have stabilized to
prevent glitches on the internal “Match” signal. Note that when
key match is used as Output Enable (OE) the match will disable
the driver, while a non-match will enable it. This can be reversed
by configuring the I/O Port to use reverse polarity for OE.
Depending on the value of the Counter Enable bit in the Mode
Control Register (see Table 10, the key input to the 5-bit
comparator comes either directly from the Key Pins (K0 through
K4) or from the output of an internal 5-bit up counter. If the
counter is selected by setting the Counter Enable bit to a logic 1,
the Key pins serve as control inputs to the counter as described
below.
K0/KCLK - Counter Clock input
K1/KCKE - Counter Clock Enable
K2/KRST - Counter (Synchronous) Reset
K3/KCLR - Counter (Asynchronous) Clear
K4/K1F - Counter Select “1F” Hex
The counter is a 5-bit modulo up counter controlled by the rising
edge on the counter clock pin (KCLK). It counts up to the 5-bit
value programmed in the Mode Control Register and then resets
to zero on the following clock edge. KCKE pin is used to qualify
the clock. Clocking is enabled when KCKE is high and disabled
when low. When the K1F pin is asserted (high), the output of the
counter is forced to “11111” regardless of the internal count.
During this time the counter continues to count up in response to
the clock input. When the KRST pin is asserted, the counter is
reset on the following clock edge. KCLR on the other hand is an
asynchronous clear. When asserted, the counter is immediately
reset to zero. When the device is reset, the Counter Enable bit
and the five Count Value bits are reset to zero.
1.3.5 Default Values for Control Signals
When the device is reset all I/O Ports are set to the default
configuration of flow-through input (IN), This is achieved by
setting the 16-to-1 muxes shown in Figure 6, to select input 15
(Vss); while the 2-to-1 muxes used for polarity selections are set
to select non-inverted value for Clock (CLK) and Clock Enable
(CKE), and inverted value for Input Enable (IE) and Output
Enable (OE).
1.4 RapidConfigure (RC) Interface
The RapidConfigure (RC) Interface allows Switch Matrix
connections and I/O Port configurations to be changed quickly. A
single Switch Matrix connection can be made or broken in a
single RapidConfigure cycle; while a single I/O Port or group of
Revision 5.0
15
IQX Family Data Sheet
2, 4, 8 or 16 I/O Ports (having the same configuration) can be
configured in a minimum of one or maximum of eight
RapidConfigure cycles.
The RapidConfigure interface shown in Figure 7 is a write only
interface. Its operation is some what similar to a memory write
cycle in a microprocessor system - it uses address, data and
control signals to write to the Switch Matrix SRAM cells and I/O
Port configuration registers. The Control bus, {P/S (Port/Switch),
C[1:0]} defines the type of operation performed by the
RapidConfigure cycle, while the Row Address, RA[m-1:0], and
Column Address, CA[m-1:0], provide the necessary addresses
and/or data for the different operations. The value “m” is different
for different devices as shown in Table 2. WE (Write Enable)
acts as chip select while STROBE is the write strobe.
Feature
IQX320
IQX240B
IQX160
IQX128B
320
240
160
128
I/O Ports Used for RC
Interface1
23 / 22
23 / 22
21/20
19/18
Row Address and
Column Address Bus
Widths
9
9
8
7
298
218
140
102
Total Number of I/O
Ports
I/O Ports whose
connections can be
changed using RC
interface2
In a typical system, an embedded processor will compute the
required Row Address, Column Address and Control values and
apply them to the IQX device. Alternatively, these values could
be computed before hand using the I-Cube supplied
development system software (IDS100), and stored in a lookup
table.
The RapidConfigure mode is enabled or disabled by correctly
setting the RC bit in the Mode Control Register. Table 3 shows
the different RapidConfigure options, depending on the values of
the “RC” and “RM” bits in the Mode Control Register. During
hardware reset (TRST* = 0) these bits are set to the signal value
on the “RCE” (RapidConnect Enable) pin. The values of these
bits can then be changed if required using the JTAG serial
interface. Note that the “P/S” signal shown in Figure 7 is required
only if the RapidConfigure interface is used for changing I/O Port
configuration, i.e., when RC bit = 1 and RM bit = 1. The pin is
available for use as signal I/O pin (I/O Port) when RM bit = 0.
Table 8 summarizes the different options. Compatibility with the
IQ family devices is achieved by connecting the RCE pin to VSS
on the board.
RC Bit RM Bit
0
RapidConfigure Mode is disabled. The device can only be
configured using the JTAG-based serial interface. In this
mode, the I/O Ports used for RapidConfigure Interface can
be used for as signal I/O Ports.
1
0
RapidConfigure Mode is enabled for changing Switch
Matrix connections but not for I/O Port configuration. The
I/O Ports can only be configured using the JTAG-based
serial interface.
In this mode, the signal coming from the P/S pin is forced
low internally. The P/S pin is available as a signal I/O Port.
1
1
RapidConfigure Mode is enabled for changing Switch
Matrix connections and I/O Port configurations.
Table 2. RapidConfigure Interface Pin Count
Notes:
1. The IQ compatibility mode uses the lower of the two numbers shown.
2. Due to the requirements for compatibility with the IQ Family and/or
bondout restrictions, this number is lower than (# in row 1 - #
in row 2) for some devices.
DATA
BUS
ADDRESS
BUS
CA[m-1:0]
I/O Port
I/O Port
RA[m-1:0]
IQX
CPU
CLK
Config
Control
Logic
RCE
C0
C1
P/S
WE
STROBE
Optional
Figure 7. IQX RapidConfigure System Interface
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Table 3. RapidConfigure Options
The user must ensure that the I/O Ports used for the
RapidConfigure interface are in the Input (IN) mode and any
connections to corresponding signal lines in the Switch Matrix
are cleared before attempting to configure the device using this
interface. During device reset, the I/O Ports used for the
RapidConfigure interface are set to the required Input (IN) and
all connections in the Switch Matrix are cleared.
1.4.1 Switch Matrix Connection Changes
I/O Port
TRST* TDI TMS TCK
16
Operation
0
As indicated earlier, the Switch Matrix SRAM cells that control
the connections among I/O Ports form a two dimensional array.
Every SRAM cell location in the Switch Matrix that is being
written to is uniquely identified by its Row (or Word) Address and
Column (or Bit) Address. The real SRAM cell responsible for the
connection between two I/O Port numbers “i” and “j” on the
Revision 5.0
June 2000
IQX Family Data Sheet
device die has the Row Address of Binary (i) and Column
Address of Binary (j), or vice versa. Furthermore, when dealing
with the bondout devices IQX240B and IQX128B the I/O Port
numbers on the device package must first be mapped to the I/O
Port number on the device die to determine the Row and
Column Address of the real SRAM cell. Refer to Appendix A for
the tables and decision logic used to determine the location of
the real SRAM cell, and the mapping of I/O Port numbers on the
device package to I/O Port numbers on the device die.
The Control bus, {P/S=0, C[1:0]} specifies the type of connection
change, either make or break; the Row and Column Addresses
are the values corresponding to the two I/O Port numbers as
determined using the tables in Appendix A. P/S is set to 0 when
changing Switch Matrix connections using RapidConfigure.
As indicated in Table 4, when the control bit C1 is held low
during a make or break operation, the remaining SRAM cells
belonging to the word addressed by the Row Address are
automatically cleared. This feature can be used to speed up
connection changes as described below.
In one common crossbar application, the signal I/O Ports on the
device are divided into equal groups of inputs and outputs, and a
pin in the output group is required to be connected to any pin in
the input group. By judicious assignment of the I/O Ports to the
output group, one can ensure that for every output port, the real
SRAM cells controlling the connection between that output port
and all ports in the input group fall on the word corresponding to
the output port number. With this assignment, when establishing
a new connection using RapidConfigure, any existing connection
to that output I/O Port is automatically broken (C1=0). Thus a
connection change, i.e., breaking an existing connection and
then making a new one, can be accomplished in one
RapidConfigure cycle. Tables in Appendix A provide information
on determining the word locations of real SRAM cells. Refer to ICube’s application notes for further details of using
RapidConfigure.
Attempting to alter the contents of the SRAM cells responsible
for connections to the I/O Ports used for the RapidConfigure
Interface will result in unpredictable results.
Control Bus
{P/S, C[1:0]}
Row Address
RA[m-1:0]
Column Address
CA[m-1:0]
Break the connection between I/O Ports i & j by writing a “0” to the SRAM cell location whose
Row Address is i and Column Address is j, [0 ≤ i, j ≤ r]. Other SRAM cells are unchanged,
i.e., no other connections are affected.(2,3)
010
BINARY(i)
BINARY(j)
Make the connection between I/O Ports i & j by writing a “1” to the SRAM cell location whose
Row Address is i and Column Address is j, [0 ≤ i, j ≤ r]. Other SRAM cell are unchanged, i.e.,
no other connections are affected.(2,3)
011
BINARY(i)
BINARY(j)
Break the connection between I/O Ports i & j by writing a “0” to the SRAM cell location whose
Row Address is i and Column Address is j, [0 ≤ i, j ≤ r]. Clear all SRAM cells on row i; i.e.,
break all the connections controlled by the real SRAM cells belonging to row i.(2,3)
000
BINARY(i)
BINARY(j)
Make the connection between I/O Ports i & j by writing a “1” to the SRAM cell location whose
Row Address is i and Column Address is j, [0 ≤ i, j ≤ r]. Clear all SRAM cells on row i; i.e.,
break all the connections controlled by the real SRAM cells belonging to row i.(2,3)
001
BINARY(i)
BINARY(j)
Operation
Table 4. Changing Switch Matrix Connections Using RapidConfigure
Notes:
(1) Binary (j) is the m-bit binary equivalent value of i. Right most bit is LSB. m equals Row/Column Address width. “i” and “j” refer to the I/O Port
number on the device die.
(2) “r” is the I/O Port number on the die corresponding the highest available signal I/O Port.
(3) Assumes the real SRAM cell controlling the connection has Row Address=Binary(j)
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IQX Family Data Sheet
1.4.2 I/O Port Configuration
Configuring I/O Ports using the RapidConfigure interface
involves two steps. During the first step the 50-bit I/O Port
Configuration Holding Register, consisting of seven 8-bit
segments, is loaded with the configuration data. The loading is
accomplished one 8-bit segment at a time, and may take up to 7
RapidConfigure cycles to load this register. In the second step,
the data in the I/O Port Configuration Holding Register is
completely transferred to the individual I/O Ports in a single
RapidConnect cycle. A single I/O Port, or a group of 2, 4, 8 or 16
contiguous I/O Ports with a starting address of modulo 2, 4, 8 or
16 respectively, (and requiring the same configuration) can be
configured in a single RapidConfigure cycle during this step.
When using RapidConfigure for configuring I/O Ports, the
Control bus, {P/S = 1, C[1:0]} specifies the type of operation; and
the Row and Column Addresses provide the information about
the I/O Port, or the group of ports to be configured. P/S is set to
1 when configuring I/O Ports using RapidConfigure. Refer to
Table 5 for details. The I/O Port information specified in the Row
and Column address values applies to the I/O pad location on
the die. When using the RapidConfigure interface for configuring
bondout versions such as the IQX240B and IQX128B proper
translation for I/O Port number on the package to the
corresponding I/O Port number on the die must first be made.
Refer to Appendix A for the mapping.
I/O Ports used for the RapidConfigure interface P/S, C[1:0], RA,
CA, WE and STROBE, cannot be configured using the
RapidConfigure interface. Combinations not listed in Table 5 may
result in unpredictable results and should be avoided.
IQX320, IQX240B
IQX160
IQX128B
Operation
Control Bus
{P/S, C[1:0]}
Row Add.
RA[8:0]
Col. Add.
CA[8:0]
Row Add.
RA[7:0]
Col. Add.
CA[7:0]
Row Add.
RA[6:0]
Col. Add.
CA[6:0]
Load Configuration Register (1)
110
000000sss
0dddddddd
0000sssd
0ddddddd
000sssd
ddddddd
Configure Port i [0 ≤ i ≤ r] (2,3)
111
ppppppppp
000000001
pppppppp
00000001
ppppppp
0000001
Configure 2 I/O Port Group
111
pppppppp0
000000011
ppppppp0
00000011
pppppp0
0000011
Configure 4 I/O Port Group
111
ppppppp00
000000111
pppppp00
00000111
ppppp00
0000111
Configure 8 I/O Port Group
111
pppppp000
000001111
ppppp000
00001111
pppp000
0001111
Configure 16 I/O Port Group
111
ppppp0000
000011111
pppp0000
00011111
ppp0000
0011111
Table 5. Configuring I/O Ports Using RapidConfigure Interface
Notes:
(1) “sss” is the 8-bit segment in the 50-bit I/O Port Configuration Holding Register and dddddddd is the 8-bit data to be loaded. Right most bits are
LSBs.
(2) “ppppp....” is the I/O Port or I/O Port Group number to be configured. This vector is 9-bits long or less, depending on the device and size of the
I/O Port Group. The I/O Port Group is a contiguous group of I/O Ports with the lowest I/O Port number being (ppppp....) multiplied by (Number of
Ports in the Group).
(3) “r” is the I/O Port number on the die corresponding to the highest I/O Port number on the package that can be configured using RapidConfigure.
1.4.3 I/O Port Configuration Holding Register
I/O Port Configuration Holding Register is used to hold the data
that is to be loaded into the I/O Port Configuration Register. This
50-bit holding register consists of six 8-bit segments and one 2bit segment, and is loaded one segment at a time using the
RapidConfigure interface.
Using the RapidConfigure interface, the holding register is first
loaded with 50 bits of data that defines the I/O Port function. The
data is then transferred into the I/O Port Configuration
Register(s), also using the RapidConfigure interface. Depending
on the current contents of the holding register segments, it may
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take 7 RapidConfigure cycles or less to load the holding register.
The holding register contains unknown values when the device
is reset.
Table 6 describes the I/O Port programming bits and shows their
location in the I/O Port Configuration Holding Register. Table 7
shows the bit values for the various I/O Port configurations.
Revision 5.0
June 2000
IQX Family Data Sheet
Name
Seg#
Bit#
0
0
IES0
Group Function
Reset
Value
Input Group
Description
1
Input Enable (IE) Source Bit 0 (LSB).
IES1
1
1
Input Enable (IE) Source Bit 1.
IES2
2
1
Input Enable (IE) Source Bit 2.
IES3
3
1
Input Enable (IE) Source Bit 3 (MSB).
INV_IE
4
1
Invert Polarity for Input Enable; Default is Active High.
IN
5
1
Input Port Mode.
A0
6
0
Force Array Side Low.
A1
7
0
Force Array Side High.
1
Output Enable (OE) Source Bit 0 (LSB).
OES0
1
0
Output Group
OES1
1
1
Output Enable (OE) Source Bit 1.
OES2
2
1
Output Enable (OE) Source Bit 2.
OES3
3
1
Output Enable (OE) Source Bit 3 (MSB).
INV_OE
4
1
Invert Polarity for Output Enable, Default is Active Low.
OP
5
0
Output Port Mode.
F0
6
0
Force Pin Side Low.
F1
7
0
Force Pin Side High.
1
Clock (CLK) Source Bit 0 (LSB).
1
Clock (CLK) Source Bit 1.
CLKS0
2
0
Clock Source,
Register, and Latch
Group
CLKS1
1
CLKS2
2
1
Clock (CLK) Source Bit 2.
CLKS3
3
1
Clock (CLK) Source Bit 3 (MSB).
LO
4
0
Latched Output Mode.
LI
5
0
Latched Input Mode.
RO
6
0
Registered Output Mode.
RI
7
0
Registered Input Mode.
Table 6. I/O Port Configuration Bits
June 2000
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IQX Family Data Sheet
Name
CKES0
Seg#
Bit#
3
0
Group Function
Reset
Value
Clock Enable Group
Description
1
Clock Enable (CKE) Source Bit 0 (LSB).
CKES1
1
1
Clock Enable (CKE) Source Bit 1.
CKES2
2
1
Clock Enable (CKE) Source Bit 2.
CKES3
3
1
Clock Enable (CKE) Source Bit 3 (MSB).
INV_CKE
4
1
Invert Polarity for Clock Enable; Default is enabled when high for Register and transparent when
High for Latch.
INV_CLK
5
0
Invert Polarity for Clock; Default is Rising Edge Triggered for Register and Transparent when
High for Latch.
INV_PI
6
0
Invert Input Data in Registered Input (RI) mode.
reserved
7
0
Reserved for internal use. Must be set to default value.
0
Key Tag Bit 0 (LSB).
0
Key Tag Bit 1.
K0
4
0
Key Control and
Pipeline Delay Group
K1
1
K2
2
0
Key Tag Bit 2.
K3
3
0
Key Tag Bit 3.
K4
4
0
Key Tag Bit 4 (MSB).
DELAY0
5
0
Input Pipeline Delay Bit 0 (LSB).
DELAY1
6
0
Input Pipeline Delay Bit 1.
DELAY2
7
0
Input Pipeline Delay Bit 2 (MSB).
0
Bus Repeater Mode.
BR
5
0
Misc. Group
IAS
1
1
Array Side Trickle Current.
IPS
2
1
Pin Side Trickle Current.
PU_WK
3
0
Weak Static Pull Up Current.
PU_SG
4
0
Strong Static Pull Up Current.
NB
5
0
Non-Buffered Mode.
reserved
6
1
Reserved for internal use. Must be set to default value.
reserved
7
1
Reserved for internal use. Must be set to default value.
0
Reserved for internal use. Must be set to default value.
0
Reserved for internal use. Must be set to default value.
reserved
reserved
6
0
Test Group
1
Table 6. I/O Port Configuration Bits (Continued)
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IQX Family Data Sheet
1.4.4 I/O Port Configuration Register Contents
Seg 3
Bit
76543210
Seg 2
Seg 1
Seg 0
Bit
Bit
Bit
76543210 76543210 76543210
11000110
00000000
00011111
00001111 00011111 00111111
00000000
11000110
00000000
00011111
00001111 00011111 00111111
00000000
11000110
000*****
00011111
00001111 00011111 001*****
00000000
11000110
000*****
00******
0010**** 00011111 00111111
00000000
11000110
000*****
00******
0010**** 00011111 001*****
00000000
11000110
********
0*******
1000**** 00011111 00011111
00000000
11000110
********
0*******
1000**** 00011111 00001111
00000000
11000110
00000000
00011111
00001111 00101111 000*****
00000000
11000110
000*****
00011111
00001111 001***** 00001111
00000000
11000110
000*****
00******
0001**** 00101111 00001111
00000000
11000110
000*****
00******
0001**** 001***** 00001111
00000000
11000110
00000000
00******
0100**** 00001111 00001111
00000000
11000110
000*****
00******
0100**** 000***** 00001111
BT
00000000
11000110
00000000
00111111
00001111 001***** 001*****
Bidirectional Transceiver w/ Latched Input
BT&LI
00000000
11000110
000*****
00******
0010**** 001***** 001*****
Bidirectional Transceiver w/ Registered Input
BT&RI
00000000
11000110
000*****
00******
1000**** 001***** 000*****
Bidirectional Transceiver w/ Latched Output
BT&LO
00000000
11000110
000*****
00******
0001**** 001***** 001*****
Bidirectional Transceiver w/ Registered Output
BT&RO
00000000
11000110
000*****
00******
0100**** 000***** 001*****
Pin Force 0
F0
00000000
11000110
00000000
00011111
00001111 01001111 00001111
Pin Force 1
F1
00000000
11000110
00000000
00011111
00001111 10001111 00001111
Array Force 0
A0
00000000
11000110
00000000
00011111
00001111 00011111 01011111
Array Force 1
A1
00000000
11000110
00000000
00011111
00001111 00011111 10011111
Bus Repeater
BR
00000000
110**111
00000000
00011111
00001111 00101111 00111111
No Connect
NC
00000000
11000110
00000000
00011111
00001111 00011111 00001111
Input
IN
Input w/ Tristate
Latched Input
LI
Latched Input w/ Tristate
Registered Input
RI
Registered Input w/ Tristate
Output
OP
Output w/ Tristate
Latched Output
LO
Latched Output w/ Tristate
Registered Output
RO
Registered Output w/ Tristate
Bidirectional Transceiver
A1
A0
IN
INV_IE
IES3
IES2
IES1
IES0
00000000
Value After Reset
F1
F0
OP
INV_OE
OES3
OES2
OES1
OES0
RI
RO
LI
LO
CLKS3
CLKS2
CLKS1
CLKS0
Seg 4
Bit
76543210
.
INV_PI
INV_CLK
INV_CKE
CKES3
CKES2
CKES1
CKES0
Seg 5
Bit
76543210
DELAY2
DELAY1
DELAY0
K4
K3
K2
K1
K0
Seg 6
Bit
76543210
.
.
NB
PU_SQ
PU_WK
IPS
IAS
BR
Mnemon
ic
.
.
.
.
.
.
.
.
I/O Mode
Table 7. I/O Configuration Register Contents
Note:
* User defined value
Each programmable I/O Port on the IQX device contains a 50-bit
Configuration Register. The function of an I/O Port is determined
by the contents of its configuration register. Table 7 shows the
contents for the different I/O functions. Combinations that are not
listed are illegal and may result in improper operation or damage
to the device.
holding register are set to the default state shown in Table 8,
however the contents of the Mode Control Register and the state
of the JTAG controller are not affected.
The bits in Table 7 indicated by a “*” refer to the values and
polarity of the various control sources and must be filled in
correctly based on the user selection of the control sources.
1.4.5 Reset Commands
The RapidConfigure interface can also be used to quickly clear
the Switch Matrix and reset the I/O Ports to their default state.
Refer to the table below for details. When RapidConfigure is
used for resetting the I/O Ports the contents of the configuration
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IQX Family Data Sheet
IQX320, IQX240B
Operation
IQX160
IQX128B
Control Bus
(P/S, C[1:0])
Row Add.
RA[8:0]
Col. Add.
CA [8:0]
Row Add.
RA[7:0]
Col. Add.
CA[7:0]
Row Add.
RA[6:0]
Col. Add.
CA[6:0]
Clear All Switch Matrix
SRAM Cells (Break
Connections)
111
000000000
000100000
00000000
00100000
0000000
0100000
Clear All Switch Matrix
SRAM Cells (Break
Connections) and Set All I/O
Ports to Power-on
Default Function [Input (IN)]
111
000000000
001100000
00000000
01100000
0000000
1100000
Table 8. RapidConfigure Reset Commands
1.5 JTAG-based Configuration Controller
1.5.2 I/O Port Configuration
In the IQX devices, the I/O attributes and Switch Matrix
connections can be programmed using the JTAG serial bus.
Additionally, the RapidConfigure Interface, used for quickly
changing I/O Port Configurations and Switch Matrix connections,
can be enabled or disabled using the JTAG serial bus.
The JTAG-based serial mode is always available for
configuration regardless of whether the RapidConfigure mode is
enabled or disabled. However proper care must be taken when
switching between JTAG and RapidConfigure for configuring the
devices. The user must ensure that the RapidConfigure mode is
first disabled by using JTAG serial mode to set the RC bit to zero
in the Mode Control Register before attempting to change Switch
Matrix connections or I/O Port configuration through JTAG.
In most cases, the user does not need to know the details of the
JTAG protocol. The I-Cube supplied software will automatically
generate the necessary bit stream from a higher-level textual
description of the required configuration.
I/O Port configuration is accomplished by loading the appropriate
bit stream into the programming registers present at each I/O
Port. The JTAG serial bus is used to load configuration data into
the I/O Port programming registers, one I/O Port at a time.
1.5.3 Switch Matrix Configuration
The contents of the SRAM cells controlling Switch Matrix
connections can be modified using the JTAG. This is
accomplished by loading the configuration data, one word at a
time into the SRAM cells in the Switch Matrix.
1.5.4 Mode Control Register Configuration
The IQX device contains a Mode Control Register. Some bits in
the register are used to store user flags such as RapidConfigure
Enable, and certain non-user flags required for proper
functioning of the device. The contents of this register can be
changed using the JTAG interface. Refer to Table 10 for details.
1.5.1 JTAG Interface
The JTAG interface is a serial interface and uses five pins: Test
Data In (TDI), Test Data Out (TDO), Test Clock (TCK), Test
Mode Select (TMS) and Test Reset (TRST*). TCK is used to
clock data in and out of TDI and TDO. TMS, in conjunction with
TDI implements a state machine that controls the various
operations of the JTAG protocol. Data on the TDI and TMS pins
is clocked into the IQX device on the rising edge of the TCK
signal, while the valid data appears on the TDO pin after the
falling edge of TCK. On the IQX devices, TRST* is used to reset
both the device and the JTAG controller.
22
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IQX Family Data Sheet
2.0 MISCELLANEOUS DETAILS
2.1 Device Reset
To ensure proper operation, the device reset pin, TRST* must be
held low during power up. The reset pulse must be at least
200 ns long. The IQX device is ready for configuration as soon
as it comes out of reset. The recommended reset circuitry is
shown in Figure 8, using an external supervisor device.
It should be noted that the TRST* pin must not be driven by any
devices which cannot guarantee a low signal during power-up.
Improper devices are those whose pins are either high or tristated during power-up. Examples of such devices are SRAMbased FPGAs.
.
When the device is in operation, different functional blocks can
be reset using one of following methods. Each method performs
a slightly different action as shown in Table 9.
IQX
+5
In any of the reset methods the edge and level-sensitive flipflops in the I/O Port buffers are not cleared and will have
unknown output values.
Vmon
Supervisor
Vdd
Ref
GND
RST
RST
TRST*
PBRST
Figure 8. Reset Circuit
Switch
Matrix
Reset Method
I/O Ports
I/O Config.
Holding
Register
JTAG
State
Machine
RapidConfigure
Interface
Pulsing TRST* low
Cleared
Set to Input (IN) Set to Input (IN) Reset
Shifting in the “Device Reset” instruction using JTAG
Cleared
Set to Input (IN) Set to Input (IN) Unchanged Enabled if RCE pin = 1
Applying “I/O Port and Switch Matrix Reset” instruction using RapidConfigure
interface
Cleared
Set to Input (IN) Set to Input (IN) Unchanged Stays Enabled
Applying “Switch Matrix Reset” instruction using RapidConfigure interface
Cleared
Unchanged
Unchanged
Enabled if RCE pin = 1
Unchanged Stays Enabled
Table 9. Device Reset
2.2 Mixed Voltage Operation
2.3 Power Pin VDD.X
There are multiple sources for power on the IQX device. The first
one called VDD is a 5V source and is used to power the device
core, including the Switch Matrix SRAM cells, I/O Port logic
(excluding the I/O buffer driver), I/O control logic, JTAG logic and
other circuitry. The I/O buffer drivers are powered by a different
source called VDD.PAD. The number of VDD.PAD sources
depends on the device. Table 13 shows the number of VDD.PAD
sources and the I/O Ports controlled by them. The VDD.PAD pins
can be connected to either a 5V or 3V supply. This makes it
easy to interface IQX device to 5V and/or 3V logic levels.
The IQX devices contain a pin marked VDD.X. The devices
contain an on-chip charge pump. In order for the charge pump to
operate correctly, it is required that the VDD.x pin be left floating
and completely unconnected. The charge pump should also be
left in its default “on’ setting. This is controlled by bit #6
(C_PUMP) of the mode control register.
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IQX Family Data Sheet
2.4 Mode Control Register
The IQX device contains a 16-bit Mode Control Register. It
stores the RapidConfigure Enable and certain other non-user
flags which must be set correctly for the proper functioning of the
device. Table 10 shows the bit assignment and their function.
A special JTAG instruction is used to write to the Mode Control
Register. When this register is written using JTAG the least
significant bit (Bit 0) is shifted in first.
Bit #
Name
Default
Description
0
KCNT
0
Key Counter Enable.
When set, uses the internal 5-bit counter to provide
Key Address
1
RM
*
Used to enable IOB configuration through
RapidConfigure interface.
Default value equals the RCE pin value on Reset.
2
RC
*
Enables or disables RapidConfigure mode.
Default value equals the RCE pin value on Reset.
3
IOB_PU1
1
IOB Pull Up 10k Ref
4
BRO_PW1
1
BR external one-shot Pulse Width 10k Ref
5
BRI_PW1
1
BR internal one-shot Pulse Width 10k Ref
6
C_PUMP
1
Charge Pump Enable Bit
7
IOB_PU2
0
IOB Pull Up 20k Ref
8
BRO_PW2
0
BR external one-shot Pulse Width 20k Ref
9
BRI_PW2
0
BR internal one-shot Pulse Width 20k Ref
10
INTERNAL
0
For internal use. Should not be changed by the user.
11
KVAL0
0
Terminal count value bit 0 (LSB) when internal
counter is used as Key Address
12
KVAL1
0
Terminal count value bit 1 when internal counter is
used as Key Address
13
KVAL2
0
Terminal count value bit 2 when internal counter is
used as Key Address
14
KVAL3
0
Terminal count value bit 3 when internal counter is
used as Key Address
15
KVAL4
0
Terminal count value bit 4 (MSB) when internal
counter is used as Key Address
Table 10. Mode Control Register Bit Assignment
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IQX Family Data Sheet
3.0 IN SYSTEM CONFIGURATION USING JTAGBASED CONFIGURATION CONTROLLER
The JTAG-based configuration mode allows the user to initialize
the device, configure the I/O Ports, establish connections
through the Switch Matrix and set the contents of the Mode
Control Register.
Configuring the device using JTAG involves two steps. In the
first step the user generates the bit stream. Two different
software options - off-line and embedded bit stream generation are available to accomplish this task. The choice depends on the
target application. The second step is the actual downloading of
the bit stream into the device. The downloading circuitry can
take on different forms, depending on the target application.
• By using I-Cube Development System Software product
IDS100.
• By user written code based on the information provided in the
“IQX Family Register Programming Users Reference.”
If the bit stream is generated off-line then, depending on the
application, it is either stored in non-volatile memory or directly
downloaded from a host processor such as a PC connected to
the target hardware.
3.2 Bit Stream Downloading
Compile Configuration File
to Create Configuration Bitstream
The bit stream can be downloaded into the IQX device using
several different hardware schemes. The choice depends on the
end application. All these schemes use the standard JTAG
protocol and timing. As per the JTAG protocol, the clock signal
(TCK) must be supplied externally.
Convert Bitstream for Use with
Configuration Circuitry in the Target System
Serial
Onboard
Download
EPROM Microcontroller
Cable
Figure 9. Off-line Bit Stream Generation
If the target hardware is controlled by a computer such as a PC,
the parallel port on the computer can be used to download the
bit stream. I-Cube provides a software utility to perform the
downloading. Under this scheme, the necessary data for TDI
and TMS pins as well as the (software generated) TCK clock
signal are sent over the parallel port.
An on-board byte-wide EPROM or E2PROM, or a serial
E2PROM can be used to store the bit stream. Using minimal
external logic, the bit stream stored in one of these devices can
be downloaded into the IQX device(s) over the TDI and TMS
pins, with the TCK pin used for synchronization. The clock signal
for the TCK pin is generated by the external logic.
Memory
Application
Software
IQX
Programming
Library
The configuration bit stream can be generated off-line or insystem by an embedded CPU using one of the following
methods:
The software used for off-line generation accepts a text file
describing the desired configuration - connections between
different I/O Ports, functional attributes of each I/O Port, and
settings of certain user flags - and generates a file containing the
bit stream.
Create Configuration File
(Text File)
EPROM
3.1 Bit Stream Generation
Configuration
Circuitry
IQX
Figure 10. Embedded Bit Stream Generation
June 2000
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If the target system has an on-board microcontroller, the bit
stream data can be read from memory and downloaded into the
IQX device(s) using 3 I/O pins on the microcontroller to generate
the required TDI, TMS and TCK signals. For real-time
applications, the microcontroller/microprocessor can generate
the bit stream (using the I-Cube supplied software examples or
user written code) and then download it into the IQX device in a
single operation.
Revision 5.0
25
IQX Family Data Sheet
The actual time required to download the configuration bit
stream and program a IQX device depends on the device(s)
used, the user’s specific configuration pattern, and JTAG clock
frequency. Table 11 shows the number of JTAG cycles and
configuration time required for some typical operations. The size
of the memory (number of bytes) required is two (one each for
TDI and TMS) times the number of JTAG cycles divided by eight.
U3
U2
IQX
TDO
TDI
TDI
U1
IQX
IQX
TDO
TDI
TDO
TDI
TCK
TCK
TCK
TMS
TMS
TMS
TRST*
TRST*
TRST*
TDO
TCK
3.3 Configuring Multiple IQX Devices
TMS
TRST*
The JTAG-based controller allows a single device or multiple
IQX devices connected in a chain to be configured in a single
operation. For multiple device configuration, the pins are
connected as shown in Figure 11.
Figure 11. Configuring Multiple IQX Devices
During the initial configuration sequence, the internal controllers
on all IQX devices are first brought to their reset state by pulsing
the TRST* reset pin low. This is followed by the actual
configuration bit stream, which is downloaded into the IQX
devices over the TDI and TMS pins.
Bitstream Size
JTAG Cycles
Config. Time
IQX128B
Bitstream Size
JTAG Cycles
Config. Time
IQX160
Bitstream Size
JTAG Cycles
Config. Time
IQX240B
Bitstream Size
Operation
Config. Time
JTAG Cycles
IQX320
JTAG Reset Sequence (TMS = “11111”)
5
500
ns
10
bits
5
500
ns
10
bits
5
500
ns
10
bits
5
500
ns
10
bits
Enable or Disable Rapid Configure
42
4.2
µs
84
bits
42
4.2
µs
84
bits
42
4.2
µs
84
bits
42
4.2
µs
84
bits
Change IOB attributes of ONE I/O Port
76
7.6
µs
152
bits
76
7.6
µs
152
bits
76
7.6
µs
152
bits
76
7.6
µs
152
bits
Change IOB attributes of ALL I/O Ports
24 K
2.4
ms
6 KB
18 K
1.8
ms
4.5
KB
12 K
1.2
ms
4 KB
10 K
1.0
ms
2.5
KB
Reset JTAG Controller + Reset ALL I/O Ports + Clear ALL SRAM cells
32
3.2
µs
64
bits
32
3.2
µs
64
bits
32
3.2
µs
64
bits
32
3.2
µs
64
bits
Connect or disconnect two I/O Ports
346
34.6
µs
692
bits
346
34.6
µs
692
bits
186
18.6
µs
372
bits
186
18.6
µs
372
bits
110 K 11.0
ms
27.5
KB
84 K
8.4
ms
21 KB 30 K
3.0
ms
7.5
KB
24 K
2.4
ms
6 KB
13.4 34 KB 102 K 10.02 26 KB 42 K
ms
ms
4.2
ms
11 KB 34 K
3.4
ms
9 KB
Configure Entire Switch Matrix
Completely Configure the Device (All I/O and All Switch Matrix Connections) 134K
Table 11. Number of JTAG Cycles and Configuration Time (using a 10 MHz JTAG Clock)
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IQX Family Data Sheet
4.0 PIN SUMMARY
IQX320
IQX240B
IQX160
IQX128B
DIR
P000 - P083
I/O
Dedicated I/O Ports
P104, P105,
P106, P108,
P109
P84 -P88
I/O
Shared I/O Ports
I/O Ports shared with General Tristate Control GT12 - GT8, used for Input Enable (IE) and
Output Enable (OE) Signals.
P199 - P203
P110, P111,
P112, P114,
P115
P89 -P93
I/O
Shared I/O Ports
I/O Ports shared with General Clock Control GC12 - GC8, used for Clock (CLK) and Clock
Enable (CKE) Signals.
P273, P275, P277,
P279, P281
P204 - P208
P116, P117,
P120, P121,
P122
P94 -P98
I/O
Shared I/O Ports
I/O Ports shared with Key Control K4 - K0, used for generating Clock (CLK), Clock Enable
(CKE), Input Enable (IE) and Output Enable (OE) signals.
P283, P285,
P287, P289
P209-P212
P125-P128,
P138, P137
P99-P102,
P108, P107
I/O
P291, P293, P295
P213 - P215
P131 - P134
P103 - P106
I/O
GT4 - GT0
GT4 - GT0
GT3 - GT0
GT3 - GT0
I
(Dedicated) General Tristate Control Pins
Used for Input Enable (IE) and Output Enable (OE) Signals.
GC3 - GC0
GC3 - GC0
GC1 - GC0
GC1 - GC0
I
(Dedicated) General Clock Control Pins
Used for Clock (CLK) and Clock Enable (CKE) signals.
P296 - P304
CA0 - CA8
P216 - P224
CA0 - CA8
P140 - P147
CA0 - CA7
P110 - P116
CA0 - CA6
I/O
Shared I/O Ports
I/O Ports shared with Column Address (CA) Bus
P306 - P314
RA0 - RA8
P226 - P234
RA0 - RA8
P148 - P155
RA0 - RA7
P117 - P123
RA0 - RA6
I/O
Shared I/O Ports
I/O Ports shared with Row Address (RA) Bus
P315 - P317
P235 - P237
P139, P156,
P157
P109, P124,
P125
I/O
Shared I/O Ports
I/O Ports shared with P/S, C0 AND C1
P318, P319
P238, P239
P158, P159
P126, P127
I/O
Shared I/O Ports
RapidConfigure Write Enable (WE) and Write Strobe (STROBE)
TRST*
TRST*
TRST*
TRST*
I
TDI, TMS, TCK,
TDO
TDI, TMS,
TCK,
TDO
TDI, TMS,
TCK,
TDO
TDI, TMS,
TCK,
TDO
I
I
O
RCE
RCE
RCE
RCE
I
RapidConfigure Enable Pin
For Enabling RapidConfigure interface after reset
VDD.PAD1
VDD.PAD2
VDD.PAD3
VDD.PAD4
VDD.PAD1
VDD.PAD2
VDD.PAD3
VDD.PAD4
VDD.PAD1
VDD.PAD2
VDD.PAD1
VDD.PAD2
P
P
P
P
Power & Ground Pins
Power Pins for Group 1
Power Pins for Group 2
Power Pins for Group 3
Power Pins for Group 4
P000 - P259,
P262, P264, P266,
P274, P276, P278,
P280, P282, P284,
P286, P288, P290,
P292, P294, P305
P000 - P193, P000 - P103,
P225
P107, P113,
P118, P119,
P123, P124,
P129, P130,
P135, P136
P260, P261, P263,
P265, P267
P194, P195,
P196, P197,
P198
P268 - P272
Description
Shared I/O Ports
I/O Ports shared with General Clock Control GC7-GC4 for IQX320 and IQX240B and GC7GC2 for remaining devices, used for Clock (CLK) and Clock Enable (CKE) Signals.
Shared I/O Ports
I/O Ports shared with General Tristate Control GT7 - GT5 for IQX320 and IQX240B and GT7
- GT4 for remaining devices, used for Input Enable (IE) and Output Enable (OE) Signals.
Hardware Reset
Device Reset
JTAG Pins
For downloading the serial configuration bitstream
I/O
I/O
I/O
I/O
Buffer
Buffer
Buffer
Buffer
Drivers.
Drivers.
Drivers.
Drivers.
Table 12. IQX Pin Summary
June 2000
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IQX Family Data Sheet
IQX320
IQX240B
IQX160
IQX128B
DIR
VDD
VDD.X
VSS
VDD
VDD.X
VSS
VDD
VDD.X
VSS
VDD
VDD.X
VSS
P
P
P
Description
Power Pins for on-chip circuitry other than I/O Buffer Drivers.
Supply for Switch Matrix.
Ground Pins.
Table 12. IQX Pin Summary (Continued)
Supply Voltage
Pins Powered by Supply Voltage
IQX320
IQX240B
IQX160
IQX128B
VDD
TDI,TMS,TCK,TRST*, GC0-GC3,
GT0-GT4
TDI,TMS,TCK,TRST*, GC0-GC3,
GT0-GT4
TDI,TMS,TCK, TDO, TRST*, GC0, TDI,TMS,TCK,TDO,TRST*, GC0,
GC1, GT0-GT3
GC1, GT0-GT3
VDD.PAD1
P000:P079, TDO
P000:P059, TDO
P000:P079
P000:P063
VDD.PAD2
P080:P159
P060:P119
P080:P159
P064:P127
VDD.PAD3
P160:P239
P120:P179
VDD.PAD4
P240:P319
P180:P239
Table 13. Supply Voltage Source
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IQX Family Data Sheet
5.0 ELECTRICAL SPECIFICATIONS
5.1 Absolute Maximum Ratings (1)
Symbol
Parameter
Limits
Units
VDD
Supply Voltage to Ground
-0.3 to +7.0
V
VDD.PAD
Supply Voltage for I/O Buffer Driver
-0.3 to +7.0
V
VIN (2)
Input Voltage
-0.3 to
(VDD.PAD + 0.3)
V
TJ
Junction Temperature
150
°C
TSTG
Storage Temperature
-65 to +150
IOS
Current per Port Pin
°C
± 100
mA
Table 14. Absolute Maximum Ratings
5.2 Recommended Operating Conditions
Symbol
Parameter
Limits
Units
VDD
Supply Voltage to Ground
4.75 to 5.25
V
VDD.PAD (4)
Supply Voltage for I/O Buffer Driver
4.75 to 5.25
2.97 to 3.63
V
TA
Operating Temperature
0 to 70
°C
Table 15. Recommended Operating Conditions
5.3 Capacitance (3)
Symbol
Parameter
Min
Max
CIN
Input Capacitance (JTAG pins)
-
8
Units
pF
COUT
Output Capacitance (TDO pin)
-
8
pF
CPORT
I/O Signal Port
-
10
pF
CCNTL
Dedicated General Clock and
General Tristate Pin Capacitance
-
10
pF
Table 16. Capacitance
Notes:
(1) Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
(2) A maximum overshoot and undershoot of 2V for a maximum duration of 20 ns is acceptable.
(3) Capacitance measured at 25°C. Sample-tested only.
(4) VDD.PAD1, VDD.PAD2, VDD.PAD3 and VDD.PAD4 can operate at different voltages from each other.
June 2000
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IQX Family Data Sheet
5.4 DC Electrical Specifications
(TA = 0°C to 70°C, VDD = 5V±5%; V DD .PAD = 5V±5%, or V DD .PAD = 3.3V±10%)
Symbol
Parameter
Conditions
IQX320, IQX240B
IQX160, IQX128B
Min
Max
Min
Max
Unit
2.0
VDD + 0.3
2.0
VDD + 0.3
V
VIH
High-Level Input Voltage
VIL
Low-Level Input Voltage
-0.3
0.8
-0.3
0.8
V
VOH
High-Level Output Voltage
VDD = Min, VDD.PAD = 4.75V
IOH = - 8 mA
2.4
-
2.4
-
V
High-Level Output Voltage
VDD = Min, VDD.PAD = 2.97V
IOH = - 4mA
2.4
-
2.4
-
V
Low-Level Output Voltage
VDD = Min, VDD.PAD = 4.75V
IOL = 12 mA
-
0.4
-
0.4
V
Low-Level Output Voltage
VDD = Min, VDD.PAD = 2.97V
IOL = 12 mA
-
0.4
-
0.4
V
|IIH“|” |IIL|
IPT
Input Leakage Current for I/O ports
VDD = Max, 0 ≤ VIN ≤
VDD = Max, 0 ≤ VIN ≤
VDD.PAD
-
5
-
5
µA
I/O Port Trickling Current(1)
VDD.PAD
-
-25
-
-25
µA
|IOZ|
Tristate Output Off-State Current
VDD = Max, 0 ≤ VIN ≤ VDD.PAD
-
5
-
5
µA
IPU-WK
Programmed-Weak Additional Pull-Up Current
VDD = VDD.PAD = 4.75V, VO = GND
2.5
4.0
2.0
4.0
mA
IPU-SG
Programmed-Strong Additional Pull-Up Current
9
13.5
8.0
13.5
mA
IOS
Short Circuit Current(1, 2)
VDD = VDD.PAD = 4.75V, VO = GND
VDD = Max, VO = GND
-60
-
-60
-
mA
-
85
-
85
mA
VOL
IDDQ_CORE Quiescent Core Power Supply Current
VDD = Max, I/O = GND, CP = On
VDD = Max, I/O = GND, CP = Off
-
8
-
8
mA
VDD.PAD = 5.25V, All I/O = NC
VDD = Max, VO = GND
-
80
-
80
µA
QDDD_CORE Dynamic CorePower Supply Current
VDD.PAD = 5.25V, VDD = Max, No Load,
@ 1.0 MHZ clock input, connect one output
per input
-
0.2
-
0.1
mA/
MHz
QDDD_PAD Dynamic Pad Power Supply Current
VDD.PAD = 5.25V, VDD = Max, No Load,
@ 1.0 MHZ clock input, connect one output
per input
-
0.1
-
0.05
mA/
MHz
IDDQ_PAD
Quiescent Pad Power Supply Current
Table 17. DC Electrical Specifications
Notes:
(1) These parameters are guaranteed but not tested in production.
(2) No more than one output should be tested at a time and the duration of the test should be limited to less than one second.
30
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IQX Family Data Sheet
5.5 AC Electrical Specifications for IQX320 and IQX240B
(TA = 0°C to 70°C, VDD = 5V±5%; V DD.PAD = 5V±5%, or V DD.PAD = 3.3V±10%. Assume two I/O ports connected
through the Switch Matrix with 35 pF external loading)
Speed Grade
Symbol
Parameter
-10
-12
Ref.
Min Max Min Max Units Figure
fRIO
Register Input/Output, Clock Frequency(1, 2)
tW-RIO
Register Input/Output, Clock Pulse Width, Low or High(1, 2)
4.5
5.5
tS-RIO
Register Input/Output, Data Setup Time to CLK
2.5
3.0
ns
tH-RIO
Register Input/Output, CLK to Data Hold Time
2.0
2.0
ns
tCO-RIO
Register Input/Output, Clock to Output Data Valid
9.5
11.5
ns
fRI
Register Input, Clock Frequency (1)
80
66
MHz
tW-RI
Register Input, Clock Pulse Width, Low or High
4.5
5.5
tS-RI
Register Input, Data Setup Time to CLK
2.5
3.0
ns
tH-RI
Register Input, CLK to Data Hold Time
2.0
2.0
ns
tCO-RI
Register Input, Clock to Output Data Valid
12.5
15.0
ns
fRO
Register Output, Clock Pulse Frequency(1)
100
80
MHz
tW-RO
Register Output, Clock Width, Low or High
4.5
5.5
tS-RO
Register Output, Data Setup Time to CLK
4.5
5.0
ns
tH-RO
Register Output, CLK to Data Hold Time
0.0
0.0
ns
tCO-RO
Register Output, Clock to Output Data Valid
9.5
11.5
tPHL, tPLH
One Way Signal Propagation Delay
10.0
12.5
ns
tSK
Skew Between Output Ports(1)
1.5
1.5
ns
tW+
Input Flow Through Positive Pulse Width(2)
4.5
6.0
ns
tW-
Input Flow Through Negative Pulse Width(2)
6.5
8.0
ns
RDATA
NRZ Data Rate(1, 2)
180
150
Mb/s
tPZH-IT, tPZL-IT
Input Enable (GT) to Data Valid
12.0
13.0
ns
17
tPZH-OT, tPZL-OT
Output Enable (GT) to Data Valid
12.0
13.0
ns
18
tPHZ-OT, tPLZ-OT
Output Enable (GT) to Output at High Z(1)
8.5
10.5
ns
tW-LI
Latch Input, Latch Enable (GC) Pulse Width, Low or High
4.5
5.5
tS-LI
Latch Input, Data Setup Time to Latch Enable (GC) Trailing Edge
2.5
3.0
ns
tH-LI
Latch Input, Data to Latch Enable (GC) Trailing Edge Hold Time
2.0
2.0
ns
tCO-LI
Latch Input, Latch Enable (GC) Leading Edge to Data Out Delay
tP-LIT
Latch Input, Transparent Mode Propagation Delay
tW-LO
Latch Output, Latch Enable (GC) Pulse Width, Low or High
tS-LO
Latch Output, Data Setup Time to Latch Enable (GC) Trailing Edge
4.5
5.0
ns
tH-LO
Latch Output, Data to Latch Enable (GC) Trailing Edge Hold Time
0.0
0.0
ns
tCO-LO
Latch Output, Latch Enable (GC) Leading Edge to Data Out Delay
tP-LOT
Latch Output, Transparent Mode Propagation Delay
tKW-RI
Register Input, Minimum Pulse Width of KEY as Clock Enable, Low or High
tKS-RI
Register Input, Clock Enable (Key) Setup Time to CLK (GC)
3.0
3.5
ns
tKH-RI
Register Input, CLK (GC) to Clock Enable (Key) Hold Time
2.0
2.0
ns
tKCO-RI
Register Input, Key Clock to Output Data Valid
100
80
15.0
ns
15
ns
16
ns
12.5
19
ns
ns
ns
25.0
27.5
10.0
12.5
ns
7.0
ns
13.0
14
ns
5.5
6.0
13
ns
17.5
10.0
4.5
MHz
15.5
20
ns
21
ns
Table 18. AC Electrical Specifications for IQX320 and IQX240B
June 2000
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IQX Family Data Sheet
Speed Grade
Symbol
Parameter
-10
-12
Ref.
Min Max Min Max Units Figure
tKW-RO
Register Output, Minimum Pulse Width of KEY as Clock Enable, Low or High
6.0
7.0
tKS-RO
Register Output, Clock Enable (Key) Setup Time to CLK (GC)
5.0
5.5
ns
tKH-RO
Register Output, CLK (GC) to Clock Enable (Key) Hold Time
0.0
0.0
ns
tKCO-RO
Register Output, Key Clock to Output Data Valid
7.5
9.5
tKPZH-IT tKPZL-IT
Input Enable (Key) to Data Valid
11.0
13.5
ns
23
9.0
11.0
ns
24
11.0
ns
tKPZH-OT tKPZL-OT Output Enable (Key) to Data Valid
tKPHZ-OT tKPLZ-OT Output Enable (Key) to Output at High Z(1)
9.0
ns
22
ns
tKW-LI
Latch Input, Minimum Pulse Width of KEY as Latch Enable, Low or High
6.0
7.0
ns
tKS-LI
Latch Input, Data Setup Time to Latch Enable (Key) Trailing Edge
3.0
3.5
ns
tKH-LI
Latch Input, Data to Latch Enable (Key) Trailing Edge Hold Time
2.0
tKCO-LI
Latch Input, Latch Enable (Key) Leading Edge to Data Out
tKP-LIT
Latch Input, Transparent Mode Propagation Delay
tKW-LO
Latch Output, Minimum Pulse Width of KEY as Latch Enable, Low or High
tKS-LO
Latch Output, Data Setup Time to Latch Enable (Key) Trailing Edge
5.0
5.5
ns
tKH-LO
Latch Output, Data to Latch Enable (Key) Trailing Edge Hold Time
0.0
0.0
ns
tKCO-LO
Latch Output, Latch Enable (Key) Leading Edge to Data Out
7.5
9.5
tKP-LOT
Latch Output, Transparent Mode Propagation Delay
10.0
12.5
ns
fKCNT
Key Counter, Input Clock Frequency
66
50
MHz
tWKCNT
Key Counter Clock, Pulse Width
6.0
7.0
ns
tS_KCKE
Key Counter, Enable Setup Time to KCLK
2.5
3.5
ns
tH_KCKE
Key Counter, KCLK to Enable Hold Time
0.0
0.0
ns
tS_KRST
Key Counter, Reset Setup Time to KCLK
2.5
3.5
ns
tH_KRST
Key Counter, KCLK to Reset Hold Time
0.0
tKCLK_OE
Key Counter, Clock to Output Data Valid or Output High Z
9.5
11.5
ns
tKCLK_IE
Key Counter, Clock to Input Data Valid
11.5
14.0
ns
tP_KCLR
Key Counter, Clear to Output Active / High Z Delay
11.5
13.5
ns
tP_KF1F
Key Counter, Force 0x1F to Output Active / High Z Delay
10.5
12.5
ns
TRC
RapidConfigure Strobe Period
30.0
32.5
ns
tW+ -RC , tW- -RC
RapidConfigure Strobe Pulse Width
6.0
7.0
ns
tS-RC
RapidConfigure Address and Data Setup Time to Strobe
0.0
0.0
ns
tH-RC
RapidConfigure Address and Data Hold Time to Strobe
3.0
3.0
ns
tP-RC
RapidConfigure Strobe Falling Edge to Data Valid (Make Connection)
fJTAG
JTAG Clock (TCK) Frequency
tW-JTAG
JTAG Clock (TCK) Pulse Width
20.0
20.0
tS-JTAG
JTAG Setup Time
4.0
4.0
ns
tH-JTAG
JTAG Hold Time
0.0
0.0
ns
tP-JTAG
JTAG Clock to Output Data Valid
15.0
15.0
ns
2.0
13.0
10.0
6.0
ns
15.5
12.5
7.0
25
ns
ns
ns
0.0
26
ns
ns
27
28
35.0
37.5
ns
10
10
MHz
ns
29
Table 18. AC Electrical Specifications for IQX320 and IQX240B (Continued)
Notes:
(1) These parameters are guaranteed but not tested in production.
(2) The timing parameters are specified for a configuration where an Input Port is driving one Output Port. For configurations where an Input Port is
driving two or more Output Ports, the timing parameters are de-rated as shown in Section 5.7 or Table 20. These parameters are guaranteed but
not tested in production.
32
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IQX Family Data Sheet
5.6 AC Electrical Specifications for IQX160 and IQX128B
(TA = 0°C to 70°C, VDD = 5V±5%; V DD .PAD = 5V±5%, or V DD .PAD = 3.3V±10%. Assume two I/O Ports connected through the
Switch Matrix with 35 pF external loading.)
Speed Grade
Symbol
-7
Parameter
Min
-10
Max
Min
Ref.
Max Units Figure
fRIO
Register Input/Output, Clock Frequency(1, 2)
tW-RIO
Register Input/Output, Clock Pulse Width, Low or High(1, 2)
3.3
4.5
tS-RIO
Register Input/Output, Data Setup Time to CLK
2.0
3.0
ns
tH-RIO
Register Input/Output, CLK to Data Hold Time
0.0
0.0
ns
tCO-RIO
Register Input/Output, Clock to Output Data Valid
8.5
10.0
ns
fRI
Register Input, Clock Frequency(1)
100
80
MHz
133
100
MHz
ns
tW-RI
Register Input, Clock Pulse Width, Low or High
3.3
4.5
tS-RI
Register Input, Data Setup Time to CLK
2.0
3.0
ns
tH-RI
Register Input, CLK to Data Hold Time
0.0
0.0
ns
tCO-RI
Register Input, Clock to Output Data Valid
12.0
15.0
ns
fRO
Register Output, Clock Pulse Frequency (1)
133
100
MHz
ns
tW-RO
Register Output, Clock Width, Low or High
3.3
4.5
tS-RO
Register Output, Data Setup Time to CLK
3.0
4.0
ns
tH-RO
Register Output, CLK to Data Hold Time
0.0
0.0
ns
tCO-RO
Register Output, Clock to Output Data Valid
8.5
10.0
tPHL, tPLH
One Way Signal Propagation Delay
7.5
10.0
ns
∆tBR
Additional Delay in Bus Repeater (BR) Mode (1, 2)
0.0
0.0
ns
tSK
Skew Between Output Ports(1)
1.5
ns
tW+
Input Flow Through Positive Pulse Width(2)
3.5
4.5
ns
tW-
Input Flow Through Negative Pulse Width(2)
4.5
5.0
ns
RDATA
NRZ Data Rate (1, 2)
200
180
tPZH-IT, tPZL-IT
tPZH-OT, tPZL-OT
Input Enable (GT) to Data Valid
10.0
12.5
ns
Output Enable (GT) to Data Valid
9.0
10.0
ns
tPHZ-OT, tPLZ-OT
tW-LI
Output Enable (GT) to Output at High Z (1)
8.5
ns
tS-LI
Latch Input, Data Setup Time to Latch Enable (GC) Trailing Edge
2.0
3.0
ns
tH-LI
Latch Input, Data to Latch Enable (GC) Trailing Edge Hold Time
4.0
4.0
ns
tCO-LI
Latch Input, Latch Enable (GC) Leading Edge to Data Out Delay
tP-LIT
Latch Input, Transparent Mode Propagation Delay
tW-LO
Latch Output, Latch Enable (GC) Pulse Width, Low or High
tS-LO
Latch Output, Data Setup Time to Latch Enable (GC) Trailing Edge
4.0
5.0
ns
tH-LO
Latch Output, Data to Latch Enable (GC) Trailing Edge Hold Time
0.0
0.0
ns
tCO-LO
Latch Output, Latch Enable (GC) Leading Edge to Data Out Delay
tP-LOT
Latch Output, Transparent Mode Propagation Delay
tKW-RI
Register Input, Minimum Pulse Width of KEY as Clock Enable, Low or High
5.0
6.0
ns
tKS-RI
Register Input, Clock Enable (Key) Setup Time to CLK (GC)
2.5
3.0
ns
tKH-RI
Register Input, CLK (GC) to Clock Enable (Key) Hold Time
2.0
2.0
ns
tKCO-RI
Register Input, Key Clock to Output Data Valid
1.5
7.0
Latch Input, Latch Enable (GC) Pulse Width, Low or High
3.3
10.0
4.5
35.0
8.0
10.5
15
ns
16
Mb/s
17
18
ns
15.0
9.0
3.3
14
ns
4.5
12.0
13
19
ns
ns
ns
40.0
ns
10.0
ns
13.0
20
21
ns
Table 19. AC Electrical Specifications for IQX160 and IQX128B
June 2000
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IQX Family Data Sheet
Speed Grade
Symbol
-7
Parameter
Min
-10
Max
Min
Ref.
Max Units Figure
tKW-RO
Register Output, Minimum Pulse Width of KEY as Clock Enable, Low or High
5.0
6.0
ns
tKS-RO
Register Output, Clock Enable (Key) Setup Time to CLK (GC)
4.5
5.0
ns
tKH-RO
Register Output, CLK (GC) to Clock Enable (Key) Hold Time
0.0
0.0
ns
tKCO-RO
Register Output, Key Clock to Output Data Valid
6.5
7.5
ns
tKPZH-IT tKPZL-IT
Input Enable (Key) to Data Valid
9.0
11.0
ns
tKPZH-OT tKPZL-OT
Output Enable (Key) to Data Valid
7.5
9.0
ns
tKPHZ-OT tKPLZ-OT
Output Enable (Key) to Output at High Z(1)
9.0
ns
tKW-LI
Latch Input, Minimum Pulse Width of KEY as Latch Enable, Low or High
tKS-LI
Latch Input, Data Setup Time to Latch Enable (Key) Trailing Edge
2.5
3.0
ns
tKH-LI
Latch Input, Data to Latch Enable (Key) Trailing Edge Hold Time
2.0
2.0
ns
tKCO-LI
Latch Input, Latch Enable (Key) Leading Edge to Data Out
tKP-LIT
Latch Input, Transparent Mode Propagation Delay
tKW-LO
Latch Output, Minimum Pulse Width of KEY as Latch Enable, Low or High
5.0
6.0
ns
tKS-LO
Latch Output, Data Setup Time to Latch Enable (Key) Trailing Edge
4.5
5.0
ns
tKH-LO
Latch Output, Data to Latch Enable (Key) Trailing Edge Hold Time
0.0
0.0
tKCO-LO
Latch Output, Latch Enable (Key) Leading Edge to Data Out
6.5
7.5
tKP-LOT
Latch Output, Transparent Mode Propagation Delay
7.5
10.0
ns
fKCNT
Key Counter, Input Clock Frequency
80
66
MHz
tWKCNT
Key Counter Clock, Pulse Width
5.0
6.0
tS_KCKE
Key Counter, Enable Setup Time to KCLK
2.0
2.5
ns
tH_KCKE
Key Counter, KCLK to Enable Hold Time
0.0
0.0
ns
tS_KRST
Key Counter, Reset Setup Time to KCLK
2.0
2.5
ns
tH_KRST
Key Counter, KCLK to Reset Hold Time
0.0
0.0
ns
tKCLK_OE
Key Counter, Clock to Output Data Valid or Output High Z
tKCLK_IE
tP_KCLR
7.5
5.0
6.0
10.5
23
24
ns
13.0
7.5
22
10.0
25
ns
ns
ns
26
ns
ns
8.0
9.5
ns
Key Counter, Clock to Input Data Valid
9.5
11.5
ns
Key Counter, Clear to Output Active / High Z Delay
9.5
11.5
ns
tP_KF1F
Key Counter, Force 0x1F to Output Active / High Z Delay
8.5
10.5
ns
TRC
RapidConfigure Strobe Period
15.0
17.0
ns
tW+ -RC, tW- -RC
RapidConfigure Strobe Pulse Width
6.0
7.5
ns
tS-RC
RapidConfigure Address and Data Setup Time to Strobe
2.0
3.0
ns
tH-RC
RapidConfigure Address and Data Hold Time to Strobe
0.0
0.0
ns
tP-RC
RapidConfigure Strobe Falling Edge to Data Valid (Make Connection)
fJTAG
JTAG Clock (TCK) Frequency
tW-JTAG
JTAG Clock (TCK) Pulse Width
20.0
20.0
tS-JTAG
JTAG Setup Time
4.0
4.0
ns
tH-JTAG
JTAG Hold Time
0.0
0.0
ns
tP-JTAG
JTAG Clock to Output Data Valid
15.0
15.0
ns
25.0
30.0
ns
10
10
MHz
27
28
ns
29
Table 19. AC Electrical Specifications for IQX160 and IQX128B (Continued)
Notes:
(1) These parameters are guaranteed but not tested in production.
(2) The timing parameters are specified for a configuration where an Input Port is driving one Output Port. For configurations where an Input Port is
driving two or more Output Ports, the timing parameters are de-rated as shown in Section 5.7 or Table 20. These parameters are guaranteed but
not tested in production.
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IQX Family Data Sheet
5.7 Parameter De-rating For One-to-Many Connections
IQX320
Symbol
Parameter
IQX240B
IQX160
IQX128B
Min Max Min Max Min Max Min Max
Units
CNMAX
Maximum Number of Connections Per Input
-
32
-
32
-
32
-
32
∆tPD
Increase in tPD for Every Additional Output Port Connected to an Input Port
Increase in tw+ and tw- for Every Additional Output Port Connected to an
Input Port
-
0.35
-
0.35
-
0.25
-
0.25
ns
-
200
-
200
-
160
-
160
ps
Decrease in Maximum Operating Frequency Every Additional Output Port
Connected to an Input Port
-
1
-
1
-
0.75
-
0.75
MHz
∆tW
∆f
Table 20. Parameter De-rating For One-to-Many Connections
June 2000
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IQX Family Data Sheet
5.8 Test Circuit and Timing Diagrams
tF
Vin
D.U.T.
3.0V
90%
VDD.Pad
Pulse
Generator
tR
7.0V
Parameter Switch
Tested Position
tPLZ/tPZL Closed
500Ω
All Others
Vout
50Ω
Negative Pulse
500Ω
35pF*
1.5V
10%
0V
tW
Open
tF = 3 ns (max)
tR = 3 ns (max)
3.0V
90%
Positive Pulse
1.5V
10%
0V
tR
* Load capacitance includes jig and probe capacitance.
tF
Figure 12. Test Circuit and Waveform Definition
tW-RIO
tW-RIO
GC (CLK)
tS-RIO tH-RIO
RI
InPort
D
Switch
Matrix
Q
RO
D
Q
Out
Port
InPort
Dn
OutPort
CE
Dn+1
Dn-2
CE
CLK
Dn-1
Dn
tCO-RIO
Figure 13. Registered Input and Registered Output Mode Timing (ICLK, OCLK Synchronized)
tW-RI
tW-RI
GC (CLK)
tS-RI tH-RI
RI
InPort
D
Q
Switch
Matrix
InPort
OP
Dn
Dn+1
OutPort
OutPort
CLK
CE
Dn-1
Dn
Dn+1
tCO-RI
Figure 14. Registered Input Mode Timing
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IQX Family Data Sheet
tW-RO
tW-RO
GC (CLK)
tS-RO tH-RO
IN
RO
Switch
Matrix
InPort
D
InPort
Dn
Dn+1
Out Port
Q
OutPort
CLK
Dn-1
Dn
Dn+1
tCO-RO
CE
Figure 15. Registered Output Mode Timing
InPort 1
InPort 2
IN
OP
InPort 1
1.5V
tW+
tPLH
tPHL
tSK
tSK
OutPort 1
OutPort 1
Switch
Matrix
InPort 2
OutPort 2
OutPort 2
Figure 16. I/O Port Timing (Flow–through Mode)
GT (IE)
tPZH-IT
InPort
IE
InPort
IN
Switch
Matrix
tPZL-IT
OP
OutPort
OutPort
Figure 17. Input Enable Timing (Flow–through Mode)
June 2000
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IQX Family Data Sheet
GT (OE)
tPZH-OT
InPort
IN
Switch
Matrix
InPort
OP
tPZL-OT
OutPort
tPLZ-OT
VOH
VOH - 0.3V
OutPort
OE
tPHZ-OT
VOL
VOL +0.3V
Figure 18. Output Enable Timing (Flow–through Mode)
tH-LI
tS-LI
GC (CLK)
tW-LI
InPort
LI
InPort
D
CLK
Q
Switch
Matrix
OP
tP-LIT
OutPort
OutPort
LE
tCO-LI
Figure 19. Latched Input Mode Timing
tH-LO
tS-LO
GC (CLK)
tW-LO
InPort
IN
InPort
CLK
LO
Switch
Matrix
D
tP-LOT
Q
OutPort
OutPort
LE
tCO-LO
Figure 20. Latched Output Mode Timing
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IQX Family Data Sheet
GC (CLK)
tKH-RI
tKS-RI
KEY (CKE )
Valid
tKW-RI
RI
InPort
D
Switch
Matrix
Q
OP
InPort
OutPort
tKCO-RI
CLK
CKE
OutPort
CE
Figure 21. Key Timing for Register Input, Clock Enable (CKE)
GC (CLK)
tKH-RO
tKS-RO
KEY (CKE)
Valid
tKW-RO
IN
RO
Switch
Matrix
InPort
D
InPort
tKCO-RO
OutPort
Q
CLK
OutPort
CKE
CE
Figure 22. Key Timing for Register Output, Clock Enable (CKE)
Key (IE)
Valid
tKPZH-IT
InPort
IE
InPort
IN
Switch
Matrix
Valid
tKPZL-IT
OP
OutPort
OutPort
Figure 23. Key Timing for Input Enable
June 2000
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IQX Family Data Sheet
Key (OE)
Valid
Valid
InPort
IN
InPort
Switch
Matrix
OP
tKPZL-OT
OutPort
tKPHZ-OT
tKPZH-OT
tKPLZ-OT
VOH
VOH - 0.3V
OutPort
OE
VOL
VOL +0.3V
Figure 24. Key Timing for Output Enable
GC (CLK)
KEY (CKE)
Valid
tKH-LI
tKS-LI
InPort
LI
InPort
D
Q
Switch OP
Matrix
OutPort
tKP-LIT
OutPort
CKE
LE
tKCO-LI
CLK
Figure 25. Key Timing for Latch Input, Enable (CKE)
GC (CLK)
KEY (CKE)
Valid
tKH-LO
tKS-LO
InPort
IN
InPort
Switch
Matrix
tKP-LOT
LO
D
Q
OutPort
OutPort
CKE
LE
tKCO-LO
CLK
Figure 26. Key Timing for Latch Output, Enable (CKE)
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IQX Family Data Sheet
K0/KCLK
a
K1/KCKE
tS_KCKE
b
c
d
e
f
g
h
j
m
n
p
r
t
tH_KCKE
tS_KRST
K2/KRST
tH_KRST
K3/KCLR
K4/K1F
0
Key Bus (Internal)
IN
InPort1
Switch
Matrix
TG1*
TG2*
OP
tKCLK_OE
OutPort1
OutPort1
OE
tKCLK_OE
tKCLK_OE
VOL
IE
InPort2
IN
OP
Switch
Matrix
TG1*
0
1
0
1
2
1F
tKCLK_OE
VOH
VOH - 0.3V
VOL + 0.3V
InPort2
OutPort2
tKCLK_IE
tKCLK_IE
OutPort2
* TG1 and TG2 are the 5-bit tag values programmed in the I/O Ports OutPort1 and InPort2 respectively.
Figure 27. Key Counter Timing
TRC
tW+RC
tW-RC
STROBE
tH-RC
tS-RC
RA[7:0]
CA[3:0]
tS-RC
tS-RC
tH-RC
P/S, C1, C0
tS-RC
tH-RC
WE
tP-RC
Output Port
Make
Connection
Break
Connection
Figure 28. RapidConfigure Timing
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IQX Family Data Sheet
tW-JTAG
tW-JTAG
TCK
tS-JTAG tH-JTAG
TDI, TMS
tP-JTAG
TDO
Figure 29. JTAG Timing
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IQX Family Data Sheet
6.0 PINOUT
6.1 IQX320 [PBGA/416L] Package Pinout by Name
Name Pin#
GC0
E2
GC1
D1
GC2
E3
GC3
C3
GT0
D22
GT1
E24
GT2
AB5
GT3
AA5
GT4
D2
P000
D5
P001
E14
P002
E6
P003
E11
P004
D6
P005
E9
P006
E8
P007
C6
P008
E7
P009
B6
P010
D7
P011
C7
P012
E10
P013
B7
P014
D9
P015
A7
P016
D8
P017
C8
P018 D10
P019
B8
P020 C10
P021
C9
P022
D11
P023
B9
P024
C11
P025
A9
P026
E12
P027
B10
P028 D12
P029
B11
P030 C12
P031
B12
P032
E13
P033
A13
P034 D13
P035
B14
P036 C14
P037
A15
P038 D14
P039
B16
P040 C15
P041
B17
P042 D15
Name
P043
P044
P045
P046
P047
P048
P049
P050
P051
P052
P053
P054
P055
P056
P057
P058
P059
P060
P061
P062
P063
P064
P065
P066
P067
P068
P069
P070
P071
P072
P073
P074
P075
P076
P077
P078
P079
P080
P081
P082
P083
P084
P085
P086
P087
P088
P089
P090
P091
P092
P093
P094
Pin#
A18
E15
B18
C16
C18
D16
B19
E16
C19
C17
B20
D17
C20
E17
A21
D18
B21
D19
C21
E18
B22
E19
C22
D20
B23
E20
A24
D21
C23
E21
B24
E22
C25
C24
D25
E23
C26
F24
D26
G23
E25
G24
D27
H23
E26
H24
F25
J23
F26
J24
G25
K23
Name
P095
P096
P097
P098
P099
P100
P101
P102
P103
P104
P105
P106
P107
P108
P109
P110
P111
P112
P113
P114
P115
P116
P117
P118
P119
P120
P121
P122
P123
P124
P125
P126
P127
P128
P129
P130
P131
P132
P133
P134
P135
P136
P137
P138
P139
P140
P141
P142
P143
P144
P145
P146
Pin#
G26
K24
G27
K25
H25
L23
H26
L24
J25
L25
J26
M25
J27
M23
K26
M24
L26
N23
M26
N24
N27
P25
N26
P23
R26
P24
R27
R25
T26
R24
U26
R23
V27
T25
V26
T24
V25
T23
W26
U25
W25
U24
X26
V24
X25
W24
Y27
V23
Y26
Y24
Y25
X23
Name
P147
P148
P149
P150
P151
P152
P153
P154
P155
P156
P157
P158
P159
P160
P161
P162
P163
P164
P165
P166
P167
P168
P169
P170
P171
P172
P173
P174
P175
P176
P177
P178
P179
P180
P181
P182
P183
P184
P185
P186
P187
P188
P189
P190
P191
P192
P193
P194
P195
P196
P197
P198
Pin#
AA26
W23
AA25
Y23
AC27
U23
AB25
AA24
AC26
AA23
AD25
AB23
AC25
AB22
AD24
AC23
AE25
AB21
AE24
AC22
AD23
AC21
AF24
AB20
AE23
AC20
AD22
AB19
AE22
AC19
AD21
AB18
AE21
AC18
AF21
AD18
AD20
AB17
AE20
AC17
AD19
AD17
AE19
AB16
AF19
AC16
AE18
AD16
AE17
AC15
AE16
AB15
Name
P199
P200
P201
P202
P203
P204
P205
P206
P207
P208
P209
P210
P211
P212
P213
P214
P215
P216
P217
P218
P219
P220
P221
P222
P223
P224
P225
P226
P227
P228
P229
P230
P231
P232
P233
P234
P235
P236
P237
P238
P239
P240
P241
P242
P243
P244
P245
P246
P247
P248
P249
P250
Pin#
AF15
AD14
AE15
AB14
AE14
AC14
AE13
AD13
AE12
AC13
AE11
AB13
AF10
AC12
AE10
AB12
AD10
AC11
AE9
AC10
AD9
AC9
AE8
AB11
AD8
AC8
AF7
AB10
AE7
AB8
AD7
AB9
AE6
AB7
AD6
AC7
AE5
AC6
AF4
AB6
AD5
AC5
AE4
AD3
AD4
AB4
AC3
AA4
AD2
Y5
AC2
Y4
Name
P251
P252
P253
P254
P255
P256
P257
P258
P259
P260/GT12
P261/GT11
P262
P263/GT10
P264
P265/GT9
P266
P267/GT8
P268/GC12
P269/GC11
P270/GC10
P271/GC9
P272/GC8
P273/K4
P274
P275/K3
P276
P277/K2
P278
P279/K1
P280
P281/K0
P282
P283/GC7
P284
P285/GC6
P286
P287/GC5
P288
P289/GC4
P290
P291GT7
P292
P293/GT6
P294
P295/GT5
P296/CA0
P297/CA1
P298/CA2
P299/CA3
P300/CA4
P301/CA5
P302/CA6
Pin#
AB3
X5
AC1
X4
AB2
W5
AA3
W4
AA2
V5
Y3
V4
Y2
V3
Y1
U5
X3
U4
X2
U3
W3
T5
W1
T4
V2
T3
U2
R4
T2
R5
R1
P3
P2
P4
N1
N3
M2
P5
L2
N4
K1
M3
K2
L3
K3
N5
J2
M5
J3
M4
H2
L4
Name
P303/CA7
P304/CA8
P305
P306/RA0
P307/RA1
P308/RA2
P309/RA3
P310/RA4
P311/RA5
P312/RA6
P313/RA7
P314/RA8
P315/P/S
P316/C0
P317/C1
P318/WE
P319/STROBE
RCE
TCK
TDI
TDO
TMS
TRST*
VDD
VDD
VDD
VDD
VDD.PAD1
VDD.PAD1
VDD.PAD1
VDD.PAD1
VDD.PAD1
VDD.PAD1
VDD.PAD1
VDD.PAD1
VDD.PAD2
VDD.PAD2
VDD.PAD2
VDD.PAD2
VDD.PAD2
VDD.PAD2
VDD.PAD2
VDD.PAD2
VDD.PAD2
VDD.PAD3
VDD.PAD3
VDD.PAD3
VDD.PAD3
VDD.PAD3
VDD.PAD3
VDD.PAD3
VDD.PAD3
Pin#
H3
L5
G1
K4
G2
K5
G3
J4
F2
J5
H5
G4
G5
F4
F5
E5
D3
C4
A4
B3
C5
B4
B5
A19
H27
W2
AD12
A5
A8
A10
A14
A23
B13
B15
C13
E27
F23
K27
N25
P26
P27
W27
X24
AB27
AD11
AD15
AF5
AF9
AF13
AF14
AF18
AF20
Name
VDD.PAD3
VDD.PAD4
VDD.PAD4
VDD.PAD4
VDD.PAD4
VDD.PAD4
VDD.PAD4
VDD.PAD4
VDD.PAD4
VDD.PAD4
VDD.PAD4
VDD.X
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Pin#
AF23
E1
H4
J1
N2
P1
R2
R3
V1
X1
AB1
F3
A6
A11
A12
A16
A17
A20
A22
AA1
AA27
AB24
AB26
AC4
AC24
AD26
AE3
AF6
AF8
AF11
AF12
AF16
AF17
AF22
B25
C2
D4
D23
D24
E4
F1
F27
H1
L1
L27
M1
M27
T1
T27
U1
U27
X27
Table 21. IQX320 [PBGA/416L] Package Pinout by Name
June 2000
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IQX Family Data Sheet
6.2 IQX320 [PBGA/416L] Package Pinout by Location
Pin#
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
C2
C3
C4
C5
C6
C7
C8
C9
C10
Name
TCK
VDD.PAD1
VSS
P015
VDD.PAD1
P025
VDD.PAD1
VSS
VSS
P033
VDD.PAD1
P037
VSS
VSS
P043
VDD
VSS
P057
VSS
VDD.PAD1
P069
TDI
TMS
TRST*
P009
P013
P019
P023
P027
P029
P031
VDD.PAD1
P035
VDD.PAD1
P039
P041
P045
P049
P053
P059
P063
P067
P073
VSS
VSS
GC3
RCE
TDO
P007
P011
P017
P021
P020
Pin#
Name
Pin# Name Pin#
C11
P024
E11
P003
J24
C12
P030
E12
P026
J25
C13
VDD.PAD1
E13
P032
J26
C14
P036
E14
P001
J27
C15
P040
E15
P044
K1
C16
P046
E16
P050
K2
C17
P052
E17
P056
K3
C18
P047
E18
P062
K4
C19
P051
E19
P064
K5
C20
P055
E20
P068
K23
C21
P061
E21
P072
K24
C22
P065
E22
P074
K25
C23
P071
E23
P078
K26
C24
P076
E24
GT1
K27
C25
P075
E25
P083
L1
C26
P079
E26
P087
L2
D1
GC1
E27 VDD.PAD2
L3
L4
D2
GT4
F1
VSS
D3 P319/STROBE
F2
P311/RA5
L5
D4
VSS
F3
VDD.X
L23
D5
P000
F4
P316/C0
L24
D6
P004
F5
P317/C1
L25
D7
P010
F23 VDD.PAD2 L26
D8
P016
F24
P080
L27
D9
P014
F25
P089
M1
D10
P018
F26
P091
M2
M3
D11
P022
F27
VSS
D12
P028
G1
P305
M4
D13
P034
G2 P307/RA1 M5
D14
P038
G3 P309/RA3 M23
D15
P042
G4 P314/RA8 M24
D16
P048
G5
P315/P/S M25
D17
P054
G23
P082
M26
D18
P058
G24
P084
M27
D19
P060
G25
P093
N1
D20
P066
G26
P095
N2
D21
P070
G27
P097
N3
D22
GT0
H1
VSS
N4
D23
VSS
H2 P301/CA5 N5
H3 P303/CA7 N23
D24
VSS
D25
P077
H4 VDD.PAD4 N24
D26
P081
H5 P313/RA7 N25
D27
P085
H23
P086
N26
E1
VDD.PAD4
H24
P088
N27
E2
GC0
H25
P099
P1
E3
GC2
H26
P101
P2
H27
VDD
P3
E4
VSS
J1
VDD.PAD4 P4
E5
P318/WE
E6
P002
J2
P297/CA1
P5
E7
P008
J3
P299/CA3 P23
E8
P006
J4
P310/RA4 P24
E9
P005
J5
P312/RA6 P25
E10
P012
J23
P090
P26
Name
P092
P103
P105
P107
P291/GT7
P293/GT6
P295/GT5
P306/RA0
P308/RA2
P094
P096
P098
P109
VDD.PAD2
VSS
P289/GC4
P294
P302/CA6
P304/CA8
P100
P102
P104
P111
VSS
VSS
P287/GC5
P292
P300/CA4
P298/CA2
P108
P110
P106
P113
VSS
P285/GC6
VDD.PAD4
P286
P290
P296/CA0
P112
P114
VDD.PAD2
P117
P115
VDD.PAD4
P283/GC7
P282
P284
P288
P118
P120
P116
VDD.PAD2
Pin#
P27
R1
R2
R3
R4
R5
R23
R24
R25
R26
R27
T1
T2
T3
T4
T5
T23
T24
T25
T26
T27
U1
U2
U3
U4
U5
U23
U24
U25
U26
U27
V1
V2
V3
V4
V5
V23
V24
V25
V26
V27
W1
W2
W3
W4
W5
W23
W24
W25
W26
W27
X1
X2
Name
VDD.PAD2
P281/K0
VDD.PAD4
VDD.PAD4
P278
P280
P126
P124
P122
P119
P121
VSS
P279/K1
P276
P274
P272/GC8
P132
P130
P128
P123
VSS
VSS
P277/K2
P270/GC10
P268/GC12
P266
P152
P136
P134
P125
VSS
VDD.PAD4
P275/K3
P264
P262
P260/GT12
P142
P138
P131
P129
P127
P273/K4
VDD
P271/GC9
P258
P256
P148
P140
P135
P133
VDD.PAD2
VDD.PAD4
P269/GC11
Pin#
X3
X4
X5
X23
X24
X25
X26
X27
Y1
Y2
Y3
Y4
Y5
Y23
Y24
Y25
Y26
Y27
AA1
AA2
AA3
AA4
AA5
AA23
AA24
AA25
AA26
AA27
AB1
AB2
AB3
AB4
AB5
AB6
AB7
AB8
AB9
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AB24
AB25
Name
P267/GT8
P254
P252
P146
VDD.PAD2
P139
P137
VSS
P265/GT9
P263/GT10
P261/GT11
P250
P248
P150
P144
P145
P143
P141
VSS
P259
P257
P246
GT3
P156
P154
P149
P147
VSS
VDD.PAD4
P255
P251
P244
GT2
P238
P232
P228
P230
P226
P222
P214
P210
P202
P198
P190
P184
P178
P174
P170
P164
P160
P158
VSS
P153
Pin# Name
AB26
VSS
AB27 VDD.PAD2
AC1
P253
AC2
P249
AC3
P245
AC4
VSS
AC5
P240
AC6
P236
AC7
P234
AC8
P224
AC9
P220
AC10
P218
AC11
P216
AC12
P212
AC13
P208
AC14
P204
AC15
P196
AC16
P192
AC17
P186
AC18
P180
AC19
P176
AC20
P172
AC21
P168
AC22
P166
AC23
P162
AC24
VSS
AC25
P159
AC26
P155
AC27
P151
AD2
P247
AD3
P242
AD4
P243
AD5
P239
AD6
P233
AD7
P229
AD8
P223
AD9
P219
AD10
P215
AD11 VDD.PAD3
AD12
VDD
AD13
P206
AD14
P200
AD15 VDD.PAD3
AD16
P194
AD17
P188
AD18
P182
AD19
P187
AD20
P183
AD21
P177
AD22
P173
AD23
P167
AD24
P161
AD25
P157
Pin#
AD26
AE3
AE4
AE5
AE6
AE7
AE8
AE9
AE10
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
AF16
AF17
AF18
AF19
AF20
AF21
AF22
AF23
AF24
Name
VSS
VSS
P241
P235
P231
P227
P221
P217
P213
P209
P207
P205
P203
P201
P197
P195
P193
P189
P185
P179
P175
P171
P165
P163
P237
VDD.PAD3
VSS
P225
VSS
VDD.PAD3
P211
VSS
VSS
VDD.PAD3
VDD.PAD3
P199
VSS
VSS
VDD.PAD3
P191
VDD.PAD3
P181
VSS
VDD.PAD3
P169
Table 22. IQX320 [PBGA/416L] Package Pinout by Location
44
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June 2000
IQX Family Data Sheet
6.3 IQX320 [PBGA/416L] Package Footprint
AF AE AD AC AB AA
1
2
3
Y
P253 VDD4 VSS P265
/
P247 P249 P255 P259 P263
/
VSS P242 P245 P251 P257 P261
/
P237 P241 P243 VSS P244 P246 P250
X
W
V
U
T
R
P
N
M
L
K
J
H
VDD4 P273/ VDD4 VSS VSS P281/ VDD4 P285/ VSS VSS P291/ VDD4 VSS
P269/ VDD P275/ P277
/
P267/ P271/ P264 P270
/
P254 P258 P262 P268
/
GT3 P248 P252 P256 P260/ P266
G
F
P305 VSS
P279 VDD4 P283/ VDD4 P287 P289 P293/ P297/ P301/ P307
/
/
/
/
P276 VDD4 P282 P286 P292 P294 P295/ P299/ P303/ P309
/
P274 P278 P284 P290 P300 P302 P306/ P310/ VDD4 P314
/
/
/
P272 P280 P288 P296/ P298 P304 P308/ P312/ P313/ P315
/
/
/
/
P311/
E
D
C
B
A
VDD4 GC1
1
GC0
2
VDD.X GC2
GT4 VSS
P319 GC3 TDI
3
/
VSS RCE TMS TCK 4
P316/
VSS
P317/
P231 P233 P236 P238
P318/ P000 TDO TRST VDD1 5
*
P002 P004 P007 P009 VSS 6
7 P225 P227 P229 P234 P232
P008 P010 P011 P013 P015 7
8 VSS
P221 P223 P224 P228
P006 P016 P017 P019 VDD1 8
9 VDD3 P217 P219 P220 P230
P005 P014 P021 P023 P025 9
10 P211 P213 P215 P218 P226
P012 P018 P020 P027 VDD1 10
11 VSS
P209 VDD3 P216 P222
P003 P022 P024 P029 VSS
11
12 VSS
P207 VDD P212 P214
P026 P028 P030 P031 VSS
12
4
5 VDD3 P235 P239 P240 GT2
6 VSS
13 VDD3 P205 P206 P208 P210
P032 P034 VDD1 VDD1 P033 13
14 VDD3 P203 P200 P204 P202
P001 P038 P036 P035 VDD1 14
15 P199 P201 VDD3 P196 P198
P044 P042 P040 VDD1 P037 15
16 VSS
P197 P194 P192 P190
P050 P048 P046 P039 VSS
16
17 VSS
P195 P188 P186 P184
P056 P054 P052 P041 VSS
17
18 VDD3 P193 P182 P180 P178
P062 P058 P047 P045 P043 18
19 P191 P189 P187 P176 P174
P064 P060 P051 P049 VDD 19
20 VDD3 P185 P183 P172 P170
P068 P066 P055 P053 VSS
21 P181 P179 P177 P168 P164
P072 P070 P061 P059 P057 21
22 VSS
P074 GT0 P065 P063 VSS
P175 P173 P166 P160
20
22
23 VDD3 P171 P167 P162 P158 P156 P150 P146 P148 P142 P152 P132 P126 P118 P112 P108 P100 P094 P090 P086 P082 VDD2 P078 VSS P071 P067 VDD1 23
24 P169 P165 P161 VSS VSS
P154 P144 VDD2 P140 P138 P136 P130 P124 P120 P114 P110 P102 P096 P092 P088 P084 P080
P163 P157 P159 P153 P149 P145 P139 P135 P131 P134 P128 P122 P116 VDD2 P106 P104 P098 P103 P099 P093 P089
25
VSS
26
P155 VSS
P147 P143 P137 P133 P129 P125 P123 P119 VDD2 P117 P113 P111 P109 P105 P101 P095 P091
P151 VDD2 VSS P141 VSS
27
AF AE AD AC AB AA
Y
X
VDD2 P127 VSS VSS P121 VDD2 P115 VSS VSS VDD2 P107 VDD P097 VSS
W
V
U
T
R
P
N
M
L
K
J
H
G
F
GT1
VSS P076 P073 P069 24
P083 P077 P075 VSS
25
P087 P081 P079
26
VDD2 P085
27
E
D
C
B
A
Figure 30. IQX320 [PBGA/416L] Package Footprint
Notes:
(1)
(2)
(3)
(4)
(5)
VDD1 - VDD.PAD1
VDD2 - VDD.PAD2
VDD3 - VDD.PAD3
VDD4 - VDD.PAD4
Pxxx/ - Port is dual function
June 2000
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Revision 5.0
45
IQX Family Data Sheet
6.4 IQX240B [PQFP/304L] Package Pinout by Name
Name
Pin#
Name
Pin#
Name
Pin#
Name
Pin#
Name
Pin#
Name
Pin#
Name
Pin#
Name
Pin#
GC0
12
P029
262
P067
215
P105
171
P143
125
P181
78
P219/CA3
30
VDD.PAD2
178
GC1
9
P030
261
P068
214
P106
170
P144
124
P182
75
P220/CA4
29
VDD.PAD2
192
GC2
7
P031
260
P069
213
P107
169
P145
123
P183
74
P221/CA5
27
VDD.PAD2
221
GC3
3
P032
259
P070
212
P108
168
P146
122
P184
73
P222/CA6
26
VDD.PAD3
84
GT0
229
P033
258
P071
209
P109
167
P147
121
P185
72
P223/CA7
25
VDD.PAD3
147
GT1
228
P034
257
P072
208
P110
164
P148
120
P186
70
P224/CA8
24
VDD.PAD3
101
GT2
77
P035
256
P073
207
P111
163
P149
117
P187
69
P225
23
VDD.PAD3
119
GT3
76
P036
255
P074
206
P112
162
P150
116
P188
68
P226/RA0
22
VDD.PAD3
131
GT4
5
P037
254
P075
205
P113
161
P151
115
P189
67
P227/RA1
19
VDD.PAD4
20
P000
303
P038
251
P076
204
P114
160
P152
114
P190
66
P228/RA2
18
VDD.PAD4
35
P001
300
P039
250
P077
203
P115
157
P153
111
P191
65
P229/RA3
17
VDD.PAD4
48
P002
295
P040
249
P078
202
P116
156
P154
110
P192
64
P230/RA4
16
VDD.PAD4
60
P003
293
P041
248
P079
201
P117
155
P155
109
P193
63
P231/RA5
15
VDD.X
28
P004
292
P042
247
P080
200
P118
154
P156
108
P194/GT12
62
P232/RA6
14
VSS
10
P005
291
P043
246
P081
199
P119
153
P157
107
P195/GT11
59
P233/RA7
13
VSS
21
P006
290
P044
245
P082
198
P120
152
P158
106
P196/GT10
58
P234/RA8
11
VSS
36
P007
288
P045
244
P083
197
P121
151
P159
105
P197/GT9
57
P235/P/S
8
VSS
49
P008
287
P046
243
P084
196
P122
150
P160
104
P198/GT8
55
P236/C0
6
VSS
61
P009
286
P047
240
P085
195
P123
149
P161
103 P199/GC12
54
P237/C1
4
VSS
71
P010
285
P048
239
P086
194
P124
148
P162
102 P200/GC11
53
P238/WE
2
VSS
83
P011
284
P049
238
P087
191
P125
145
P163
99
P201/GC10
52
P239/STROBE
1
VSS
90
P012
283
P050
237
P088
190
P126
144
P164
98
P202/GC9
51
RCE
304
VSS
100
P013
282
P051
236
P089
189
P127
143
P165
97
P203/GC8
50
TCK
298
VSS
112
P014
281
P052
234
P090
188
P128
142
P166
96
P204/K4
47
TDI
302
VSS
118
P015
280
P053
233
P091
187
P129
141
P167
95
P205/K3
46
TDO
299
VSS
130
P016
277
P054
232
P092
186
P130
140
P168
94
P206/K2
45
TMS
301
VSS
146
P017
276
P055
231
P093
185
P131
139
P169
93
P207/K1
44
TRST*
294
VSS
159
P018
275
P056
230
P094
184
P132
138
P170
92
P208/K0
43
VDD
56
VSS
166
P019
274
P057
227
P095
183
P133
137
P171
91
P209/GC7
42
VDD
113
VSS
179
P020
273
P058
226
P096
182
P134
136
P172
89
P210/GC6
41
VDD
210
VSS
193
P021
272
P059
225
P097
181
P135
135
P173
88
P211/GC5
40
VDD
242
VSS
211
P022
271
P060
224
P098
180
P136
134
P174
87
P212/GC4
39
VDD.PAD1
235
VSS
222
P023
270
P061
223
P099
177
P137
133
P175
86
P213/GT7
38
VDD.PAD1
253
VSS
241
P024
269
P062
220
P100
176
P138
132
P176
85
P214/GT6
37
VDD.PAD1
267
VSS
252
P025
268
P063
219
P101
175
P139
129
P177
82
P215/GT5
34
VDD.PAD1
279
VSS
266
P026
265
P064
218
P102
174
P140
128
P178
81
P216/CA0
33
VDD.PAD1
297
VSS
278
P027
264
P065
217
P103
173
P141
127
P179
80
P217/CA1
32
VDD.PAD2
158
VSS
289
P028
263
P066
216
P104
172
P142
126
P180
79
P218/CA2
31
VDD.PAD2
165
VSS
296
Table 23. IQX240B [PQFP/304L] Package Pinout by Name
46
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Revision 5.0
June 2000
IQX Family Data Sheet
6.5 IQX240B [PQFP/304L] Package Pinout by Location
Pin#
Name
Pin#
Name
Pin#
Name
Pin#
Name
Pin#
Name
Pin#
Name
Pin#
Name
Pin#
Name
1
P239/STROBE
39
P212/GC4
77
GT2
115
P151
153
P119
191
P087
229
GT0
267
VDD.PAD1
2
P238/WE
40
P211/GC5
78
P181
116
P150
154
P118
192
VDD.PAD2
230
P056
268
P025
3
GC3
41
P210/GC6
79
P180
117
P149
155
P117
193
VSS
231
P055
269
P024
P023
4
P237/C1
42
P209/GC7
80
P179
118
VSS
156
P116
194
P086
232
P054
270
5
GT4
43
P208/K0
81
P178
119
VDD.PAD3
157
P115
195
P085
233
P053
271
P022
6
P236/C0
44
P207/K1
82
P177
120
P148
158
VDD.PAD2
196
P084
234
P052
272
P021
7
GC2
45
P206/K2
83
VSS
121
P147
159
VSS
197
P083
235
VDD.PAD1
273
P020
8
P235/P/S
46
P205/K3
84
VDD.PAD3
122
P146
160
P114
198
P082
236
P051
274
P019
9
GC1
47
P204/K4
85
P176
123
P145
161
P113
199
P081
237
P050
275
P018
10
VSS
48
VDD.PAD4
86
P175
124
P144
162
P112
200
P080
238
P049
276
P017
P016
11
P234/RA8
49
VSS
87
P174
125
P143
163
P111
201
P079
239
P048
277
12
GC0
50
P203/GC8
88
P173
126
P142
164
P110
202
P078
240
P047
278
VSS
13
P233/RA7
51
P202/GC9
89
P172
127
P141
165
VDD.PAD2
203
P077
241
VSS
279
VDD.PAD1
P015
14
P232/RA6
52
P201/GC10
90
VSS
128
P140
166
VSS
204
P076
242
VDD
280
15
P231/RA5
53
P200/GC11
91
P171
129
P139
167
P109
205
P075
243
P046
281
P014
16
P230/RA4
54
P199/GC12
92
P170
130
VSS
168
P108
206
P074
244
P045
282
P013
17
P229/RA3
55
P198/GT8
93
P169
131
VDD.PAD3
169
P107
207
P073
245
P044
283
P012
18
P228/RA2
56
VDD
94
P168
132
P138
170
P106
208
P072
246
P043
284
P011
19
P227/RA1
57
P197/GT9
95
P167
133
P137
171
P105
209
P071
247
P042
285
P010
20
VDD.PAD4
58
P196/GT10
96
P166
134
P136
172
P104
210
VDD
248
P041
286
P009
21
VSS
59
P195/GT11
97
P165
135
P135
173
P103
211
VSS
249
P040
287
P008
22
P226/RA0
60
VDD.PAD4
98
P164
136
P134
174
P102
212
P070
250
P039
288
P007
23
P225
61
VSS
99
P163
137
P133
175
P101
213
P069
251
P038
289
VSS
24
P224/CA8
62
P194/GT12
100
VSS
138
P132
176
P100
214
P068
252
VSS
290
P006
25
P223/CA7
63
P193
101
VDD.PAD3
139
P131
177
P099
215
P067
253
VDD.PAD1
291
P005
26
P222/CA6
64
P192
102
P162
140
P130
178
VDD.PAD2
216
P066
254
P037
292
P004
27
P221/CA5
65
P191
103
P161
141
P129
179
VSS
217
P065
255
P036
293
P003
28
VDD.X
66
P190
104
P160
142
P128
180
P098
218
P064
256
P035
294
TRST*
29
P220/CA4
67
P189
105
P159
143
P127
181
P097
219
P063
257
P034
295
P002
30
P219/CA3
68
P188
106
P158
144
P126
182
P096
220
P062
258
P033
296
VSS
31
P218/CA2
69
P187
107
P157
145
P125
183
P095
221
VDD.PAD2
259
P032
297
VDD.PAD1
32
P217/CA1
70
P186
108
P156
146
VSS
184
P094
222
VSS
260
P031
298
TCK
33
P216/CA0
71
VSS
109
P155
147
VDD.PAD3
185
P093
223
P061
261
P030
299
TDO
34
P215/GT5
72
P185
110
P154
148
P124
186
P092
224
P060
262
P029
300
P001
35
VDD.PAD4
73
P184
111
P153
149
P123
187
P091
225
P059
263
P028
301
TMS
36
VSS
74
P183
112
VSS
150
P122
188
P090
226
P058
264
P027
302
TDI
37
P214/GT6
75
P182
113
VDD
151
P121
189
P089
227
P057
265
P026
303
P000
38
P213/GT7
76
GT3
114
P152
152
P120
190
P088
228
GT1
266
VSS
304
RCE
Table 24. IQX240B [PQFP/304L] Package Pinout by Location
June 2000
Powered by ICminer.com Electronic-Library Service CopyRight 2003
Revision 5.0
47
IQX Family Data Sheet
Top View
I/O Ports Powered by VDD.PAD2
I/O Ports Powered by VDD.PAD4
I/O Ports Powered by VDD.PAD1
I/O Ports Powered by VDD.PAD3
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172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
GT1
P057
P058
P059
P060
P061
VSS
VDD.PAD2
P062
P063
P064
P065
P066
P067
P068
P069
P070
VSS
VDD
P071
P072
P073
P074
P075
P076
P077
P078
P079
P080
P081
P082
P083
P084
P085
P086
VSS
VDD.PAD2
P087
P088
P089
P090
P091
P092
P093
P094
P095
P096
P097
P098
VSS
VDD.PAD2
P099
P100
P101
P102
P103
P104
P105
P106
P107
P108
P109
VSS
VDD.PAD2
P110
P111
P112
P113
P114
VSS
VDD.PAD2
P115
P116
P117
P118
P119
VDD.PAD3
P176
P175
P174
P173
P172
VSS
P171
P170
P169
P168
P167
P166
P165
P164
P163
VSS
VDD.PAD3
P162
P161
P160
P159
P158
P157
P156
P155
P154
P153
VSS
VDD
P152
P151
P150
P149
VSS
VDD.PAD3
P148
P147
P146
P145
P144
P143
P142
P141
P140
P139
VSS
VDD.PAD3
P138
P137
P136
P135
P134
P133
P132
P131
P130
P129
P128
P127
P126
P125
VSS
VDD.PAD3
P124
P123
P122
P121
P120
GT2
P181
P180
P179
P178
P177
VSS
239/STROBE
P238/WE
GC3
P237/C1
GT4
P236/C0
GC2
P235/ P/S
GC1
VSS
P234/RA8
GC0
P233/RA7
P232/RA6
P231/RA5
P230/RA4
P229/RA3
P228/RA2
P227/RA1
VDD.PAD4
VSS
P226/RA0
P225
P224/CA8
P223/CA7
P222/CA6
P221/CA5
VDD.X
P220/CA4
P219/CA3
P218/CA2
P217/CA1
P216/CA0
P215/GT5
VDD.PAD4
VSS
P214/GT6
P213/GT7
P212/GC4
P211/GC5
P210/GC6
P209/GC7
P208/K0
P207/K1
P206/K2
P205/K3
P204/K4
VDD.PAD4
VSS
P203/GC8
P202/GC9
P201/GC10
P200/GC11
P199/GC12
P198/GT8
VDD
P197/GT9
P196/GT10
P195/GT11
VDD.PAD4
VSS
P194/GT12
P193
P192
P191
P190
P189
P188
P187
P186
VSS
P185
P184
P183
P182
GT3
304
303
302
301
300
299
298
297
296
295
294
293
292
291
290
289
288
287
286
285
284
283
282
281
280
279
278
277
276
275
274
273
272
271
270
269
268
267
266
265
264
263
262
261
260
259
258
257
256
255
254
253
252
251
250
249
248
247
246
245
244
243
242
241
240
239
238
237
236
235
234
233
232
231
230
229
RCE
P000
TDI
TMS
P001
TDO
TCK
VDD.PAD1
VSS
P002
TRST*
P003
P004
P005
P006
VSS
P007
P008
P009
P010
P011
P012
P013
P014
P015
VDD.PAD1
VSS
P016
P017
P018
P019
P020
P021
P022
P023
P024
P025
VDD.PAD1
VSS
P026
P027
P028
P029
P030
P031
P032
P033
P034
P035
P036
P037
VDD.PAD1
VSS
P038
P039
P040
P041
P042
P043
P044
P045
P046
VDD
VSS
P047
P048
P049
P050
P051
VDD.PAD1
P052
P053
P054
P055
P056
GT0
6.6 IQX240B [PQFP/304L] Package Pinout
Figure 31. IQX240B [PQFP/304L] Package Pinout
48
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June 2000
IQX Family Data Sheet
6.7 IQX160 [PQFP/208L] Package Pinout by Name
Name
GC0
GC1
GT0
GT1
GT2
GT3
P000
P001
P002
P003
P004
P005
P006
P007
P008
P009
P010
P011
P012
P013
P014
P015
P016
P017
P018
P019
P020
P021
P022
P023
P024
P025
P026
P027
P028
P029
P030
P031
P032
P033
P034
P035
P036
P037
P038
P039
P040
P041
P042
P043
P044
P045
Pin#
10
7
157
156
53
52
203
202
201
200
198
197
196
195
194
192
191
190
189
188
187
184
183
182
181
180
179
177
176
175
174
173
172
170
169
168
167
166
165
162
161
160
159
158
155
154
153
152
151
150
147
146
Name
P046
P047
P048
P049
P050
P051
P052
P053
P054
P055
P056
P057
P058
P059
P060
P061
P062
P063
P064
P065
P066
P067
P068
P069
P070
P071
P072
P073
P074
P075
P076
P077
P078
P079
P080
P081
P082
P083
P084
P085
P086
P087
P088
P089
P090
P091
P092
P093
P094
P095
P096
P097
Pin#
145
144
143
142
140
139
138
137
136
135
132
131
130
129
128
127
125
124
123
122
121
120
117
116
115
114
113
112
110
109
108
107
106
105
104
103
102
101
100
99
96
95
94
93
92
91
89
88
87
86
85
84
Name
P098
P099
P100
P101
P102
P103
P104/GT12
P105/GT11
P106/GT10
P107
P108/GT9
P109/GT8
P110/GC12
P111/GC11
P112/GC10
P113
P114/GC9
P115/GC8
P116/K4
P117/K3
P118
P119
P120/K2
P121/K1
P122/K0
P123
P124
P125/GC7
P126/GC6
P127/GC5
P128/GC4
P129
P130
P131/GT7
P132/GT6
P133/GT5
P134/GT4
P135
P136
P137/GC3
P138/GC2
P139/ P/S
P140/CA0
P141/CA1
P142/CA2
P143/CA3
P144/CA4
P145/CA5
P146/CA6
P147/CA7
P148/RA0
P149/RA1
Pin#
82
81
80
78
77
76
74
73
72
71
70
69
67
66
65
64
63
62
59
58
57
56
55
54
51
50
49
48
47
44
43
42
41
40
39
37
36
35
34
33
32
30
28
27
26
25
24
22
21
20
19
17
Name
P150/RA2
P151/RA3
P152/RA4
P153/RA5
P154/RA6
P155/RA7
P156/C0
P157/C1
P158/WE
P159/STROBE
RCE
TCK
TDI
TDO
TMS
TRST*
VDD
VDD
VDD.PAD1
VDD.PAD1
VDD.PAD1
VDD.PAD1
VDD.PAD2
VDD.PAD2
VDD.PAD2
VDD.PAD2
VDD.PAD2
VDD.X
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Pin#
16
15
14
13
12
11
5
4
3
2
6
206
1
207
208
204
29
133
119
164
186
205
8
45
61
79
98
148
9
18
23
31
38
46
60
68
75
83
90
97
111
118
126
134
141
149
163
171
178
185
193
199
Table 25. IQX160 [PQFP/208L] Package Pinout by Name
June 2000
Powered by ICminer.com Electronic-Library Service CopyRight 2003
Revision 5.0
49
IQX Family Data Sheet
6.8 IQX160 [PQFP/208L] Package Pinout by Location
Pin#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
Name
TDI
P159/STROBE
P158/WE
P157/C1
P156/C0
RCE
GC1
VDD.PAD2
VSS
GC0
P155/RA7
P154/RA6
P153/RA5
P152/RA4
P151/RA3
P150/RA2
P149/RA1
VSS
P148/RA0
P147/CA7
P146/CA6
P145/CA5
VSS
P144/CA4
P143/CA3
P142/CA2
P141/CA1
P140/CA0
VDD
P139/ P/S
VSS
P138/GC2
P137/GC3
P136
P135
P134/GT4
P133/GT5
VSS
P132/GT6
P131/GT7
P130
P129
P128/GC4
P127/GC5
VDD.PAD2
VSS
P126/GC6
P125/GC7
P124
P123
P122/K0
GT3
Pin#
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
Name
GT2
P121/K1
P120/K2
P119
P118
P117/K3
P116/K4
VSS
VDD.PAD2
P115/GC8
P114/GC9
P113
P112/GC10
P111/GC11
P110/GC12
VSS
P109/GT8
P108/GT9
P107
P106/GT10
P105/GT11
P104/GT12
VSS
P103
P102
P101
VDD.PAD2
P100
P099
P098
VSS
P097
P096
P095
P094
P093
P092
VSS
P091
P090
P089
P088
P087
P086
VSS
VDD.PAD2
P085
P084
P083
P082
P081
P080
Pin#
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
Name
P079
P078
P077
P076
P075
P074
VSS
P073
P072
P071
P070
P069
P068
VSS
VDD.PAD1
P067
P066
P065
P064
P063
P062
VSS
P061
P060
P059
P058
P057
P056
VDD
VSS
P055
P054
P053
P052
P051
P050
VSS
P049
P048
P047
P046
P045
P044
VDD.X
VSS
P043
P042
P041
P040
P039
P038
GT1
Pin#
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
Name
GT0
P037
P036
P035
P034
P033
VSS
VDD.PAD1
P032
P031
P030
P029
P028
P027
VSS
P026
P025
P024
P023
P022
P021
VSS
P020
P019
P018
P017
P016
P015
VSS
VDD.PAD1
P014
P013
P012
P011
P010
P009
VSS
P008
P007
P006
P005
P004
VSS
P003
P002
P001
P000
TRST*
VDD.PAD1
TCK
TDO
TMS
Table 26. IQX160 [PQFP/208L] Package Pinout by Location
50
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June 2000
IQX Family Data Sheet
I/O Ports Powered by VDD.PAD1
I/O Ports Powered by VDD.PAD2
Top View
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
GT1
P038
P039
P040
P041
P042
P043
VSS
VDD.X
P044
P045
P046
P047
P048
P049
VSS
P050
P051
P052
P053
P054
P055
VSS
VDD
P056
P057
P058
P059
P060
P061
VSS
P062
P063
P064
P065
P066
P067
VDD.PAD1
VSS
P068
P069
P070
P071
P072
P073
VSS
P074
P075
P076
P077
P078
P079
GT2
P121/K1
P120/K2
P119
P118
P117/K3
P116/K4
VSS
VDD.PAD2
P115/GC8
P114/GC9
P113
P112/GC10
P111/GC11
P110/GC12
VSS
P109/GT8
P108/GT9
P107
P106/GT10
P105/GT11
P104/GT12
VSS
P103
P102
P101
VDD.PAD2
P100
P099
P098
VSS
P097
P096
P095
P094
P093
P092
VSS
P091
P090
P089
P088
P087
P086
VSS
VDD.PAD2
P085
P084
P083
P082
P081
P080
TDI
P159/STROBE
P158/WE
P157/C1
P156/C0
RCE
GC1
VDD.PAD2
VSS
GC0
P155/RA7
P154/RA6
P153/RA5
P152/RA4
P151/RA3
P150/RA2
P149/RA1
VSS
P148/RA0
P147/CA7
P146/CA6
P145/CA5
VSS
P144/CA4
P143/CA3
P142/CA2
P141/CA1
P140/CA0
VDD
P139/ P/S
VSS
P138/GC2
P137/GC3
P136
P135
P134/GT4
P133/GT5
VSS
P132/GT6
P131/GT7
P130
P129
P128/GC4
P127/GC5
VDD.PAD2
VSS
P126/GC6
P125/GC7
P124
P123
P122/K0
GT3
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
TMS
TDO
TCK
VDD.PAD1
TRST*
P000
P001
P002
P003
VSS
P004
P005
P006
P007
P008
VSS
P009
P010
P011
P012
P013
P014
VDD.PAD1
VSS
P015
P016
P017
P018
P019
P020
VSS
P021
P022
P023
P024
P025
P026
VSS
P027
P028
P029
P030
P031
P032
VDD.PAD1
VSS
P033
P034
P035
P036
P037
GT0
6.9 IQX160 [PQFP/208L] Package Pinout
Figure 32. IQX160 [PQFP/208L] Package Pinout
June 2000
Powered by ICminer.com Electronic-Library Service CopyRight 2003
Revision 5.0
51
IQX Family Data Sheet
6.10 IQX128B [PQFP/184L] Package Pinout by Name
Name
Pin#
Name
Pin#
Name
Pin#
Name
GC0
10
P040
123
P086/GT10
63
TMS
Pin#
184
GC1
7
P041
122
P087/GT9
62
TRST*
179
GT0
139
P042
121
P088/GT8
61
VDD
28
GT1
138
P043
120
P089/GC12
58
VDD
118
GT2
48
P044
117
P090/GC11
57
VDD.PAD1
146
GT3
45
P045
116
P091/GC10
56
VDD.PAD1
93
P000
178
P046
115
P092/GC9
55
VDD.PAD1
106
P001
177
P047
114
P093/GC8
54
VDD.PAD1
137
P002
176
P048
113
P094/K4
52
VDD.PAD1
157
P003
175
P049
111
P095/K3
51
VDD.PAD1
168
P004
173
P050
110
P096/K2
50
VDD.PAD1
180
P005
172
P051
109
P097/K1
49
VDD.PAD2
47
P006
171
P052
108
P098/K0
44
VDD.PAD2
8
P007
170
P053
107
P099/GC7
43
VDD.PAD2
18
P008
169
P054
104
P100/GC6
42
VDD.PAD2
40
P009
166
P055
103
P101/GC5
39
VDD.PAD2
60
P010
165
P056
102
P102†/GC4
38
VDD.PAD2
73
P011
164
P057
101
P103†/GT7
37
VDD.PAD2
86
P012
163
P058
100
P104†/GT6
36
VDD.X
131
P013
161
P059
98
P105†/GT5
34
VSS
41
P014
160
P060
97
P106†/GT4
33
VSS
9
P015
159
P061
96
P107†/GC3
32
VSS
17
P016
158
P062
95
P108†/GC2
31
VSS
22
P017
155
P063
94
P109†/P/S
29
VSS
30
P018
154
P064
92
P110/CA0
27
VSS
35
P019
153
P065
90
P111/CA1
26
VSS
46
P020
152
P066
89
P112/CA2
25
VSS
53
P021
150
P067
88
P113/CA3
24
VSS
59
P022
149
P068
87
P114/CA4
23
VSS
66
P023
148
P069
84
P115/CA5
21
VSS
72
P024
147
P070
83
P116/CA6
20
VSS
79
P025
144
P071
82
P117/RA0
19
VSS
85
P026
143
P072
81
P118/RA1
16
VSS
91
P027
142
P073
80
P119/RA2
15
VSS
99
P028
141
P074
78
P120/RA3
14
VSS
105
P029
140
P075
77
P121/RA4
13
VSS
112
P030
136
P076
76
P122/RA5
12
VSS
119
P031
135
P077
75
P123/RA6
11
VSS
125
P032
134
P078
74
P124/C0
5
VSS
132
P033
133
P079
71
P125/C1
4
VSS
145
P034
130
P080
70
P126/WE
3
VSS
151
P035
129
P081
69
P127/STROBE
2
VSS
156
P036
128
P082
68
RCE
6
VSS
162
P037
127
P083
67
TCK
181
VSS
167
P038
126
P084/GT12
65
TDI
1
VSS
174
P039
124
P085/GT11
64
TDO
183
VSS
182
Table 27. IQX128B [PQFP/184L] Package Pinout by Name
52
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Revision 5.0
June 2000
IQX Family Data Sheet
6.11 IQX128B [PQFP/184L] Package Pinout by Location
Pin#
Name
Pin#
Name
Pin#
Name
Pin#
1
TDI
47
VDD.PAD2
93
VDD.PAD1
139
Name
GT0
2
P127/STROBE
48
GT2
94
P063
140
P029
3
P126/WE
49
P097/K1
95
P062
141
P028
4
P125/C1
50
P096/K2
96
P061
142
P027
5
P124/C0
51
P095/K3
97
P060
143
P026
6
RCE
52
P094/K4
98
P059
144
P025
7
GC1
53
VSS
99
VSS
145
VSS
8
VDD.PAD2
54
P093/GC8
100
P058
146
VDD.PAD1
P024
9
VSS
55
P092/GC9
101
P057
147
10
GC0
56
P091/GC10
102
P056
148
P023
11
P123/RA6
57
P090/GC11
103
P055
149
P022
12
P122/RA5
58
P089/GC12
104
P054
150
P021
13
P121/RA4
59
VSS
105
VSS
151
VSS
14
P120/RA3
60
VDD.PAD2
106
VDD.PAD1
152
P020
15
P119/RA2
61
P088/GT8
107
P053
153
P019
16
P118/RA1
62
P087/GT9
108
P052
154
P018
17
VSS
63
P086/GT10
109
P051
155
P017
18
VDD.PAD2
64
P085/GT11
110
P050
156
VSS
19
P117/RA0
65
P084/GT12
111
P049
157
VDD.PAD1
P016
20
P116/CA6
66
VSS
112
VSS
158
21
P115/CA5
67
P083
113
P048
159
P015
22
VSS
68
P082
114
P047
160
P014
23
P114/CA4
69
P081
115
P046
161
P013
24
P113/CA3
70
P080
116
P045
162
VSS
25
P112/CA2
71
P079
117
P044
163
P012
26
P111/CA1
72
VSS
118
VDD
164
P011
27
P110/CA0
73
VDD.PAD2
119
VSS
165
P010
28
VDD
74
P078
120
P043
166
P009
29
P109†/P/S
75
P077
121
P042
167
VSS
30
VSS
76
P076
122
P041
168
VDD.PAD1
31
P108†/GC2
77
P075
123
P040
169
P008
32
P107†/GC3
78
P074
124
P039
170
P007
33
P106†/GT4
79
VSS
125
VSS
171
P006
34
P105†/GT5
80
P073
126
P038
172
P005
35
VSS
81
P072
127
P037
173
P004
36
P104†/GT6
82
P071
128
P036
174
VSS
37
P103†/GT7
83
P070
129
P035
175
P003
38
P102†/GC4
84
P069
130
P034
176
P002
39
P101/GC5
85
VSS
131
VDD.X
177
P001
40
VDD.PAD2
86
VDD.PAD2
132
VSS
178
P000
41
VSS
87
P068
133
P033
179
TRST*
42
P100/GC6
88
P067
134
P032
180
VDD.PAD1
43
P099/GC7
89
P066
135
P031
181
TCK
44
P098/K0
90
P065
136
P030
182
VSS
45
GT3
91
VSS
137
VDD.PAD1
183
TDO
46
VSS
92
P064
138
GT1
184
TMS
Table 28. IQX128B [PQFP/184L] Package Pinout by Location
June 2000
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IQX Family Data Sheet
Top View
I/O Ports Powered by VDD.PAD1
I/O Ports Powered by VDD.PAD2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
GT1
VDD.PAD1
P030
P031
P032
P033
VSS
VDD.X
P034
P035
P036
P037
P038
VSS
P039
P040
P041
P042
P043
VSS
VDD
P044
P045
P046
P047
P048
VSS
P049
P050
P051
P052
P053
VDD.PAD1
VSS
P054
P055
P056
P057
P058
VSS
P059
P060
P061
P062
P063
VDD.PAD1
VDD.PAD2
GT2
P097/K1
P096/K2
P095/K3
P094/K4
VSS
P093/GC8
P092/GC9
P091/GC10
P090/GC11
P089/GC12
VSS
VDD.PAD2
P088/GT8
P087/GT9
P086/GT10
P085/GT11
P084/GT12
VSS
P083
P082
P081
P080
P079
VSS
VDD.PAD2
P078
P077
P076
P075
P074
VSS
P073
P072
P071
P070
P069
VSS
VDD.PAD2
P068
P067
P066
P065
VSS
P064
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
TDI
P127/STROBE
P126/WE
P125/C1
P124/C0
RCE
GC1
VDD.PAD2
VSS
GC0
P123/RA6
P122/RA5
P121/RA4
P120/RA3
P119/RA2
P118/RA1
VSS
VDD.PAD2
P117/RA0
P116/CA6
P115/CA5
VSS
P114/CA4
P113/CA3
P112/CA2
P111/CA1
P110/CA0
VDD
P109†/ P/S
VSS
P108†/GC2
P107†/GC3
P106†/GT4
P105†/GT5
VSS
P104†/GT6
P103†/GT7
P102†/GC4
P101/GC5
VDD.PAD2
VSS
P100/GC6
P099/GC7
P098/K0
GT3
VSS
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
TMS
TDO
VSS
TCK
VDD.PAD1
TRST*
P000
P001
P002
P003
VSS
P004
P005
P006
P007
P008
VDD.PAD1
VSS
P009
P010
P011
P012
VSS
P013
P014
P015
P016
VDD.PAD1
VSS
P017
P018
P019
P020
VSS
P021
P022
P023
P024
VDD.PAD1
VSS
P025
P026
P027
P028
P029
GT0
6.12 IQX128B [PQFP/184L] Package Pinout
Figure 33. IQX128B [PQFP/184L] Package Pinout
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IQX Family Data Sheet
7.0 MECHANICAL SPECIFICATION
7.1 IQX320 [PBGA/416L] Package Dimensions
Top View
AF
AE
AD
AC
AB
AA
Y
X
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
IQX320
PB416
F5N42A
USA
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Pin A1 Marking
0.50
(0.0197)
1.50 ± 0.2
(0.059 ± .0079)
0.60
(0.0236)
Cross-sectional View
20.24
(0.797)
AF
AE
AD
AC
AB
AA
Y
X
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
1.27 mm.
(0.050) (in.)
35
(1.378)
Bottom View (Ball Side)
Figure 34. IQX320 [PBGA/416L] Package Dimensions
Note:
(1) Use “mm” as the controlling dimension.
June 2000
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IQX Family Data Sheet
7.2 PQFP Package Dimensions
E
E1
D1 D
Top View
W
X
Side View
8 - 12°
A2
0 - 7°
L
A
A1
e
Dimension in
mm.
(in.)
0.10
(0.004)
B
Detail X
Detail W
Figure 35. PQFP Package Dimensions
Note:
(1) Use “mm” as the controlling dimension
Package
Dimension Table
A
max
A1
min
max
A2
min
max
D
min
max
D1
min
max
E
min
max
E1
min
max
L
min
max
B
min
max
e
BSC.
PQFP/304L
inch
mm
0.172
4.37
0.011
0.28
0.019
0.47
0.146
3.70
0.154
3.90
1.669
42.40
1.685
42.80
1.571
39.90
1.618
40.10
1.669
42.40
1.685
42.80
1.571
39.90
1.618
40.10
0.020
0.50
0.028
0.75
0.007
0.17
0.011
0.27
0.0197
0.50
PQFP/208L
inch
mm
0.157
3.99
0.010
0.25
0.017
0.43
0.135
3.43
0.140
3.56
1.195
30.40
1.215
30.91
1.098
27.93
1.106
28.14
1.195
30.40
1.215
30.91
1.098
27.93
1.106
28.14
0.018
0.46
0.030
0.76
0.006
0.15
0.011
0.28
0.0197
0.50
PQFP/184L
inch
mm
0.157
3.99
0.010
0.25
0.017
0.43
0.135
3.43
0.140
3.56
1.219
31.01
1.238
31.49
1.098
27.93
1.106
28.14
1.219
31.01
1.238
31.49
1.098
27.93
1.106
28.14
0.029
0.74
0.041
1.04
0.006
0.15
0.011
0.28
0.0197
0.50
Table 29. PQFP Package Dimensions
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IQX Family Data Sheet
8.0 PACKAGE THERMAL CHARACTERISTICS
Package
Pin Count
ΘJC(C/W)
ΘJA(°C/W)
Still Air
ΘJA(°C/W)
200 Ifpm
ΘJA(°C/W)
400 Ifpm
ΘJA(°C/W)
600 Ifpm
PQFP
184
6.6
37.4
28.3
24.2
21.7
208
6.6
36.6
27.4
24.0
21.4
304
6.3
21.6
19.3
17.9
16.3
416
1.7
13.8
10.6
9.2
8.5
PBGA
Table 30. Package Thermal Coefficients
Note:
(1) Thermal performance values are based on simulation data.
June 2000
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IQX Family Data Sheet
9.0 TABLES FOR DETERMINING DIE PAD TO I/O PORT PIN MAPPING AND LOCATIONS OF REAL SRAM
CELL
The following tables help determine the locations of the real SRAM cells in the Switch Matrix. The SRAM cell controlling the
connection between I/O Port “i” and I/O Port “j” is determined as follows:
Get the Index values corresponding to I/O Port numbers “i” and “j”. If the index value for “i” is greater than index value for “j”, then the
SRAM cell has the row (word) address i* and column (bit) address j*, otherwise it has row address of j* and column address of i*. The
numbers i* and j* represent the I/O Port locations on the die.
Ex 1: On the IQX160, the SRAM cell controlling the connection between I/O Port 20 and I/O Port 100 is at location: Row addr = 20,
Col Addr = 100; because the index for I/O Port 20 is 82, and it is greater than the index for I/O Port 100 which is 79.
Ex 2: On the IQX240B, the SRAM cell controlling the connection between I/O Port 80 and I/O Port 180 is at location: Row addr = 241,
Col Addr = 110; because the index value for I/O Port 80 is 120, and it is less than the index value for I/O Port 180 which is 313. Note
that the IQX240B is a bondout version of IQX320 die, and the I/O Ports 80 and 180 on the device package are the I/O Ports 110 and
241 respectively.
58
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IQX Family Data Sheet
Die PAD
and
IQX320
I/O Port
IQX240B
I/O Port Index
Die PAD
and
IQX320
I/O Port
IQX240B
I/O Port Index
Die PAD
and
IQX320
I/O Port
IQX240B
I/O Port Index
Die PAD
and
IQX320
I/O Port
IQX240B
I/O Port Index
0
-
2
40
30
162
80
-
0
120
90
160
1
0
6
41
31
166
81
60
4
121
91
164
2
-
10
42
32
170
82
-
8
122
92
168
3
1
14
43
33
174
83
61
12
123
93
172
4
-
18
44
34
178
84
-
16
124
94
176
5
2
22
45
35
182
85
62
20
125
95
180
6
-
26
46
36
186
86
-
24
126
96
184
7
3
30
47
37
190
87
63
28
127
97
188
8
-
34
48
38
194
88
-
32
128
98
192
9
4
38
49
39
198
89
64
36
129
99
196
10
-
42
50
40
202
90
-
40
130
100
200
11
5
46
51
41
206
91
65
44
131
101
204
12
-
50
52
42
210
92
-
48
132
102
208
13
6
54
53
43
214
93
66
52
133
103
212
14
-
58
54
44
218
94
67
56
134
104
216
15
7
62
55
45
222
95
68
60
135
105
220
16
8
66
56
-
226
96
-
64
136
106
224
17
9
70
57
46
230
97
69
68
137
107
228
18
10
74
58
-
234
98
-
72
138
108
232
19
11
78
59
47
238
99
70
76
139
109
236
20
12
82
60
-
242
100
-
80
140
-
240
21
13
86
61
48
246
101
71
84
141
110
244
22
14
90
62
-
250
102
72
88
142
-
248
23
15
94
63
49
254
103
73
92
143
111
252
24
-
98
64
-
258
104
74
96
144
-
256
25
16
102
65
50
262
105
75
100
145
112
260
26
17
106
66
-
266
106
76
104
146
-
264
27
18
110
67
51
270
107
77
108
147
113
268
28
19
114
68
-
274
108
78
112
148
-
272
29
20
118
69
52
278
109
79
116
149
114
276
30
21
122
70
-
282
110
80
120
150
-
280
31
22
126
71
53
286
111
81
124
151
115
284
32
23
130
72
-
290
112
82
128
152
-
288
33
24
134
73
54
294
113
83
132
153
116
292
34
-
138
74
-
298
114
84
136
154
-
296
35
25
142
75
55
302
115
85
140
155
117
300
36
26
146
76
56
306
116
86
144
156
-
304
37
27
150
77
57
310
117
87
148
157
118
308
38
28
154
78
58
314
118
88
152
158
-
312
39
29
158
79
59
318
119
89
156
159
119
316
Table 31. IQX320 and IQX240B I/O Port Pin Mapping
June 2000
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59
IQX Family Data Sheet
Die PAD
and
IQX320
I/O Port
IQX240B
I/O Port Index
Die PAD
and
IQX320
I/O Port
IQX240B
I/O Port Index
Die PAD
and
IQX320
I/O Port
IQX240B
I/O Port Index
Die PAD
and
IQX320
I/O Port
IQX240B
I/O Port Index
160
-
319
200
149
159
240
-
317
280
-
157
161
120
315
201
150
155
241
180
313
281
208
153
162
-
311
202
151
151
242
181
309
282
-
149
163
121
307
203
152
147
243
182
305
283
209
145
164
-
303
204
153
143
244
-
301
284
-
141
165
122
299
205
154
139
245
183
297
285
210
137
166
-
295
206
155
135
246
-
293
286
-
133
167
123
291
207
156
131
247
184
289
287
211
129
168
-
287
208
157
127
248
-
285
288
-
125
169
124
283
209
158
123
249
185
281
289
212
121
170
-
279
210
159
119
250
-
277
290
-
117
171
125
275
211
160
115
251
186
273
291
213
113
172
-
271
212
161
111
252
-
269
292
-
109
173
126
267
213
162
107
253
187
265
293
214
105
174
-
263
214
163
103
254
188
261
294
-
101
175
127
259
215
164
99
255
189
257
295
215
97
176
-
255
216
165
95
256
190
253
296
216
93
177
128
251
217
166
91
257
191
249
297
217
89
178
-
247
218
167
87
258
192
245
298
218
85
179
129
243
219
168
83
259
193
241
299
219
81
180
-
239
220
169
79
260
194
237
300
220
77
181
130
235
221
170
75
261
195
233
301
221
73
182
131
231
222
-
71
262
-
229
302
222
69
183
132
227
223
171
67
263
196
225
303
223
65
184
133
223
224
-
63
264
-
221
304
224
61
185
134
219
225
172
59
265
197
217
305
225
57
186
135
215
226
-
55
266
-
213
306
226
53
187
136
211
227
173
51
267
198
209
307
227
49
188
137
207
228
-
47
268
199
205
308
228
45
189
138
203
229
174
43
269
200
201
309
229
41
190
139
199
230
-
39
270
201
197
310
230
37
191
140
195
231
175
35
271
202
193
311
231
33
192
141
191
232
-
31
272
203
189
312
232
29
193
142
187
233
176
27
273
204
185
313
233
25
194
143
183
234
-
23
274
-
181
314
234
21
195
144
179
235
177
19
275
205
177
315
235
17
196
145
175
236
-
15
276
-
173
316
236
13
197
146
171
237
178
11
277
206
169
317
237
9
198
147
167
238
-
7
278
-
165
318
238
5
199
148
163
239
179
3
279
207
161
319
239
1
Table 31. IQX320 and IQX240B I/O Port Pin Mapping (Continued)
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IQX Family Data Sheet
128B
Port Index
Die PAD
and
IQX160
I/O Port
IQX128B
I/O Port Index
Die PAD
and
IQX160
I/O Port
IQX128B
I/O Port Index
Die PAD
and
IQX160
I/O Port
IQX128B
I/O Port Index
0
2
40
-
0
80
64
159
120
96
157
1
6
41
-
4
81
65
155
121
97
153
2
10
42
32
8
82
66
151
122
98
149
3
14
43
33
12
83
-
147
123
-
145
4
18
44
34
16
84
67
143
124
-
141
5
22
45
35
20
85
68
139
125
99
137
6
26
46
36
24
86
69
135
126
100
133
7
30
47
-
28
87
70
131
127
101
129
8
34
48
37
32
88
71
127
128
102
125
9
38
49
38
36
89
-
123
129
-
121
10
42
50
39
40
90
72
119
130
-
117
-
46
51
40
44
91
73
115
131
103
113
-
50
52
41
48
92
74
111
132
104
109
11
54
53
-
52
93
75
107
133
105
105
12
58
54
42
56
94
76
103
134
106
101
13
62
55
43
60
95
-
99
135
-
97
14
66
56
44
64
96
77
95
136
-
93
-
70
57
45
68
97
78
91
137
107
89
-
74
58
46
72
98
79
87
138
108
85
15
78
59
-
76
99
80
83
139
109
81
16
82
60
47
80
100
81
79
140
110
77
17
86
61
48
84
101
-
75
141
111
73
18
90
62
49
88
102
82
71
142
112
69
-
94
63
50
92
103
83
67
143
113
65
-
98
64
51
96
104
84
63
144
114
61
19
102
65
-
100
105
85
59
145
115
57
20
106
66
52
104
106
86
55
146
116
53
21
110
67
53
108
107
-
51
147
-
49
22
114
68
54
112
108
87
47
148
117
45
-
118
69
55
116
109
88
43
149
118
41
-
122
70
56
120
110
89
39
150
119
37
23
126
71
-
124
111
90
35
151
120
33
24
130
72
57
128
112
91
31
152
121
29
25
134
73
58
132
113
-
27
153
122
25
26
138
74
59
136
114
92
23
154
123
21
27
142
75
60
140
115
93
19
155
-
17
28
146
76
61
144
116
94
15
156
124
13
29
150
77
62
148
117
95
11
157
125
9
30
154
78
63
152
118
-
7
158
126
5
31
158
79
-
156
119
-
3
159
127
1
Table 32. IQX160 and IQX128B I/O Port Pin Mapping
June 2000
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IQX Family Data Sheet
10.0 COMPONENT AVAILABILITY AND ORDERING INFORMATION
The following table lists the IQX devices and the different
package options, and speed grades available.
Package
Pins
184
208
304
416
Type
PQFP
PQFP
PQFP
PBGA
Code
PQ184
PQ208
PQ304
PB416
IQX320
IQX240B
IQX160
IQX128B
-12
X
-10
X
-12
X
-10
X
-10
X
-7
X
-10
X
-7
X
Table 33. Component Availability
Device
Speed
Package*
Ordering#
IQX320
-12
PB 416
IQX320-PB416
-10
PB 416
IQX320-10PB416
-12
PQ 304
IQX240B-PQ304
-10
PQ 304
IQX240B-10PQ304
-10
PQ 208
IQX160-PQ208
-7
PQ 208
IQX160-7PQ208
-10
PQ 184
IQX128B-PQ184
-7
PQ 184
IQX128B-7PQ184
IQX240B
IQX160
IQX128B
Table 34. Ordering Information
* PB=Plastic Ball Grid Array, PQ=Plastic Quad Flat Pack
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IQX Family Data Sheet
11.0 IQX FAMILY AT A GLANCE
Feature
IQX320
IQX240B
IQX160
IQX128B
Number of Usable I/O Port Pins
320
240
160
128
Switch Matrix Size
320 lines
240 lines
160 lines
128 lines
Signal Direction
IN, OUT, BIDIR
IN, OUT, BIDIR
IN, OUT, BIDIR
IN, OUT, BIDIR
Dataflow
Flow-through,
Latched,
Clocked
Flow-through,
Latched,
Clocked
Flow-through,
Latched,
Clocked
Flow-through,
Latched,
Clocked
Control Signals
Clock,
Clock Enable,
Input Tristate,
Output Tristate
Clock,
Clock Enable,
Input Tristate,
Output Tristate
Clock,
Clock Enable,
Input Tristate,
Output Tristate
Clock,
Clock Enable,
Input Tristate,
Output Tristate
Programmable I/O Port Attributes
Number of Clock Control Pins
dedicated
4
4
2
2
shared with I/O Port Pins
9
9
11
11
dedicated
5
5
4
4
shared with I/O Port Pins
8
8
9
9
23 / 22
23 / 22
21/20
19/18
Number of Tristate Control Pins
I/O Ports Used By RapidConfigure Interface
Pin-to-Pin Delay
7.5 ns
7.5 ns
7.5 ns
7.5 ns
NRZ Data Rate
180 Mbs
180 Mbs
200 Mbs
200 Mbs
Maximum Clock Frequency
133 MHz
133 MHz
133 MHz
133 MHz
12 mA
12 mA
12 mA
12 mA
3V and/or 5V
3V and/or 5V
3V and/or 5V
3V and/or 5V
I/O Current Drive
I/O Voltage
Process
Packages
0.6µ
0.6µ
0.6µ
0.6µ
391 PPGA
416 PBGA
304 PQFP
304 MQUAD
208 PQFP
208 MQUAD
184 PQFP
184 MQUAD
Table 35. IQX Family at a Glance
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IQX Family Data Sheet
12.0 PRODUCT STATUS DEFINITIONS
Data Sheet Identification
Product Status
Advanced
Formative or In Design
This data sheet contains the design specifications for
product development. Specification may change in any
manner without notice.
Preproduction Product
This data sheet contains the preliminary data, and
supplementary data will be published at a later date. I-Cube
reserves the right to make changes at any time without
notice in order to improve design and supply the best
possible product.
Preliminary
No Identification
Full Production
Obsolete
No longer in Production
Definition
This data sheet contains final specifications. I-Cube
reserves the right to make changes at any time without
notice in order to improve design and supply the best
possible product.
This data sheet contains specifications for a product that
has been discontinued by I-Cube. The data sheet is
provided for reference information only.
I-Cube® is a registered trademark and RapidConnect, RapidConfigure, ActiveArray, ImpliedDisconnect, IQ, IQX, MSX, MSXPro, OCX and PSX are
trademarks of I-Cube, Inc. All other trademarks or registered trademarks are the property of their respective holders. I-Cube, Inc., does not assume
any liability arising out of the applications or use of the product described herein; nor does it convey any license under its patents, copyright rights or
any rights of others.
The information contained in this document is believed to be current and accurate as of the publication date. I-Cube reserves the right to make
changes, at any time, in order to improve reliability, function, performance or design in order to supply the best product possible. I-Cube assumes no
obligation to correct any errors contained herein or to advise any user of this text of any correction if such be made.
LIFE SUPPORT APPLICATIONS
I-Cube products are not designed for use in life support appliances, devices, or systems where malfunction of an I-Cube product can reasonably be
expected to result in personal injury. I-Cube customers using or selling I-Cube products for use in such application do so at their own risk and agree
to fully indemnify I-Cube for any damages resulting from such improper use or sale.
This product is protected under the U.S. patents: 5202593, 5282271, 5426738, 5428750, 5428800, 5465056, 5530814, 5559971, 5625780, 5710550,
5717871, 5734334, 5754791, 5781717, 5790048. Additional patents pending.
IQX Family Data Sheet—Revision 5.0, June 2000
Previously printed as IQX Family Data Sheet—Revision 4.0, February 2000
Copyright © 1992-2000 I-Cube, Inc. All rights reserved. Unpublished—rights reserved under the copyright laws of the United States. Use of copyright
notices is precautionary and does not imply publication or disclosure.
I-Cube®, Inc.
2605 S. Winchester Blvd.
Campbell, CA 95008, USA
Phone:
Fax:
Email:
Internet:
+(408) 341-1888
+(408) 341-1899
mar[email protected]
http://www.icube.com
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