ETC AM186CU

Am186™CU
High-Performance, 80C186-Compatible
16-Bit Embedded USB Microcontroller
DISTINCTIVE CHARACTERISTICS
■ E86™ family of x86 embedded processors
offers improved time-to-market
– Software migration (backwards- and upwardscompatible)
– World-class development tools, applications, and
system software
■ Serial Communications Peripherals
■ Memory and Peripheral Interface
– Integrated DRAM controller
– Glueless interface to RAM/ROM/Flash memory
(55-ns Flash memory required for zero-wait-state
operation at 50 MHz)
– Fourteen chip selects (8 peripherals, 6 memory)
– External bus mastering support
– Universal Serial Bus (USB) peripheral controller
– Multiplexed and nonmultiplexed address/data bus
– High-Speed UART with autobaud
– Programmable bus sizing
– UART
– 8-bit boot option
– Synchronous serial interface (SSI)
– SmartDMA™ channels (4) to support USB
■ System Peripherals
■ Available in the following package:
– 160-pin plastic quad flat pack (PQFP)
– 25-, 40-, and 50-MHz operating frequencies
– Three programmable 16-bit timers
– Low-voltage operation, VCC = 3.3 V ± 0.3 V
– Hardware watchdog timer
– Commercial and industrial temperature rating
– General-purpose DMA (4 channels)
– 5-V-tolerant I/O (3.3-V output levels)
– Programmable I/O (48 PIO signals)
– Interrupt Controller (36 maskable interrupts)
GENERAL DESCRIPTION
The Am186™CU USB microcontroller is a member of
AMD’s Comm86™ family of communications-specific
microcontrollers. The microcontroller is a derivative of
the Am186CC communications controller and is pincompatible with that device.
The Am186CU USB microcontroller is a cost-effective,
high-per for mance microcontroller solution for
communications applications. This highly integrated
microcontroller enables customers to save system
costs and increase perfor mance over 8-bit
microcontrollers and other 16-bit microcontrollers.
The microcontroller offers the advantages of the x86
development environment’s widely available native
development tools, applications, and system software.
Additionally, the microcontroller uses the industrystandard 186 instruction set that is part of the AMD
E86™ family, which continually offers instruction-setcompatible upgrades.
© Copyright 2000 Advanced Micro Devices, Inc. All rights reserved.
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Built into the Am186CU USB microcontroller is a wide
range of communications features required in many
communications applications, including the Universal
Serial Bus (USB) peripheral controller that designers
can use to implement a variety of microcontrollerbased USB peripheral devices for telephony, audio, or
other high-end applications. The USB controller does
not suppor t USB host or hub functions, but the
Am186CU USB microcontroller can be used to
implement USB peripheral functions in a device that
also contains separate USB hub circuitry.
Comprehensive development support is available from
AMD and its FusionE86 SM par tners. A customer
development platform board is available. AMD and its
FusionE86 partners also offer boards, schematics,
drivers, protocol stacks, and routing software to enable
fast time to market.
Publication# 22025 Rev: B Amendment/0
Issue Date: May 2000
ORDERING INFORMATION
Am186CU
–50
K
C
\W
LEAD FORMING
\W=Trimmed and Formed
TEMPERATURE RANGE
C= Am186CU Commercial (TC =0•C to +100•C)
I = Am186CU Industrial (TA =–40•C to +85•C)
where: TC = case temperature
where: TA = ambient temperature
PACKAGE TYPE
K=160-Pin Plastic Quad Flat Pack (PQFP)
SPEED OPTION
–25 = 25 MHz
–40 = 40 MHz
–50 = 50 MHz
DEVICE NUMBER/DESCRIPTION
Am186CU high-performance 80C186-compatible
16-bit embedded USB microcontroller
Valid Combinations
Valid Combinations
Valid combinations list configurations planned to be
supported in volume for this device. Consult the
local AMD sales office to confirm availability of
specific valid combinations and to check on newly
released combinations.
Am186CU–25
Am186CU–40
KC\W
Am186CU–50
Am186CU–25
Am186CU–40
2
KI\W
Am186™CU USB Microcontroller Data Sheet
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TABLE OF CONTENTS
Distinctive Characteristics ............................................................................................................ 1
General Description ..................................................................................................................... 1
Ordering Information .................................................................................................................... 2
Logic Diagram By Interface ......................................................................................................... 6
Logic Diagram By Default Pin Function ....................................................................................... 7
Pin Connection Diagram—160-Pin PQFP Package .................................................................... 8
Pin and Signal Tables .................................................................................................................. 9
Signal Descriptions ............................................................................................................... 12
Architectural Overview ............................................................................................................... 24
Detailed Description .............................................................................................................. 24
Am186™ Embedded CPU .................................................................................................... 25
Memory Organization ............................................................................................................ 25
I/O Space .............................................................................................................................. 25
Serial Communications Support ............................................................................................ 26
Universal Serial Bus ......................................................................................................... 26
Four SmartDMA™ Channels............................................................................................ 26
Two Asynchronous Serial Ports ....................................................................................... 26
Synchronous Serial Port................................................................................................... 26
System Peripherals ............................................................................................................... 27
Interrupt Controller ........................................................................................................... 27
Four General-Purpose DMA Channels ............................................................................ 27
48 Programmable I/O Signals .......................................................................................... 27
Three Programmable Timers ........................................................................................... 27
Hardware Watchdog Timer .............................................................................................. 27
Memory and Peripheral Interface .......................................................................................... 28
System Interfaces............................................................................................................. 28
DRAM Support ................................................................................................................. 30
Chip Selects ..................................................................................................................... 30
Clock Control ......................................................................................................................... 31
In-Circuit Emulator Support ................................................................................................... 31
Applications ............................................................................................................................... 31
Clock Generation and Control ................................................................................................... 32
Features ................................................................................................................................ 32
System Clock ........................................................................................................................ 32
USB Clock ............................................................................................................................. 32
Clock Sharing by System and USB ....................................................................................... 33
Crystal-Driven Clock Source ................................................................................................. 34
External Clock Source ........................................................................................................... 35
Static Operation .................................................................................................................... 35
PLL Bypass Mode ................................................................................................................. 35
UART Baud Clock ................................................................................................................. 35
Power Supply Operation ............................................................................................................ 36
Power Supply Connections ................................................................................................... 36
Input/Output Circuitry ............................................................................................................ 36
PIO Supply Current Limit ...................................................................................................... 36
Absolute Maximum Ratings ....................................................................................................... 37
Operating Ranges ...................................................................................................................... 37
Driver Characteristics—Universal Serial Bus ............................................................................ 37
DC Characteristics over Commercial and Industrial Operating Ranges .................................... 38
Capacitance ............................................................................................................................... 38
Maximum Load Derating ............................................................................................................ 39
Power Supply Current ................................................................................................................ 39
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Thermal Characteristics—PQFP Package ................................................................................ 40
Commercial and Industrial Switching Characteristics and Waveforms ...................................... 41
Switching Characteristics over Commercial and Industrial Operating Ranges ......................................48
Appendix A—Pin Tables ............................................................................................................A-1
Pin List Table Column Definitions ........................................................................................A-9
Appendix B—Physical Dimensions: PQR160, Plastic Quad Flat Pack (PQFP) ........................B-1
Appendix C—Customer Support ...............................................................................................C-1
Related AMD Products—E86™ Family Devices ..................................................................C-1
Related Documents ..............................................................................................................C-2
Am186CC/CH/CU Microcontroller Customer Development Platform ..................................C-2
Third-Party Development Support Products .................................................................................C-2
Customer Service .................................................................................................................C-2
Hotline and World Wide Web Support............................................................................. C-2
Corporate Applications Hotline........................................................................................ C-2
World Wide Web Home Page ......................................................................................... C-3
Documentation and Literature ......................................................................................... C-3
Literature Ordering .......................................................................................................... C-3
Index .................................................................................................................................. Index-1
LIST OF FIGURES
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
4
Am186CU USB Microcontroller Block Diagram .................................................... 24
Two-Component Address Example ...................................................................... 25
Am186CU Microcontroller Address Bus — Default Operation .............................. 29
Am186CU Microcontroller—Address Bus Disable In Effect .................................. 29
System and USB Clock Generation ...................................................................... 33
Suggested System Clock Frequencies, Clock Modes, and Crystal Frequencies . 34
External Interface to Support Clocks—Fundamental Mode Crystal ...................... 34
External Interface to Support Clocks—External Clock Source ............................. 35
UART and High-Speed UART Clocks ................................................................... 35
Typical Icc Versus Frequency ................................................................................ 39
Thermal Resistance(•C/Watt) ............................................................................... 40
Thermal Characteristics Equations ....................................................................... 40
Key to Switching Waveforms ................................................................................ 41
Read Cycle Waveforms ........................................................................................ 50
Write Cycle Waveforms ......................................................................................... 53
Software Halt Cycle Waveforms ........................................................................... 54
Peripheral Waveforms ........................................................................................... 55
Reset Waveforms .................................................................................................. 56
Signals Related to Reset (System PLL in 1x or 2x Mode) .................................... 57
Signals Related to Reset (System PLL in 4x Mode) ............................................. 57
Synchronous Ready Waveforms ........................................................................... 58
Asynchronous Ready Waveforms ......................................................................... 59
Entering Bus Hold Waveforms .............................................................................. 60
Exiting Bus Hold Waveforms ................................................................................. 60
System Clocks Waveforms—Active Mode (PLL 1x Mode) ................................... 62
USB Clocks Waveforms ........................................................................................ 62
USB Data Signal Rise and Fall Times .................................................................. 63
USB Receiver Jitter Tolerance .............................................................................. 63
SSI Waveforms ..................................................................................................... 64
DRAM Read Cycle without Wait States Waveform ............................................... 65
DRAM Read Cycle with Wait States Waveform .................................................... 66
DRAM Write Cycle without Wait States Waveform ............................................... 66
DRAM Write Cycle with Wait States Waveform .................................................... 67
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Figure 34.
DRAM Refresh Cycle Waveform ........................................................................... 67
LIST OF TABLES
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
PQFP Pin Assignments—Sorted by Pin Number .................................................. 10
PQFP Pin Assignments—Sorted by Signal Name ................................................ 11
Signal Descriptions Table Definitions..................................................................... 12
Signal Descriptions ............................................................................................... 13
Segment Register Selection Rules ....................................................................... 25
Crystal Parameters ................................................................................................ 34
Typical Power Consumption Calculation................................................................ 39
Thermal Characteristics (•C/Watt) ........................................................................ 40
Alphabetical Key to Switching Parameter Symbols .............................................. 42
Numerical Key to Switching Parameter Symbols .................................................. 45
Read Cycle Timing ................................................................................................ 48
Write Cycle Timing ................................................................................................ 51
Software Halt Cycle Timing ................................................................................... 54
Peripheral Timing ................................................................................................. 55
Reset Timing ......................................................................................................... 56
External Ready Cycle Timing ................................................................................ 58
Bus Hold Timing .................................................................................................... 60
System Clocks Timing ........................................................................................... 61
USB Clocks Timing ............................................................................................... 62
USB Timing ........................................................................................................... 63
SSI Timing ............................................................................................................. 64
DRAM Timing ........................................................................................................ 65
Power-On Reset (POR) Pin Defaults ...................................................................A-2
Multiplexed Signal Trade-Offs ..............................................................................A-5
PIOs Sorted by PIO Number ................................................................................A-6
PIOs Sorted by Signal Name ...............................................................................A-7
Reset Configuration Pins (Pinstraps) ...................................................................A-8
Pin List Table Definitions.......................................................................................A-9
Pin List Summary ...............................................................................................A-10
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5
LOGIC DIAGRAM BY INTERFACE1
CLKOUT
RES
RESOUT
X1
X2
Reset/
Clocks
Address and
Address/Data
Buses
20
A19–A0
16
AD15–AD0
2
/
Bus Status and
Control
3
/
ALE
ARDY
BHE
BSIZE8
DEN
DS
DRQ1–DRQ0
DT/R
HLDA
HOLD
RD
S2–S0
S6
SRDY
WHB
WLB
WR
INT8–INT0
NMI
LCS
MCS3–MCS0
PCS7–PCS0
UCS
Am186CU USB
Microcontroller
2
/
PWD
TMRIN1–TMRIN0
TMROUT1–TMROUT0
Debug
2
/
QS1–QS0
Programmable I/O
(PIO)
48
Programmable
Timers
Configuration
Pinstraps
2
/
/
PIO47–PIO0
{ADEN}
{CLKSEL1}
{CLKSEL2}
{ONCE}
{UCSX8}
{USBSEL1}
{USBSEL2}
{USBXCVR}
9
4
8
/
/
/
Interrupts
Chip
Selects
CAS0
CAS1
RAS0
RAS1
DRAM Control
SDEN
SCLK
SDATA
Synchronous
Serial Interface
RXD_U
TXD_U
CTS_U
RTR_U
Asynchronous
Serial Interface
(UART)
RXD_HU
TXD_HU
CTS_HU
RTR_HU
High-Speed
UART
UCLK
UART Clock
USBD+
USBD–
USBSCI
USBSOF
USBX1
USBX2
UDMNS
UDPLS
UTXDMNS
UTXDPLS
UXVOE
UXVRCV
Universal Serial
Bus (USB)
USB External
Transceiver
Interface
Notes:
1. Because of multiplexing, not all interfaces are available at once. Refer to Table 24, “Multiplexed Signal Trade-Offs,” on page
A-5.
6
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LOGIC DIAGRAM BY DEFAULT PIN FUNCTION1
CLKOUT
RES
RESOUT
X1
X2
Reset/
Clocks
Address and
Address/Data Buses
20
16
A19–A0
AD15–AD0
ALE [PIO33]
ARDY [PIO8]
BHE [PIO34] {ADEN}
BSIZE8
DEN [DS] [PIO30]
DRQ1
DT/R [PIO29]
HLDA {CLKSEL1}
Bus Status and
Control
Debug
/
High-Speed UART
QS1–QS0
TXD_HU
LCS [RAS0]
MCS1 [CAS1]
MCS2 [CAS0]
PCS0 [PIO13] {USBSEL1}
PCS1 [PIO14] {USBSEL2}
PCS2
PCS3
UCS {ONCE}
Chip
Selects
USBD+ [UDPLS]
USBD– [UDMNS]
USBX1
USBX2
Universal Serial Bus
(USB)
6
Interrupts
Am186CU USB
Microcontroller
HOLD
RD
S0 {USBXCVR}
S1
S2
S6
SRDY [PIO35]
WHB
WLB
WR [PIO15]
2
/
INT5–INT0
NMI
Programmable
I/O (PIO)
PIO0 [TMRIN1]
PIO1 [TMROUT1]
PIO2 [PCS5]
PIO3 [PCS4] {CLKSEL2}
PIO4 [MCS0] {UCSX8}
PIO5 [MCS3] [RAS1]
PIO6 [INT8] [PWD]
PIO7 [INT7]
PIO8 [ARDY]
PIO9 [DRQ0]
PIO10 [SDEN]
PIO11 [SCLK]
PIO12 [SDATA]
PIO16 [RXD_HU]
PIO17
PIO18
PIO19 [INT6]
PIO20 [TXD_U]
PIO21 [UCLK] [USBSOF] [USBSCI]
PIO22
PIO23
PIO24 [CTS_U]
PIO25 [RTR_U]
PIO26 [RXD_U]
PIO27 [TMRIN0]
PIO28 [TMROUT0]
PIO31 [PCS7]
PIO32 [PCS6]
PIO36
PIO37
PIO38
PIO39
PIO40
PIO41
PIO42
PIO43
PIO44
PIO45
PIO46 [CTS_HU]
PIO47 [RTR_HU]
RSVD_104 [UXVRCV]
RSVD_103 [UXVOE]
RSVD_102 [UTXDMNS]
RSVD_101 [UTXDPLS]
RSVD_119
RSVD_118
RSVD_117
RSVD_116
—
—
—
—
—
—
—
—
Reserved
1. Pin names in bold indicate the default pin function. Brackets, [ ], indicate alternate, multiplexed functions. Braces, { }, indicate
pinstrap pins.
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7
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
VCC
TXD_U
RXD_U
CTS_U
RTR_U
VSS
PIO43
PIO42
PIO44
PIO45
PIO22
PIO23
VCC
INT8/PWD
INT7
INT6
TMRIN1
TMROUT1
TMRIN0
TMROUT0
VSS
PIO37
PIO36
PIO38
PIO39
PIO40
PIO41
VCC
UCS {ONCE}
LCS/RAS0
VSS
MCS3/RAS1
MCS2/CAS0
MCS1/CAS1
MCS0 {UCSX8}
VCC
DRQ0
PIO17
PIO18
VSS
PIN CONNECTION DIAGRAM—160-PIN PQFP PACKAGE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
VSS
SDEN
SCLK
SDATA
PCS0 {USBSEL1}
PCS1 {USBSEL2}
PCS2
PCS3
PCS4 {CLKSEL2}
PCS5
PCS6
VCC
PCS7
ARDY
Am186CU USB
Microcontroller
15 SRDY
WR
DT/R
DEN/DS
ALE
BHE {ADEN}
VSS
UCLK/USBSOF/USBSCI
RTR_HU
CTS_HU
RXD_HU
TXD_HU
VCC
AD0
AD8
A0
A1
A2
VSS
AD1
AD9
A3
A4
AD2
AD10
VCC
120
119
118
117
116
115
114
113
112
111
110
109
108
107
VCC
DRQ1
RSVD_104/UXVRCV
RSVD_103/UXVOE
RSVD_102/UTXDMNS
RSVD_101/UTXDPLS
VSS
HOLD
HLDA {CLKSEL1}
RD
WLB
WHB
BSIZE8
AD15
AD7
VCC
A19
A18
A17
AD14
AD6
A16
A15
VSS
VSS_USB
USBD+/UDPLS
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
VSS
A5
A6
A7
A8
AD3
AD11
VCC
A9
A10
AD4
AD12
VSS
S6
S2
S1
S0 {USBXCVR}
RESOUT
VCC
CLKOUT
VSS
QS0
QS1
A11
A12
AD5
AD13
VCC
A13
A14
VSS
VSS_A
X1
X2
USBX1
USBX2
VCC_A
VCC
VCC_USB
USBD–/UDMNS
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
VCC
RSVD_119
RSVD_118
RSVD_117
RSVD_116
NMI
RES
INT5
INT4
INT3
INT2
INT1
VSS
INT0
8
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106
PIN AND SIGNAL TABLES
Table 1 on page 10 and Table 2 on page 11 show the
pi n s s o r t ed by pi n nu mb e r a nd s i g na l n a me,
respectively.
Table 4 on page 13 contains the signal descriptions
(grouped alphabetically within function). The table
includes columns listing the multiplexed functions and
I/O type. Table 3 on page 12 defines terms used in
Table 4.
Refer to Appendix A, “Pin Tables,” on page A-1 for an
a d d i ti on a l gr o u p o f t a bl e s w i th t h e f o l l ow i n g
information:
■ Power-on reset (POR) pin defaults including pin
numbers and multiplexed functions—Table 23 on
page A-2.
■ Multiplexed signal tradeoffs—Table 24 on page A-5.
■ Programmable I/O pins ordered by PIO pin number
and multiplexed signal name, respectively, including pin numbers, multiplexed functions, and pin
configurations following system reset—Table 25 on
page A-6 and Table 26 on page A-7.
■ Pinstraps and
page A-8.
options—Table 27
on
■ Pin and signal summary showing signal name and
alternate function, pin number, I/O type, maximum
load values, POR default function, reset state, POR
default operation, hold state, and voltage—Table 29
on page A-10.
In all tables the brackets, [ ], indicate alternate,
multiplexed functions, and braces, { }, indicate reset
configuration pins (pinstraps). The line over a pin name
indicates an active Low. The word pin refers to the
physical wire; the word signal refers to the electrical
signal that flows through it.
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pinstrap
9
Table 1. PQFP Pin Assignments—Sorted by Pin Number1
Pin No. Name—Left Side
Pin No. Name—Bottom Side Pin No. Name—Right Side
1
VSS
41
VSS
81
USBD+/UDPLS
121
VSS
2
SDEN/PIO10
42
A5
82
VSS_USB
122
PIO18
3
SCLK/PIO11
43
A6
83
VSS
123
PIO17
4
SDATA/PIO12
44
A7
84
A15
124
DRQ0/PIO9
5
PCS0/PIO13
{USBSEL1}
45
A8
85
A16
125
VCC
6
PCS1/PIO14
{USBSEL2}
46
AD3
86
AD6
126
MCS0/PIO4{UCSX8}
7
PCS2
47
AD11
87
AD14
127
MCS1/CAS1
8
PCS3
48
VCC
88
A17
128
MCS2/CAS0
9
PCS4/PIO3{CLKSEL2}
49
A9
89
A18
129
MCS3/RAS1/PIO5
10
PCS5/PIO2
50
A10
90
A19
130
VSS
11
PCS6/PIO32
51
AD4
91
VCC
131
LCS/RAS0
12
VCC
52
AD12
92
AD7
132
UCS{ONCE}
13
PCS7/PIO31
53
VSS
93
AD15
133
VCC
14
ARDY/PIO8
54
S6
94
BSIZE8
134
PIO41
15
SRDY/PIO35
55
S2
95
WHB
135
PIO40
16
WR/PIO15
56
S1
96
WLB
136
PIO39
17
DT/R/PIO29
57
S0{USBXCVR}
97
RD
137
PIO38
18
DEN/DS/PIO30
58
RESOUT
98
HLDA {CLKSEL1}
138
PIO36
19
ALE/PIO33
59
VCC
99
HOLD
139
PIO37
20
BHE/PIO34{ADEN}
60
CLKOUT
100
VSS
140
VSS
21
VSS
61
VSS
101
RSVD_101/UTXDPLS
141
TMROUT0/PIO28
22
UCLK/PIO21/USBSOF/
USBSCI
62
QS0
102
RSVD_102/UTXDMNS
142
TMRIN0/PIO27
23
RTR_HU/PIO47
63
QS1
103
RSVD_103/UXVOE
143
TMROUT1/PIO1
24
CTS_HU/PIO46
64
A11
104
RSVD_104/UXVRCV
144
TMRIN1/PIO0
25
RXD_HU/PIO16
65
A12
105
DRQ1
145
INT6/PIO19
26
TXD_HU
66
AD5
106
VCC
146
INT7/PIO7
27
VCC
67
AD13
107
INT0
147
INT8/PWD/PIO6
28
AD0
68
VCC
108
VSS
148
VCC
29
AD8
69
A13
109
INT1
149
PIO23
30
A0
70
A14
110
INT2
150
PIO22
31
A1
71
VSS
111
INT3
151
PIO45
32
A2
72
VSS_A
112
INT4
152
PIO44
33
VSS
73
X1
113
INT5
153
PIO42
34
AD1
74
X2
114
RES
154
PIO43
35
AD9
75
USBX1
115
NMI
155
VSS
36
A3
76
USBX2
116
RSVD_116
156
RTR_U/PIO25
37
A4
77
VCC_A
117
RSVD_117
157
CTS_U/PIO24
38
AD2
78
VCC
118
RSVD_118
158
RXD_U/PIO26
39
AD10
79
VCC_USB
119
RSVD_119
159
TXD_U/PIO20
40
VCC
80
USBD–/UDMNS
120
VCC
160
VCC
Notes:
1. See Table 25, “PIOs Sorted by PIO Number,” on page A-6 for PIOs sorted by PIO number.
10
Pin No. Name—Top Side
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Table 2.
Signal Name
PQFP Pin Assignments—Sorted by Signal Name1
Pin No. Signal Name
Pin No.
Signal Name
Pin No. Signal Name
Pin No.
A0
30
CLKOUT
60
PIO40
135
USBD–/UDMNS
80
A1
31
CTS_HU/PIO46
24
PIO41
134
USBX1
75
A2
32
CTS_U/PIO24
157
PIO42
153
USBX2
76
A3
36
DEN/DS/PIO30
18
PIO43
154
VCC
12
A4
37
DRQ0/PIO9
124
PIO44
152
VCC
27
A5
42
DRQ1
105
PIO45
151
VCC
40
A6
43
DT/R/PIO29
17
QS0
62
VCC
48
A7
44
HLDA {CLKSEL1}
98
QS1
63
VCC
59
99
RD
97
VCC
68
107
RES
114
VCC
78
A8
45
HOLD
A9
49
INT0
A10
50
INT1
109
RESOUT
58
VCC
91
A11
64
INT2
110
RSVD_101/UTXDPLS
101
VCC
106
A12
65
INT3
111
RSVD_102/UTXDMNS
102
VCC
120
A13
69
INT4
112
RSVD_103/UXVOE
103
VCC
125
A14
70
INT5
113
RSVD_104/UXVRCV
104
VCC
133
A15
84
INT6/PIO19
145
RSVD_116
116
VCC
148
A16
85
INT7/PIO7
146
RSVD_117
117
VCC
160
A17
88
INT8/PWD/PIO6
147
RSVD_118
118
VCC_A
77
A18
89
LCS/RAS0
131
RSVD_119
119
VCC_USB
79
A19
90
MCS0/PIO4{UCSX8}
126
RTR_HU/PIO47
23
VSS
1
AD0
28
MCS1/CAS1
127
RTR_U/PIO25
156
VSS
21
AD1
34
MCS2/CAS0
128
RXD_HU/PIO16
25
VSS
33
AD2
38
MCS3/RAS1/PIO5
129
RXD_U/PIO26
158
VSS
41
AD3
46
NMI
115
S0 {USBXCVR}
57
VSS
53
AD4
51
PCS0/PIO13{USBSEL1}
5
S1
56
VSS
61
AD5
66
PCS1/PIO14{USBSEL2}
6
S2
55
VSS
71
AD6
86
PCS2
7
S6
54
VSS
83
AD7
92
PCS3
8
SCLK/PIO11
3
VSS
100
AD8
29
PCS4/PIO3{CLKSEL2}
9
SDATA/PIO12
4
VSS
108
AD9
35
PCS5/PIO2
10
SDEN/PIO10
2
VSS
121
AD10
39
PCS6/PIO32
11
SRDY/PIO35
15
VSS
130
AD11
47
PCS7/PIO31
13
TMRIN0/PIO27
142
VSS
140
AD12
52
PIO17
123
TMRIN1/PIO0
144
VSS
155
AD13
67
PIO18
122
TMROUT0/PIO28
141
VSS_A
72
AD14
87
PIO22
150
TMROUT1/PIO1
143
VSS_USB
82
AD15
93
PIO23
149
TXD_HU
26
WHB
95
ALE/PIO33
19
PIO36
138
TXD_U/PIO20
159
WLB
96
ARDY/PIO8
14
PIO37
139
UCLK/USBSOF/
USBSCI/PIO21
22
WR/PIO15
16
BHE/PIO34{ADEN}
20
PIO38
137
UCS {ONCE}
132
X1
73
BSIZE8
94
PIO39
136
USBD+/UDPLS
81
X2
74
Notes:
1. See Table 26, “PIOs Sorted by Signal Name,” on page A-7 for PIOs sorted by signal name.
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Signal Descriptions
Table 3.
Table 4 on page 13 contains a description of the
Am186CU USB microcontroller signals. Table 3
describes the terms used in Table 4. The signals are
organized alphabetically within the following functional
groups:
■ Bus interface/general-purpose
DMA request (page 13)
■ Clocks/reset/watchdog timer (page 17)
Term
[]
Indicates the pin alternate function; a pin
defaults to the signal named without the
brackets.
{}
Indicates the reset configuration pin (pinstrap).
pin
Refers to the physical wire.
reset
An external or power-on reset is caused by
asserting RES. An internal reset is initiated by
the watchdog timer. A system reset is one that
resets the Am186CU USB microcontroller (the
CPU plus the internal peripherals) as well as
any external peripherals connected to
RESOUT. An external reset always causes a
system reset; an internal reset can optionally
cause a system reset.
signal
Refers to the electrical signal that flows across
a pin.
■ Power and ground (page 18)
■ Debug support (page 18)
■ Chip selects (page 19)
■ DRAM (page 20)
■ Interrupts (page 20)
■ Programmable timers (page 21)
SIGNAL
■ Asynchronous serial ports (UART and High-Speed
UART) (page 22)
■ Synchronous serial interface (SSI) (page 23)
Definition
General terms
■ Reserved (page 18)
■ Programmable I/O (PIOs) (page 21)
Signal Descriptions Table Definitions
A line over a signal name indicates that the
signal is active Low; a signal name without a
line is active High.
Signal types
■ Universal Serial Bus (USB) (page 23)
B
Bidirectional
For pinstraps refer to Table 27, “Reset Configuration
Pins (Pinstraps),” on page A-8.
H
High
LS
Programmable to hold last state of pin
O
Totem pole output
OD
Open drain output
OD-O
Internal pulldown resistor
PU
Internal pullup resistor
STI
Schmitt trigger input
STI-OD
TS
12
Open drain output or totem pole output
PD
Schmitt trigger input or open drain output
Three-state output
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Table 4.
Signal Name
Multiplexed
Signal(s)
Signal Descriptions
Type Description
BUS INTERFACE/GENERAL-PURPOSE DMA REQUEST
A19–A0
—
O
Address Bus supplies nonmultiplexed memory or I/O addresses to the system
one half of a CLKOUT period earlier than the multiplexed address and data bus
(AD15–AD0). During bus-hold or reset conditions, the address bus is threestated with pulldowns.
When the lower or upper chip-select regions are configured for DRAM mode, the
A19–A0 bus provides the row and column addresses at the appropriate times.
The upper and lower memory chip-select ranges can be individually configured
for DRAM mode.
AD15–AD0
—
B
Address and Data Bus time-multiplexed pins supply memory or I/O addresses
and data to the system. This bus can supply an address to the system during the
first period of a bus cycle (t1). It transmits (write cycle) or receives (read cycle)
data to or from the system during the remaining periods of that cycle (t2, t3, and
t4). The address phase of these pins can be disabled—see the {ADEN} pin
description in Table 27, “Reset Configuration Pins (Pinstraps),” on page A-8.
During a reset condition, the address and data bus is three-stated with
pulldowns, and during a bus hold it is three-stated.
In addition, during a reset the state of the address and data bus pins (AD15–
AD0) is latched into the Reset Configuration (RESCON) register. This feature
can be used to provide software with information about the external system at
reset time.
ALE
[PIO33]
O
Address Latch Enable indicates to the system that an address appears on the
address and data bus (AD15–AD0). The address is guaranteed valid on the
falling edge of ALE.
ALE is three-stated and has a pulldown resistor during bus-hold or reset
conditions.
ARDY
[PIO8]
STI
Asynchronous Ready is a true asynchronous ready that indicates to the
microcontroller that the addressed memory space or I/O device will complete a
data transfer. The ARDY pin is asynchronous to CLKOUT and is active High. To
guarantee the number of wait states inserted, ARDY or SRDY must be
synchronized to CLKOUT. If the falling edge of ARDY is not synchronized to
CLKOUT as specified, an additional clock period can be added.
To always assert the ready condition to the microcontroller, tie ARDY and SRDY
High. If the system does not use ARDY, tie the pin Low to yield control to SRDY.
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Table 4. Signal Descriptions (Continued)
Signal Name
BHE
Multiplexed
Signal(s)
[PIO34]
{ADEN}
Type Description
O
Bus High Enable: During a memory access, BHE and the least-significant
address bit (AD0) indicate to the system which bytes of the data bus (upper,
lower, or both) participate in a bus cycle. The BHE and AD0 pins are encoded as
follows:
Data Byte Encoding
BHE
AD0
0
0
Type of Bus Cycle
Word transfer
0
1
High byte transfer (bits 15–8)
1
0
Low byte transfer (bits 7–0)
1
1
Refresh
BHE is asserted during t1 and remains asserted through t3 and tW. BHE does not
require latching. BHE is three-stated with a pullup during bus-hold and reset
conditions.
WLB and WHB implement the functionality of BHE and AD0 for high and low byte
write enables, and they have timing appropriate for use with the nonmultiplexed
bus interface.
BHE also signals DRAM refresh cycles when using the multiplexed address and
data (AD) bus. A refresh cycle is indicated when both BHE and AD0 are High.
During refresh cycles, the AD bus is driven during the t1 phase and three-stated
during the t2, t3, and t4 phases. The value driven on the A bus is undefined during
a refresh cycle. For this reason, the A0 signal cannot be used in place of the AD0
signal to determine refresh cycles.
—
BSIZE8
DEN
[DS]
[PIO30]
[DRQ0]
PIO9
DRQ1
[DS]
—
DEN
[PIO30]
O
Bus Size 8 is asserted during t1–t4 to indicate an 8-bit cycle, or is deasserted to
indicate a 16-bit cycle.
O
Data Enable supplies an output enable to an external data-bus transceiver. DEN
is asserted during memory and I/O cycles. DEN is deasserted when DT/R
changes state. DEN is three-stated with a pullup during bus-hold or reset
conditions.
STI
DMA Requests 0 and 1 indicate to the microcontroller that an external device is
ready for a DMA channel to perform a transfer. DRQ1–[DRQ0] are leveltriggered and internally synchronized. DRQ1–[DRQ0] are not latched and must
remain active until serviced.
STI
O
Data Strobe provides a signal where the write cycle timing is identical to the read
cycle timing. When used with other control signals, [DS] provides an interface for
68K-type peripherals without the need for additional system interface logic.
When [DS] is asserted, addresses are valid. When [DS] is asserted on writes,
data is valid. When [DS] is asserted on reads, data can be driven on the AD bus.
Following a reset, this pin is configured as DEN. The pin is then configured by
software to operate as [DS].
DT/R
14
[PIO29]
O
Data Transmit or Receive indicates which direction data should flow through an
external data-bus transceiver. When DT/R is asserted High, the microcontroller
transmits data. When this pin is deasserted Low, the microcontroller receives
data. DT/R is three-stated with a pullup during a bus-hold or reset condition.
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Table 4. Signal Descriptions (Continued)
Signal Name
Multiplexed
Signal(s)
HLDA
{CLKSEL1}
Type Description
O
Bus-Hold Acknowledge is asserted to indicate to an external bus master that
the microcontroller has relinquished control of the local bus. When an external
bus master requests control of the local bus (by asserting HOLD), the
microcontroller completes the bus cycle in progress, then relinquishes control of
the bus to the external bus master by asserting HLDA and three-stating S2–S0,
AD15–AD0, S6, and A19–A0. The following are also three-stated and have
pullups: UCS, LCS, MCS3–MCS0, PCS7–PCS0, DEN, RD, WR, BHE, WHB,
WLB, and DT/R. ALE is three-stated and has a pulldown.
When the external bus master has finished using the local bus, it indicates this
to the microcontroller by deasserting HOLD. The microcontroller responds by
deasserting HLDA.
If the microcontroller requires access to the bus (for example, for refresh), the
microcontroller deasserts HLDA before the external bus master deasserts
HOLD. The external bus master must be able to deassert HOLD and allow the
microcontroller access to the bus. See the timing diagrams for bus hold on
page 60.
HOLD
—
STI
Bus-Hold Request indicates to the microcontroller that an external bus master
needs control of the local bus.
The microcontroller HOLD latency time—the time between HOLD request and
HOLD acknowledge—is a function of the activity occurring in the processor
when the HOLD request is received. A HOLD request is second only to DRAM
refresh requests in priority of activity requests received by the processor. This
implies that if a HOLD request is received just as a DMA transfer begins, the
HOLD latency can be as great as four bus cycles. This occurs if a DMA word
transfer operation is taking place from an odd address to an odd address. This
is a total of 16 clock cycles or more if wait states are required. In addition, if
locked transfers are performed, the HOLD latency time is increased by the
length of the locked transfer. HOLD latency is also potentially increased by
DRAM refreshes.
The board designer is responsible for properly terminating the HOLD input.
For more information, see the HLDA pin description above.
RD
—
O
Read Strobe indicates to the system that the microcontroller is performing a
memory or I/O read cycle. RD is guaranteed not to be asserted before the
address and data bus is three-stated during the address-to-data transition. RD
is three-stated with a pullup during bus-hold or reset conditions.
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Table 4. Signal Descriptions (Continued)
Signal Name
Multiplexed
Signal(s)
S0
{USBXCVR}
S1
—
S2
—
Type Description
O
Bus Cycle Status 2–0 indicate to the system the type of bus cycle in progress.
S2 can be used as a logical memory or I/O indicator, and S1 can be used as a
data transmit or receive indicator. S2–S0 are three-stated during bus hold and
three-stated with a pullup during reset. The S2–S0 pins are encoded as follows:
Bus Status Pins
S6
SRDY
—
[PIO35]
S2
S1
S0
Bus Cycle
0
0
0
Reserved
0
0
1
Read data from I/O
0
1
0
Write data to I/O
0
1
1
Halt
1
0
0
Instruction fetch
1
0
1
Read data from memory
1
1
0
Write data to memory
1
1
1
None (passive)
O
Bus Cycle Status Bit 6: This signal is asserted during t 1–t4 to indicate a DMAinitiated bus cycle or a refresh cycle. S6 is three-stated during bus hold and
three-stated with a pulldown during reset.
STI
Synchronous Ready indicates to the microcontroller that the addressed
memory space or I/O device will complete a data transfer. The SRDY pin accepts
an active High input synchronized to CLKOUT.
Using SRDY instead of ARDY allows a relaxed system timing because of the
elimination of the one-half clock period required to internally synchronize ARDY.
To always assert the ready condition to the microcontroller, tie SRDY High. If the
system does not use SRDY, tie the pin Low to yield control to ARDY.
WHB
—
O
WLB
—
O
Write High Byte and Write Low Byte indicate to the system which bytes of the
data bus (upper, lower, or both) participate in a write cycle. In 80C186
microcontroller designs, this information is provided by BHE, AD0, and WR.
However, by using WHB and WLB, the standard system interface logic and
external address latch that were required are eliminated.
WHB is asserted with AD15–AD8. WHB is the logical AND of BHE and WR. This
pin is three-stated with a pullup during bus-hold or reset conditions.
WLB is asserted with AD7–AD0. WLB is the logical AND of AD0 and WR. This
pin is three-stated with a pullup during bus-hold or reset conditions.
WR
16
[PIO15]
O
Write Strobe indicates to the system that the data on the bus is to be written to
a memory or I/O device. WR is three-stated with a pullup during bus-hold or reset
conditions.
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Table 4. Signal Descriptions (Continued)
Signal Name
Multiplexed
Signal(s)
Type Description
CLOCKS/RESET/WATCHDOG TIMER
CLKOUT
—
O
Clock Output supplies the clock to the system. Depending on the values of the
CPU mode select pinstraps, {CLKSEL1} and {CLKSEL2}, CLKOUT operates at
either the PLL frequency or the source input frequency during PLL Bypass
mode. (See Table 27, “Reset Configuration Pins (Pinstraps),” on page A-8.)
CLKOUT remains active during bus-hold or reset conditions.
The DISCLK bit in the SYSCON register can be set to disable the CLKOUT
signal. Refer to the Am186™CC/CH/CU Microcontrollers Register Set Manual,
order #21916.
All synchronous AC timing specifications not associated with SSI, UARTs, and
the USB are synchronous to CLKOUT.
RES
—
STI
Reset requires the microcontroller to perform a reset. When RES is asserted,
the microcontroller immediately terminates its present activity, clears its internal
logic, and on the deassertion of RES, transfers CPU control to the reset address
FFFF0h.
RES must be asserted for at least 1 ms to allow the internal circuits to stabilize.
RES can be asserted asynchronously to CLKOUT because RES is synchronized
internally. For proper initialization, VCC must be within specifications, and
CLKOUT must be stable for more than four CLKOUT periods during which RES
is asserted.
If RES is asserted while the watchdog timer is performing a watchdog-timer reset,
the external reset takes precedence over the watchdog-timer reset. This means
that the RESOUT signal asserts as with any external reset and the WDTCON
register will not have the RSTFLAG bit set. In addition, the microcontroller will exit
reset based on the external reset timing (i.e., 4.5 clocks after the deassertion of
RES rather than 216 clocks after the watchdog timer timeout occurred).
The microcontroller begins fetching instructions approximately 6.5 CLKOUT
periods after RES is deasserted. This input is provided with a Schmitt trigger to
facilitate power-on RES generation via a resistor-capacitor (RC) network.
RESOUT
—
O
Reset Out indicates that the microcontroller is being reset (either externally or
internally), and the signal can be used as a system reset to reset any external
peripherals connected to RESOUT.
During an external reset, RESOUT remains active (High) for two clocks after
RES is deasserted. The microcontroller exits reset and begins the first valid bus
cycle approximately 4.5 clocks after RES is deasserted.
[UCLK]
[USBSOF]
[USBSCI]
PIO21
STI
UART Clock can be used instead of the processor clock as the source clock for
either the UART or the High-Speed UART. The source clock for the UART and the
High-Speed UART are selected independently and both can use the same source.
USBX1
—
STI
USBX2
—
O
USB Controller Crystal Input (USBX1) and USB Controller Crystal Output
(USBX2) provide connections for a fundamental mode, parallel-resonant crystal
used by the internal USB oscillator circuit.
X1
—
STI
X2
—
O
If the CPU crystal is used to generate the USB clock, USBX1 must be pulled down.
CPU Crystal Input (X1) and CPU Crystal Output (X2) provide connections for
a fundamental mode, parallel-resonant crystal used by the internal oscillator
circuit. If an external oscillator is used, inject the signal directly into X1 and leave
X2 floating.
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Table 4. Signal Descriptions (Continued)
Signal Name
Multiplexed
Signal(s)
Type Description
PINSTRAPS (See Table 27, “Reset Configuration Pins (Pinstraps),” on page A-8.)
RESERVED
RSVD_101
UTXDPLS
—
RSVD_102
UTXDMNS
—
RSVD_103
UXVOE
—
RSVD_104
UXVRCV
—
The pins RSVD_104–RSVD_101 are reserved unless pinstrap {USBXCVR} is
sampled Low on the rising edge of RESET.
The pins RSVD_119–RSVD_116 are reserved.
All reserved pins should not be connected.
RSVD_116
—
—
RSVD_117
—
—
RSVD_118
—
—
RSVD_119
—
—
VCC (15)
—
STI
Digital Power Supply pins supply power (+3.3 ± 0.3 V) to the Am186CU USB
microcontroller logic.
VCC _A (1)
—
STI
Analog Power Supply pin supplies power (+3.3 ± 0.3 V) to the oscillators and
PLLs.
VCC _USB (1)
—
STI
USB Power Supply pin supplies power (+3.3 ± 0.3 V) to the USB block.
VSS (15)
—
STI
Digital Ground pins connect the Am186CU USB microcontroller logic to the
system ground.
VSS _A (1)
—
STI
Analog Ground pin connects the oscillators and PLLs to the system ground.
VSS _USB (1)
—
STI
USB Ground pin connects the USB block to the system ground.
QS0
—
O
QS1
—
O
POWER AND GROUND
DEBUG SUPPORT
Queue Status 1–0 values provide information to the system concerning the
interaction of the CPU and the instruction queue. The pins have the following
meanings:
Queue Status Pins
QS1 QS0 Queue Operation
0
0
None
0
1
First opcode byte fetched from queue
1
0
Queue was initialized
1
1
Subsequent byte fetched from queue
The following signals are also used by emulators: A19–A0, AD15–AD0, {ADEN}, ALE, ARDY, BHE, BSIZE8, CAS1–CAS0,
CLKOUT, {CLKSEL2–CLKSEL1}, HLDA, HOLD, LCS, MCS3–MCS0, NMI, {ONCE}, QS1–QS0, RAS1–RAS0, RD, RES,
RESOUT, S2–S0, S6, SRDY, UCS, {UCSX8}, WHB, WLB, WR. See the Am186CC/CH/CU Microcontrollers User’s Manual,
order #21914, for more information.
18
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Table 4. Signal Descriptions (Continued)
Signal Name
Multiplexed
Signal(s)
Type Description
CHIP SELECTS
LCS
[RAS0]
O
Lower Memory Chip Select indicates to the system that a memory access is in
progress to the lower memory block. The base address and size of the lower
memory block are programmable up to 512 Kbyte. LCS can be configured for 8bit or 16-bit bus size. LCS is three-stated with a pullup resistor during bus-hold
or reset conditions.
[MCS0]
{UCSX8}
PIO4
O
MCS1
[CAS1]
MCS2
[CAS0]
Midrange Memory Chip Selects 3–0 indicate to the system that a memory
access is in progress to the corresponding region of the midrange memory block.
The base address and size of the midrange memory block are programmable.
The midrange chip selects can be configured for 8-bit or 16-bit bus size. The
midrange chip selects are three-stated with pullup resistors during bus-hold or
reset conditions.
[MCS3]
[RAS1]
PIO5
[MCS0] can be programmed as the chip select for the entire middle chip select
address range.
Unlike the UCS and LCS chip selects that operate relative to the earlier timing of
the nonmultiplexed A address bus, the MCS outputs assert with the multiplexed
AD address and data bus timing.
PCS0
[PIO13]
{USBSEL1}
PCS1
[PIO14]
{USBSEL2}
PCS2
—
PCS3
—
[PCS4]
PIO3
{CLKSEL2}
[PCS5]
PIO2
[PCS6]
PIO32
[PCS7]
PIO31
UCS
{ONCE}
O
Peripheral Chip Selects 7–0 indicate to the system that an access is in
progress to the corresponding region of the peripheral address block (either I/O
or memory address space). The base address of the peripheral address block is
programmable. PCS7–PCS0 are three-stated with pullup resistors during bushold or reset conditions.
Unlike the UCS and LCS chip selects that operate relative to the earlier timing of
the nonmultiplexed A address bus, the PCS outputs assert with the multiplexed
AD address and data bus timing.
O
Upper Memory Chip Select indicates to the system that a memory access is in
progress to the upper memory block. The base address and size of the upper
memory block are programmable up to 512 Kbytes. UCS is three-stated with a
weak pullup during bus-hold or reset conditions.
The UCS can be configured for an 8-bit or 16-bit bus size out of reset. For
additional information, see the {UCSX8} pin description in Table 27, “Reset
Configuration Pins (Pinstraps),” on page A-8.
After reset, UCS is active for the 64-Kbyte memory range from F0000h to FFFFFh,
including the reset address of FFFF0h.
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Table 4. Signal Descriptions (Continued)
Signal Name
Multiplexed
Signal(s)
Type Description
DRAM
[CAS0]
MCS2
[CAS1]
MCS1
[RAS0]
[RAS1]
O
Column Address Strobes 1–0: When either the upper or lower chip select
regions are configured for DRAM, these pins provide the column address strobe
signals to the DRAM. The CAS signals can be used to perform byte writes in a
manner similar to WLB and WHB, respectively (i.e., [CAS0] corresponds to the
low byte (WLB) and [CAS1] corresponds to the high byte (WHB)).
LCS
O
Row Address Strobe 0: When the lower chip select region is configured to
DRAM, this pin provides the row address strobe signal to the lower DRAM bank.
[MCS3]
PIO5
O
Row Address Strobe 1: When the upper chip select region is configured to
DRAM, this pin provides the row address strobe signal to the upper DRAM bank.
STI
Nonmaskable Interrupt indicates to the microcontroller that an interrupt request
has occurred. The NMI signal is the highest priority hardware interrupt and cannot
be masked. The microcontroller always transfers program execution to the
location specified by the nonmaskable interrupt vector in the microcontroller’s
interrupt vector table when NMI is asserted.
INTERRUPTS
NMI
—
Although NMI is the highest priority hardware interrupt source, it does not
participate in the priority resolution process of the maskable interrupts. There is
no bit associated with NMI in the interrupt in-service or interrupt request
registers. This means that a new NMI request can interrupt an executing NMI
interrupt service routine. As with all hardware interrupts, the interrupt flag (IF) is
cleared when the processor takes the interrupt, disabling the maskable interrupt
sources. However, if maskable interrupts are re-enabled by software in the NMI
interrupt service routine (for example, via the STI instruction), the fact that an
NMI is currently in service does not have any effect on the priority resolution of
maskable interrupt requests. For this reason, it is strongly advised that the
interrupt service routine for NMI should not enable the maskable interrupts.
An NMI transition from Low to High is latched and synchronized internally, and it
initiates the interrupt at the next instruction boundary. To guarantee that the interrupt
is recognized, the NMI pin must be asserted for at least one CLKOUT period.
The board designer is responsible for properly terminating the NMI input.
—
INT5–INT0
STI
[INT6]
PIO19
STI
[INT7]
PIO7
STI
[INT8]
[PWD]
PIO6
STI
Maskable Interrupt Requests 8–0 indicate to the microcontroller
microcontroller that an external interrupt request has occurred. If the individual
pin is not masked, the microcontroller transfers program execution to the
location specified by the associated interrupt vector in the microcontroller’s
interrupt vector table.
Interrupt requests are synchronized internally and can be edge-triggered or
level-triggered. The interrupt polarity is programmable.To guarantee interrupt
recognition for edge-triggered interrupts, the user should hold the interrupt
source for a minimum of five system clocks. A second interrupt from the same
source is not recognized until after an acknowledge of the first.
The board designer is responsible for properly terminating the INT8–INT0 inputs.
Also configurable as interrupts are PIO5, PIO15, PIO27, PIO29, PIO30, PIO33, PIO34, and PIO35.
(See the Am186CC/CH/CU Microcontrollers User’s Manual, order #21914 for more information.)
20
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Table 4. Signal Descriptions (Continued)
Signal Name
Multiplexed
Signal(s)
Type Description
PROGRAMMABLE I/O (PIOS)
PIO47–PIO0
(For multiplexed
signals see Table
25, “PIOs Sorted by
PIO Number,” on
page A-6 and Table
26, “PIOs Sorted by
Signal Name,” on
page A-7.)
B
Shared Programmable I/O pins can be programmed with the following
attributes: PIO function (enabled/disabled), direction (input/output), and weak
pullup or pulldown.
After a reset, the PIO pins default to various configurations. The column entitled
“Pin Configuration Following System Reset” in Table 25 on page A-6 and
Table 26 on page A-7 lists the defaults for the PIOs. Most of the PIO pins are
configured as PIO inputs with pullup after reset. See Table 29 on page A-10 for
detailed termination information for all pins. The system initialization code must
reconfigure any PIO pins as required.
PIO5, PIO15, PIO27, PIO29, PIO30, and PIO33–PIO35 are capable of
generating an interrupt on the shared interrupt channel 14.
The multiplexed signals PIO33/ALE, PIO8/ARDY, PIO34/BHE, PIO30/DEN,
PIO29/DT/R, PIO14/PCS1–PIO13/PCS0, PIO35/SRDY, and PIO15/WR default
to non-PIO operation at reset.
The following PIO signals are multiplexed with alternate signals that can be used
by emulators: PIO8, PIO15, PIO33, PIO34, and PIO35. Consider any emulator
requirements for the alternate signals before using these pins as PIOs.
PROGRAMMABLE TIMERS
[PWD]
[INT8]
PIO6
STI
Pulse-Width Demodulator: If pulse-width demodulation is enabled, [PWD]
processes a signal through the Schmitt trigger input. [PWD] is used internally to
drive [TMRIN0] and [INT8], and [PWD] is inverted internally to drive [TMRIN1]
and an additional internal interrupt. If interrupts are enabled and Timer 0 and
Timer 1 are properly configured, the pulse width of the alternating [PWD] signal
can be calculated by comparing the values in Timer 0 and Timer 1.
In PWD mode, the signals [TMRIN0]/PIO27 and [TMRIN1]/PIO0 can be used as
PIOs. If they are not used as PIOs they are ignored internally.
The additional internal interrupt used in PWD mode uses the same interrupt
channel as [INT7]. If [INT7] is used, it must be assigned to the shared interrupt
channel.
[TMRIN0]
PIO27
STI
[TMRIN1]
PIO0
STI
Timer Inputs 1–0 supply a clock or control signal to the internal microcontroller
timers. After internally synchronizing a Low-to-High transition on [TMRIN1]–
[TMRIN0], the microcontroller increments the timer. [TMRIN1]–[TMRIN0] must
be tied High if not being used. When PIO is enabled for one or both, the pin is
pulled High internally.
[TMRIN1]–[TMRIN0] are driven internally by [INT8]/[PWD] when pulse-width
demodulation functionality is enabled. The [TMRIN1]–[TMRIN0] pins can be
used as PIOs when pulse-width demodulation is enabled.
[TMROUT0]
PIO28
O
[TMROUT1]
PIO1
O
Timer Outputs 1–0 supply the system with either a single pulse or a continuous
waveform with a programmable duty cycle. [TMROUT1]–[TMROUT0] are threestated during bus-hold or reset conditions.
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21
Table 4. Signal Descriptions (Continued)
Signal Name
Multiplexed
Signal(s)
Type Description
ASYNCHRONOUS SERIAL PORTS (UART AND HIGH-SPEED UART)
UART
[RXD_U]
PIO26
STI
Receive Data UART is the asynchronous serial receive data signal that supplies
data from the asynchronous serial port to the microcontroller.
[TXD_U]
PIO20
O
[CTS_U]
PIO24
STI
Clear-To-Send UART provides the Clear-to-Send signal from the asynchronous
serial port when hardware flow control is enabled for the port. The [CTS_U]
signal gates the transmission of data from the serial port transmit shift register.
When [CTS_U] is asserted, the transmitter begins transmission of a frame of
data, if any is available. If [CTS_U] is deasserted, the transmitter holds the data
in the serial port transmit shift register. The value of [CTS_U] is checked only at
the beginning of the transmission of the frame. [CTS_U] and [RTR_U] form the
hardware handshaking interface for the UART.
[RTR_U]
PIO25
O
Ready-To-Receive UART provides the Ready-to-Receive signal for the
asynchronous serial port when hardware flow control is enabled for the port. The
[RTR_U] signal is asserted when the associated serial port receive data register
does not contain valid, unread data. [CTS_U] and [RTR_U] form the hardware
handshaking interface for the UART.
STI
Receive Data High-Speed UART is the asynchronous serial receive data signal
that supplies data from the high-speed serial port to the microcontroller.
O
Transmit Data High-Speed UART is the asynchronous serial transmit data
signal that supplies data to the high-speed serial port from the microcontroller.
Transmit Data UART is the asynchronous serial transmit data signal that
supplies data to the asynchronous serial port from the microcontroller.
HIGH-SPEED UART
[RXD_HU]
PIO16
TXD_HU
—
[CTS_HU]
PIO46
STI
Clear-To-Send High-Speed UART provides the Clear-to-Send signal from the
high-speed asynchronous serial port when hardware flow control is enabled for
the port. The [CTS_HU] signal gates the transmission of data from the serial port
transmit shift register. When [CTS_HU] is asserted, the transmitter begins
transmission of a frame of data, if any is available. If [CTS_HU] is deasserted,
the transmitter holds the data in the serial port transmit shift register. The value
of [CTS_HU] is checked only at the beginning of the transmission of the frame.
[CTS_HU] and [RTR_HU] form the hardware handshaking interface for the HighSpeed UART.
[RTR_HU]
PIO47
O
Ready-To-Receive High-Speed UART provides the Ready-to-Receive signal to
the high-speed asynchronous serial port when hardware flow control is enabled
for the port. The [RTR_HU] signal is asserted when the associated serial port
receive data register does not contain valid, unread data. [CTS_HU] and
[RTR_HU] form the hardware handshaking interface for the High-Speed UART.
22
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Table 4. Signal Descriptions (Continued)
Signal Name
Multiplexed
Signal(s)
Type Description
SYNCHRONOUS SERIAL INTERFACE (SSI)
[SCLK]
PIO11
O
Serial Clock provides the clock for the synchronous serial interface to allow
synchronous transfers between the Am186CU USB microcontroller and a slave
device.
[SDATA]
PIO12
B
Serial Data is used to transmit and receive data between the Am186CU USB
microcontroller and a slave device on the synchronous serial interface.
[SDEN]
PIO10
O
Serial Data Enable enables data transfers on the synchronous serial interface.
USB External Transceiver Gated Differential Plus and USB External
Transceiver Gated Differential Minus are inputs from the external USB
transceiver used to detect single-ended zero and error conditions. The signals
have the following meanings:
UNIVERSAL SERIAL BUS (USB)
[UDMNS]
USBD–
STI
[UDPLS]
USBD+
STI
USB External Transceiver Signals
B
UDPLS
UDMNS
Status
0
0
Single-Ended Zero (SE0)
0
1
Full speed
1
0
Reserved
1
1
Error
USBD+
[UDPLS]
USB Differential Plus and USB Differential Minus form the bidirectional
electrical data interface for the USB port. The pins form a differential pair that can
be connected to a physical USB connector without an external transceiver.
USBD–
[UDMNS]
B
[USBSCI]
[UCLK]
[USBSOF]
PIO21
STI
[USBSOF]
[UCLK]
[USBSCI]
PIO21
O
USB Start of Frame is a 1-kHz frame pulse used to synchronize USB
isochronous transfers to an external device on a frame-by-frame basis.
UTXDMNS
RSVD_102
O
USB External Transceiver Differential Minus is an output that drives the
external transceiver differential driver minus input.
UTXDPLS
RSVD_101
O
USB External Transceiver Differential Plus is an output that drives the
external transceiver differential driver plus input.
UXVOE
RSVD_103
O
USB External Transceiver Transmit Output Enable is an output that enables
the external transceiver. UXVOE signals the external transceiver that USB data
is being output by the Am186CU USB microcontroller. When Low this pin
enables the transceiver output, and when High this pin enables the receiver.
UXVRCV
RSVD_104
STI
USB External Transceiver Differential Receiver is a data input received from
the external transceiver differential receiver.
USB Sample Clock Input is used to synchronize an external clock to the
internal USB peripheral controller for isochronous transfers.
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23
ARCHITECTURAL OVERVIEW
The arc hitectural goal of the Am186CU USB
m i c r o c o n t r o l l e r i s t o p r ov i d e c o m p r e h e n s i ve
communications features on a processor running the
widely known x86 instruction set. The Am186CU USB
microcontroller combines a USB peripheral controller
and general communications peripherals with the
Am186 microcontroller. This highly integrated
microcontroller provides system cost and performance
advantages for a wide range of communications
applications. Figure 1 is a block diagram of the
Am186CU USB microcontroller followed by sections
providing an overview of the features.
Serial Communications Peripherals
Am186
CPU
Chip
Selects
(14)
Glueless
Interface
to RAM/ROM
PIOs
(48)
Watchdog
Timer
DRAM
Controller
Memory Peripherals
Timers
(3)
Interrupt
Controller
(17 Ext.
Sources)
SmartDMA
Channels
(4)
GeneralPurpose
DMA (4)
USB
Synchronous
Serial
Interface (SSI)
UART
High-Speed
UART with
Autobaud
System Peripherals
Figure 1. Am186CU USB Microcontroller Block Diagram
Detailed Description
■ Universal Serial Bus (USB) peripheral controller
works with a wide variety of USB devices
– Implements high-speed 12-Mbit/s device function
– Allows an unlimited number of device descriptors
– Supports a total of six endpoints: one control
endpoint; one interrupt endpoint; and four data
endpoints that can be either bulk or isochronous,
IN or OUT
– Two data endpoints have 16-byte FIFOs; two
data endpoints have 64-byte FIFOs
– Fully integrated differential driver directly
supports the USB interface (D+, D–)
– Specialized hardware supports adaptive
isochronous data streams
– General-purpose DMA and SmartDMA™
channels supported
■ 8 Direct Memory Access (DMA) channels
– Four buffer descriptor ring SmartDMA channels
for the USB bulk and isochronous endpoints
– Four general-purpose DMAs support the two
integrated asynchronous serial ports and/or USB
endpoints; two DMA channels have external
DMA request inputs
24
■ High-speed asynchronous serial interface
provides enhanced UART functions
–
–
–
–
–
Capable of sustained operation at 460 Kbaud
7-, 8-, or 9-bit data transfers
FIFOs to support high-speed operation
DMA support available
Automatic baud-rate detection that allows
emulation of a Hayes AT-compatible modem
– Independent baud generator with clock input
source programmable to use CPU or external
clock input pin
■ Asynchronous serial interface (UART)
– 7-, 8-, or 9-bit data transfers
– DMA support available
– Independent baud generator with clock input
source programmable to use CPU or external
clock input pin
■ Synchronous Serial Interface (SSI) provides
half-duplex, bidirectional interface to highspeed peripherals
– Useful with many telecommunication interface
peripherals such as codecs, line interface units,
and transceivers
– Selectable device-select polarity
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– Selectable bit shift order on transmit and receive
– Glueless connection to AMD Subscriber Line
Audio Processing Circuit (SLAC™) devices
■ Clocking options offer high flexibility
– CPU can run in 1x, 2x, or 4x mode
– USB can run in 2x or 4x mode
– USB can run from system clock if running at
48 MHz, allowing entire system to run from one
12-MHz or 24-MHz crystal
– Separate crystal oscillator inputs for CPU and
USB clock sources
Am186™ Embedded CPU
and adding the 16-bit offset value to yield a 20-bit
physical address (see Figure 2). This allows for a
1-Mbyte physical address size.
All members of the Am186 family, including the
Am186CU USB microcontroller, are compatible with
the original industry-standard 186 parts, and build on
the same core set of 186 registers, address generation,
I/O space, instruction set, segments, data types, and
addressing modes.
All instructions that address operands in memory must
specify the segment value and the 16-bit offset value.
For speed and compact instruction encoding, the
segment register used for physical address generation
is implied by the addressing mode used (see Table 5).
Memory Organization
I/O Space
Memory is organized in sets of segments. Each
segment is a linear contiguous sequence of 64K (216)
8-bit bytes. Memor y is addressed using a twocomponent address consisting of a 16-bit segment
value and a 16-bit offset. The 16-bit segment values
are contained in one of four internal segment registers
(CS, DS, SS, or ES). The physical address is
calculated by shifting the segment value left by 4 bits
15
Shift
Left
4 Bits
1
0
2
A
15
0
19
1
2
A
4
Segment Base
Logical Address
0
0
2
2
Offset
0
0
0
0
2
19
1
4
0
15
0
The I/O space consists of 64K 8-bit or 32K 16-bit ports.
Separate instructions (IN/INS and OUT/OUTS)
address the I/O space with either an 8-bit port address
specified in the instruction, or a 16-bit port address in
the DX register. Eight-bit port addresses are zeroextended such that A15–A8 are Low.
2
0
2
A
6
2
Physical Address
To Memory
Memory Reference Needed
Instructions
Local Data
Stack
External Data (Global)
Figure 2.
Two-Component Address Example
Table 5.
Segment Register Selection Rules
Segment Register Used Implicit Segment Selection Rule
Code (CS)
Instructions (including immediate data)
Data (DS)
All data references
All stack pushes and pops;
Stack (SS)
any memory references that use the BP register
Extra (ES)
All string instruction references that use the DI register as an index
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25
Serial Communications Support
The Am186CU USB microcontroller supports four
serial interfaces. This includes a USB peripheral
controller, two UARTs, and a synchronous serial
interface.
Universal Serial Bus
The Am186CU USB microcontroller includes a highly
flexible integrated USB peripheral controller that
de s i g ne r s c an u s e t o im p l e me n t a va r ie t y o f
microcontroller-based USB peripheral devices for
telephony, audio, or other high-end applications. This
integrated USB peripheral controller can provide a
significant system-cost reduction compared to other
platforms that require a separate USB controller.
The Am186CU USB microcontroller can be used in
self-powered USB peripherals that use the full-speed
signalling rate of 12 Mbit/s. The USB low-speed rate
(1.5 Mbit/s) is not supported. An integrated USB
transceiver is provided to minimize system device
count and cost, but an external transceiver can be used
instead, if necessary.
The USB controller does not support USB host or hub
f u n c t i o n s . H o w e ve r, t h e A m 1 8 6 C U U S B
microcontroller can be used to implement USB
peripheral functions in a device that also contains
separate USB hub circuitry.
In addition, the Am186CU USB microcontroller
supports the following:
■ An unlimited number of device descriptors
■ A total of 6 endpoints: 1 control endpoint, 1 interrupt
endpoint, and 4 data endpoints that can be
configured as control, interrupt, bulk, or isochronous.
The interrupt, bulk, and isochronous endpoints can
be configured for the IN or OUT direction.
■ Two data endpoints have 16-byte FIFOs; two data
endpoints have 64-byte FIFOs
■ Fully integrated differential driver, which supports
the USB interface directly
■ Specialized hardware, which supports adaptive
isochronous data streams
■ General-purpose DMA and SmartDMA channels
Four SmartDMA Channels
The Am186CU USB microcontroller provides four
SmartDMA channels, which provide a faster method
for moving data between peripherals and memory with
lower CPU utilization. Smar tDMA transmits and
receives data across multiple memory buffers and a
sophisticated buffer-chaining mechanism. These
channels are always used in pairs: transmitter and
receiver. The transmit channels can only transfer data
from memory to a peripheral; the receive channels can
only transfer data from a peripheral to memory.
26
The four SmartDMA channels (two pairs) support USB
endpoints A, B, C, or D.
In addition to the four Smar tDMA channels, the
Am186CU USB microcontroller provides four generalpurpose DMA channels (see page 27).
Two Asynchronous Serial Ports
Th e A m 18 6C U US B m ic r o c on tr o ll e r ha s two
asynchronous serial ports (a UART and a High-Speed
UART) which provide full-duplex, bidirectional data
transfer at speeds of up to 115.2 Kbaud or up to 460
Kbaud, respectively. The High-Speed UART has
16-byte transmit and 32-byte receive FIFOs, specialcharac ter matching, and automatic baud-rate
detection, suitable for implementation of a Hayescompatible modem interface to a host PC. There is also
a lower speed UART that typically is used for a low
baud-rate system configuration port or debug port.
Each of these UARTs can derive its baud rate from the
system clock or from a separate baud-rate generator
clock input. Both UARTs support 7-, 8-, or 9-bit data
transfers; address bit generation and detection in 7- or
8-bit frames; one or two stop bits; even, odd, or no
parity; break generation and detection; hardware flow
control; and DMA to and/or from the serial ports using
the general-purpose DMA channels.
Synchronous Serial Port
The Am186CU USB microcontroller includes one SSI
por t that provides a half-duplex, bidirectional,
communications interface between the microcontroller
and other system components. This interface is
typically used by the microcontroller to monitor the
status of other system devices and/or to configure
these devices under software control. In a
communications application, these devices could be
system components such as audio codecs, line
interface units, and transceivers. The SSI supports
data transfer speeds of up to 25 Mbit/s with a 50-MHz
system clock.
The SSI port operates as an interface master, with the
other attached devices acting as slave devices. Using
this protocol, the Am186CU USB microcontroller sends
a command byte to the attached device, and then
follows that with either a read or write of a byte of data.
The SSI port consists of three I/O pins: an enable
(SDEN), a clock (SCLK), and a bidirectional data pin
(SDATA). SDEN can be used directly as an enable for
a single attached device. When more than one device
requires control via the SSI, PIOs can be used to
provide enable pins for those devices.
The Am186CU SSI is, in general, software compatible
with software written for the Am186EM SSI. (Additional
features have been added to the Am186CU SSI
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implementation.) The Am186CU USB microcontroller
features the additional capability of selecting the
polarity of the SCLK and SDEN pins, as well as the shift
order of bits on the SDATA pin (least-significant-bit first
versus most-significant-bit first). The SSI port also
offers a programmable clock divisor (dividing the clock
from 2 to 256 in power of 2 increments), a bidirectional
transmit/receive shift register, and direct connection to
AMD SLAC devices.
System Peripherals
Interrupt Controller
function. If an application does not need the alternate
func tion, the as soc iate d PIO c an be us ed by
programming the PIO registers.
If a pin is enabled to function as a PIO signal, the
alternate function is disabled and does not affect the
pin. A PIO signal can be configured to operate as an
input or output, with or without internal pullup or
pulldown resistors (pullup or pulldown depends on the
pin configuration and is not user-configurable), or as an
open-drain output. Additionally, eight PIOs can be
configured as external interrupt sources.
The Am186CU USB microcontroller features an
interrupt controller that arranges the 36 maskable
interrupt requests by priority and presents them one at
a time to the CPU. In addition to interrupts managed by
t h e i n t e r r u p t c o n t r o l l e r, t h e A m 1 8 6 C U U S B
m i c r o c o n t r o l l e r s u p p o r t s e i g h t n o n m a s k a bl e
interrupts—an external or internal nonmaskable
interrupt (NMI), a trace interrupt, and software
interrupts and exceptions.
Three Programmable Timers
The interrupt controller supports the 36 maskable
interrupt sources through the use of 15 channels.
Because of this, most channels support multiple
interrupt sources. These channels are programmable to
support the external interrupt pins and/or various
peripheral devices that can be configured to generate
interrupts. The 36 maskable interrupt sources include 19
internal sources and 17 external sources.
Timer 2 is not connected to any external pins. It can be
used by software to generate interrupts, or it can be
polled for real-time coding and time-delay applications.
Timer 2 can also be used as a prescaler to Timer 0 and
Timer 1, or as a DMA request source.
Four General-Purpose DMA Channels
The Am186CU USB microcontroller provides four
general-purpose DMA channels that can be used for
data transfer between memory and I/O spaces (i.e.,
memory-to-I/O or I/O-to-memory) or within the same
space (i.e., memory-to-memory or I/O-to-I/O). In
addition, the Am186CU USB microcontroller supports
data transfer between peripherals and memory or I/O.
Internal peripherals that support general-purpose DMA
are the USB peripheral controller, Timer 2, and the two
asynchronous serial ports (UART and High-Speed
UART). External peripherals support DMA transfers
through the external DMA request pins. Each generalpurpose channel can accept synchronized DMA
requests from one of four sources: the DMA request pins
(DRQ1–DRQ0), Timer 2, the UARTs, or the USB
controller. In addition, system software can initialize and
start unsynchronized DMA transfers.
In addition to the four general-purpose channels, the
Am186CU USB microcontroller provides four
SmartDMA channels (see page 26).
48 Programmable I/O Signals
The Am186CU USB microcontroller provides 48 userprogrammable input/output signals (PIOs). Thirty-four
of the 48 signals share a pin with at least one alternate
There are three 16-bit programmable timers in the
Am186CU USB microcontroller. Timers 0 and 1 are
highly versatile and are each connected to two external
pins (each one has an input and an output). These two
timers can be used to count or time external events that
drive the timer input pins. Timers 0 and 1 can also be
used to generate nonrepetitive or variable-duty-cycle
waveforms on the timer output pins.
The source clock for Timer 2 is one-fourth of the
system clock frequency. The source clock for Timers 0
and 1 can be configured to be one-fourth of the system
clock, or they can be driven from their respective timer
input pins. When driven from a timer input pin, the timer
is counting the “event” of an input transition.
The Am186CU USB microcontroller also provides a
pulse width demodulation (PWD) option so that a
toggling input signal’s Low state and High state
durations can be measured.
Hardware Watchdog Timer
The Am186CU USB microcontroller provides a fullfeatured watchdog timer, which includes the ability to
generate Non-Maskable Interrupts (NMIs), microcontroller
resets, and system resets when the timeout value is
reached. The timeout value is programmable and ranges
from 210 to 226 processor clocks.
The watchdog timer is used to regain control when a
system has failed due to a software error or to failure of
an external device to respond in the expected way.
Software errors can sometimes be resolved by
recapturing control of the execution sequence via a
watchdog-timer-generated NMI. When an external
device fails to respond, or responds incorrectly, it may be
necessary to reset the controller or the entire system,
including external devices. The watchdog timer provides
the flexibility to support both NMI and reset generation.
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27
Memory and Peripheral Interface
System Interfaces
The Am186CU USB microcontroller bus interface
controls all accesses to the peripheral control block
(PCB), memory-mapped and I/O-mapped external
peripherals, and memory devices. Internal peripherals
are accessed by the bus interface through the PCB.
The bus interface features programmable bus sizing;
individually selectable chip selects for the upper (UCS)
memory space, lower (LCS) memory space, all non-UCS,
non-LCS and I/O memory spaces; separate byte-write
enables; and, boot option from an 8- or 16-bit device.
The integrated peripherals are controlled by 16-bit
read/write registers. The peripheral registers are
contained within an internal 1-Kbyte control block. At
reset, the base of the PCB is set to FC00h in I/O space.
The registers are physically located in the peripheral
devices they control, but they are addressed as a single
1-Kbyte block. For details on the PCB registers, refer to
the Am186™CC/CH/CU Microcontrollers Register Set
Manual, order #21916.
Accesses to the PCB should be performed by direct
processor actions. The use of DMA to write or read
from the PCB results in unpredictable behavior, except
where explicit exception is made to suppor t a
peripheral function, such as the High-Speed UART
transmit and receive data registers.
The 80C186 and 80C188 microcontrollers use a
multiplexed address and data (AD) bus. The address is
present on the AD bus only during the t1 clock phase.
The Am186CU USB microcontroller continues to
provide the multiplexed AD bus and, in addition,
provide a nonmultiplexed address (A) bus. The A bus
provides an address to the system for the complete bus
cycle (t 1 –t 4 ). During refresh cycles, the AD bus is
driven during the t1 phase and the values are unknown
during the t2, t3, and t4 phases. The value driven on the
A bus is undefined during a refresh cycle.
28
The nonmultiplexed address bus (A19–A0) is valid onehalf CLKOUT cycle in advance of the address on the
AD bus. When used with the modified UCS and LCS
outputs and the byte write enable signals, the A19–A0
bus provides a seamless interface to SRAM, DRAM,
and Flash/EPROM memory systems.
For systems where power consumption is a concern, it
is possible to disable the address from being driven on
the AD bus on the microcontroller during the normal
address portion of the bus cycle for accesses to upper
(UCS) and/or lower (LCS) address spaces. In this
mode, the affected bus is placed in a high-impedance
state during the address portion of the bus cycle. This
feature is enabled through the DA bits in the Upper
Memory Chip Select (UMCS) and Lower Memory Chip
Select (LMCS) registers.
When address disable is in effect, the number of
signals that assert on the bus during all normal bus
cycles to the associated address space is reduced,
thus decreasing power consumption, reducing
processor switching noise, and preventing bus
contention with memory devices and peripherals when
operating at high clock rates.
If the ADEN pin is asserted during processor reset, the
value of the DA bits in the UMCS and LMCS registers is
ignored and the address is driven on the AD bus for all
accesses, thus preserving the industry-standard
80C186 and 80C188 microcontrollers’ multiplexed
address bus and providing suppor t for existing
emulation tools. For details on these registers, refer to
the Am186™CC/CH/CU Microcontrollers Register Set
Manual, order #21916.
Figure 3 on page 29 shows the affected signals during
a normal read or write operation. The address and data
are multiplexed onto the AD bus.
Figure 4 on page 29 shows a bus cycle when address
bus disable is in effect, which causes the AD bus to
operate in a nonmultiplexed data-only mode. The A bus
has the address during a read or write operation.
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t1
t2
Address
Phase
t3
t4
Data
Phase
CLKOUT
A19–A0
Address
AD15–AD0
(Read)
Address
AD15–AD0
(Write)
Address
Data
Data
LCS or UCS
MCSx, PCSx
Figure 3. Am186CU Microcontroller Address Bus — Default Operation
t1
Address
Phase
t2
t3
Data
Phase
t4
CLKOUT
A19–A0
Address
AD7–AD0
(Read)
Data
AD15–AD8
(Read)
Data
AD15–AD0
(Write)
Data
LCS or UCS
Figure 4.
Am186CU Microcontroller—Address Bus Disable In Effect
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29
Bus Interface
The bus interface controls all accesses to external
peripherals and memory devices. External accesses
include those to memory devices, as well as those to
memory-mapped and I/O-mapped peripherals and the
per ipheral contr ol block. The Am186CU USB
microcontroller provides an enhanced bus interface
unit with the following features:
■ Nonmultiplexed address bus
■ Separate byte write enables for high and low bytes
■ Output enable
The standard 80C186/80C188 multiplexed address
and data bus requires system interface logic and an external address latch. On the Am186CU USB microcontroller, byte write enables and a nonmultiplexed
address bus can reduce design costs by eliminating
this external logic.
Nonmultiplexed Address Bus
The nonmultiplexed address bus (A19–A0) is valid onehalf CLKOUT cycle in advance of the address on the
AD bus. When used with the modified UCS and LCS
outputs and the byte write enable signals, the A19–A0
bus provides a seamless interface to external SRAM,
and Flash memory/EPROM systems.
Byte Write Enables
The Am186CU USB microcontroller provides the WHB
(Write High Byte) and WLB (Write Low Byte) signals
that act as byte write enables.
WHB is the logical OR of BHE and WR. WHB is Low
when both BHE and WR are Low. WLB is the logical
OR of A0 and WR. WLB is Low when A0 and WR are
both Low.
T h e b y t e w r i t e e n a b l e s a r e d r i ve n w i t h t h e
nonmultiplexed address bus as required for the write
timing requirements of common SRAMs.
Output Enable
The Am186CU USB microcontroller provides the RD
(Read) signal that acts as an output enable for memory
or peripheral devices. The RD signal is Low when a
word or byte is read by the microcontroller.
DRAM Support
To support DRAM, the Am186CU USB microcontroller
has a fully integrated DRAM controller that provides a
glueless interface to 25–70-ns Extended Data Out
(EDO) DRAM. (EDO DRAM is sometimes called
Hyper-Page Mode DRAM.) Up to two banks of 4-Mbit
(256 Kbit x 16 bit) DRAM can be accessed. Page Mode
DRAM, Fast Page Mode DRAM, Asymmetrical DRAM,
and 8-bit wide DRAM are not suppor ted. The
microcontroller provides zero-wait state operation at up
to 50 MHz with 40-ns DRAM. This allows designs
30
requiring larger amounts of memory to save system
cost over SRAM designs by taking advantage of low
DRAM memory costs.
The DRAM interface uses various chip select pins to
implement the RAS/CAS interface required by DRAMs.
The DRAM controller drives the RAS/CAS interface
appropriately during both normal memory accesses
and during refresh. All signals required are generated
by the microcontroller and no external logic is required.
The DRAM multiplexed address pins are connected to
t he o d d a d d r e s s p i ns o f t h e A m 1 8 6 C U U S B
microcontroller, starting with A1 on the Am186CU USB
microcontroller connecting to MA0 on the DRAM. The
correct row and column addresses are generated on
these odd address pins during a DRAM access.
The RAS pins are multiplexed with LCS and MCS3,
allowing a DRAM bank to be present in either high or
low memory space. The MCS1 and MCS2 function as
the upper and lower CAS pins, respectively, and define
which byte of data in a 16-bit DRAM is being accessed.
The microcontroller supports the most common DRAM
refresh option, CAS-Before-RAS. All refresh cycles
contain three wait states to support the DRAMs at
various frequencies. The DRAM controller never
performs a burst access. All accesses are single
accesses to DRAM. If the PCS chip selects are
decoded to be in the DRAM address range, PCS
accesses take precedence over the DRAM.
Chip Selects
The Am186CU USB microcontroller provides six chip
select outputs for use with memory devices and eight
more for use with peripherals in either memory or I/O
space. The six memory chip selects can be used to
address three memory ranges. Each peripheral chip
select addresses a 256-byte block offset from a
programmable base address.
The microcontroller can be programmed to sense a
ready signal for each of the peripheral or memory chip
select lines. A bit in each chip select control register
determines whether the external ready signal is
required or ignored.
The chip selects can control the number of wait states
inserted in the bus cycle. Although most memory and
peripheral devices can be accessed with three or less
wait states, some slower devices cannot. This feature
allows devices to use wait states to slow down the bus.
The chip select lines are active for all memory and I/O
cycles in their programmed areas, whether they are
generated by the CPU or by the integrated DMA unit.
General enhancements over the original 80C186
include bus mastering (three-state) support for all chip
selects and activation only when the associated
register is written, not when it is read.
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Clock Control
The processor supports clock rates from 16 to 50 MHz
using an integrated cr ystal oscillator and PLL.
Commercial and industrial temperature ratings are
available. Separate cr ystal oscillator inputs are
provided for the USB and CPU. Flexibility is provided to
run the entire device from a 12- or 24-MHz crystal
when the USB is in use. The CPU can run in 1x, 2x, or
4x PLL mode. The USB can run in 2x or 4x PLL mode.
In-Circuit Emulator Support
Because pins are an expensive resource, many play a
dual role, and the programmer selects PIO operation or
an alternate function. However, a pin configured to be
a PIO may also be required for emulation support.
Therefore, it is impor tant that before a design is
committed to hardware, a user should contact potential
emulator suppliers for a list of their emulator’s pin
r e q ui r em e n ts. T h e fo l l owi n g P I O s i g na l s ar e
multiplexed with alternate signals that may be used by
emulators: PIO8, PIO15, PIO33–PIO35.
The Am186CU USB microcontroller was designed to
minimize conflicts. In most cases, pin conflict is
avoided. For example, if the ALE signal is required for
multiplex bus support, then it is not programmed as
PIO33. If the multiplexed AD bus is not used, then ALE
ca n be pro gramme d as a P IO pi n. And i f th e
multiplexed bus is not in use, then the emulator does
not require the ALE signal. However, an emulator is
likely to always use the de-multiplexed address,
regardless of how the AD bus is programmed.
APPLICATIONS
The Am186CU USB microcontroller with its integrated
USB and other communications features provides a
highly integrated, cost-effective solution for a wide
range of te lec ommunic atio ns an d netwo r k in g
applications.
■ xDSL Applications: Today’s xDSL applications,
such as high-speed ADSL modems, require data
handling of 2 Mbit/s or greater and can take advantage of the USB interface for easy connectivity to
the PC.
■ USB Peripheral Devices: These devices will become more common as the PC market embraces
the USB protocol. In addition to implementing communications devices, the USB peripheral controller
makes the Am186CU USB microcontroller suitable
for certain PC desktop applications such as a USB
camera interface, ink-jet printers, and scanners.
■ General Communications Applications: The
Am186CU USB microcontroller will also find a home
in general embedded applications, because many
devices will incorporate communications capability in
the future. The microcontroller is especially attractive
for 186 designs adding USB.
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31
CLOCK GENERATION AND CONTROL
The Am186CU USB microcontroller clocks include the
general system clock (CLKOUT), USB clock, and the
baud rate generator clock for UART and High-Speed
UART.
The SSI and the timers (Timers 0, 1, and 2) derive their
clocks from the system clock.
Features
The Am186CU USB microcontroller clocks include the
following features and characteristics:
■ Two independent crystal-controlled oscillators that
use exter nal fundamental mode cr ystals or
oscillators to generate the system input clock and
the USB input clock.
■ Two independent internal PLLs, one of which
generates a system clock (CLKOUT) that is 1x, 2x,
or 4x the system input clock, and one that
generates the 48-MHz clock required for the USB
from either a48-, 24-, or 12-MHz input.
■ Single clock source operation possible by sharing
the clock source between the system and the USB.
■ SSI clock (SCLK) is derived from the system clock,
divided by 2, 4, 8, 16, 32, 64, 128, or 256.
■ Timers 0 and 1 can be configured to be driven by
the timer input pins (TMRIN1, TMRIN0) or at onefourth of the system clock. Timer 2 is driven at onefourth of the system clock.
■ UART clock can be derived from the internal system
clock frequency or from the UART clock (UCLK)
input.
See Figure 5 on page 33 for a diagram of the basic
clock generation and Figure 6 on page 34 for
suggested clock frequencies and modes.
System Clock
The system PLL generates frequencies from 16 to
50 MHz. The reference for the system PLL can vary
from 8 to 40 MHz, depending on the PLL mode selected
and the desired system frequency (see Figure 6 on
page 34).
■ Bypassing the internal PLL. The external reference
generated from either a crystal or an external
oscillator input is used to generate the system clock.
For more information about bypassing the internal
PLL, refer to “PLL Bypass Mode” on page 35.
USB Clock
The USB PLL provides the 48-MHz clock that is
required for USB full-speed operation. This clock is
divided down to provide a 12-MHz clock that supports
the full-speed USB rate (12 Mbit/s). The low-speed rate
of 1.5 Mbit/s is not supported. The USB PLL modes are
chosen by the state of the {USBSEL1} and {USBSEL2}
pins during reset. For these pinstrap settings see Table
27, “Reset Configuration Pins (Pinstraps),” on page
A-8.
The USB clock can be generated in one of two ways:
■ Using the system clock. In this mode, the system
PLL is restricted to 48-MHz operation only.
Note: When using the system clock for the USB clock
source, the designer must externally pull down the
USBX1 input.
■ Using its own internal 48-MHz PLL. This PLL can
run in 2x or 4x mode and requires a 12- or 24-MHz
reference that can be generated by either the
integrated cr ystal-controlled oscillator or an
external oscillator input.
Note: The system clock must be a minimum of
24 MHz when using the USB peripheral controller and
its internal 48-MHz PLL.
The USB specification requires a frequency tolerance
of less than 2500 ppm, which must be met whether
using an external clock source, a crystal on USBX1–
USBX2, or clock sharing by system and USB. When
using a crystal, some frequency tolerance margin must
be allowed to account for the differences in external
loading capacitances, etc. The usual rule of thumb is to
specify a crystal with a frequency tolerance of one half
the required frequency tolerance.
The system PLL modes are chosen by the state of the
{CLKSEL1} and {CLKSEL2} pins during reset. For these
pinstrap settings see Table 27, “Reset Configuration
Pins (Pinstraps),” on page A-8.
The system clock can be generated in one of two ways:
■ Using the internal PLL running at 1x, 2x, or 4x the
reference clock. The reference clock can be
generated from an external crystal using the
integrated oscillator or an external oscillator input.
32
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■ The system can be run at 24 MHz by sharing an
exter nal clock reference (X1) with the USB
(USBX1). A 12-MHz source can be used with the
system PLL in 2x mode and the USB PLL in 4x
mode, or a 24-MHz source can be used with the
system in 1x mode and the USB in 2x mode.
Clock Sharing by System and USB
The CPU and USB clocks can be generated from a
single source in one of two ways:
■ The system can run at 48 MHz by using the system
clock for the USB clock.
Note: When using the system clock for the USB clock
source, the designer must externally pull down the
USBX1 input.
Am186CU USB Microcontroller
System Clock
1x
X1
PLL
X2
CLKOUT
2x
4x
PLL Bypass Mode
{CLKSEL2}–{CLKSEL1}
USBX1
2x
USBX2
PLL
48-MHz
USB Clock
4x
{USBSEL2}–{USBSEL1}
Figure 5.
System and USB Clock Generation
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33
System Operating Frequency
20 MHz
0 MHz
30 MHz
24 MHz
40 MHz
32 MHz
16 MHz
8-MHz to 12.5-MHz Xtal or Clock
4x Mode
8-MHz to 25-MHz Xtal or Clock
2x Mode
16-MHz to 40-MHz Xtal or Clock1
1x Mode
PLL
Bypass
Mode
50 MHz
0-MHz to 24-MHz Xtal or Clock
PLL Bypass Mode
1The
1x Mode
2x Mode
4x Mode
crystal oscillator is not guaranteed above 40 MHz.
Figure 6.
Suggested System Clock Frequencies, Clock Modes, and Crystal Frequencies
Crystal-Driven Clock Source
The internal oscillator circuit is designed to function
with an external parallel-resonant fundamental mode
crystal. The crystal frequency can vary from 8 to 40
MHz, depending on the PLL mode selected and desired system frequency.
When selecting a crystal, the load capacitance should
always be specified (C L ). This value can cause
variance in the oscillation frequency from the desired
specified value (resonance). The load capacitance and
the loading of the feedback network have the following
relationship:
Table 6. Crystal Parameters1
Parameter
Min.
Value
Max.
Value
Units
Frequency
8
40
MHz
ESR
8–24 MHz
20
90
ohms
24–50 MHz
20
60
ohms
Load capacitance
10
—
pF
Notes:
1. If the crystal is used for a USB clock source, there is an
additional clock jitter tolerance.
CL = (C1 ⋅ C2) + CS
(C1 + C2)
X1/USBX1
where CS is the stray capacitance of the circuit.
Table 6 shows crystal parameter values. Figure 7
shows the system clocks using an external crystal and
the integrated oscillator. The specific values for C 1 and
C 2 must be determined by the designer and are
dependent on the characteristics of the chosen crystal
and board design.
34
Xtal
X2/USBX2
C1
Figure 7.
C2
External Interface to Support Clocks—
Fundamental Mode Crystal
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External Clock Source
The internal oscillator also can be driven by an external
clock source. The external clock source should be
connected to the input of the inverting amplifier (X1 or
USBX1) with the output (X2 or USBX2) left
unconnected. Figure 8 shows the system clocks using
an external clock source (oscillator bypass).
Note: X1, X2, USBX1, and USBX2 are not 5-V
tolerant and have a maximum input equal to VCC.
NC
Figure 8.
When changing frequency in PLL Bypass mode, the X1
input must not have any short or “runt” pulses. At
24 MHz, the nominal High/Low time is 21 ns. The
actual High times and Low times must not fall below 16
ns. These values allow a 60%/40% duty cycle at X1.
In the Am186CU microcontroller, the USB PLL and
USBX1 determine the USB clock. USB requires the
system clock to be 24 MHz or greater. Therefore,
disable the USB peripheral controller before slowing
the system clock to less than 24 MHz. If USB is not
used, the USBX1 can be pulled down.
X1/USBX1
External
Clock
the X1 input frequency. This mode must be used with
an external clock source. For PLL Bypass mode
enabling, see Table 27, “Reset Configuration Pins
(Pinstraps),” on page A-8.
X2/USBX2
UART Baud Clock
External Interface to Support Clocks—
External Clock Source
Static Operation
The UART and High-Speed UART have two possible
clock sources: the system clock or the UCLK input pin.
If UCLK is used for the UART clock, the system clock
must be at least the same frequency as UCLK. The
clock configurations are shown graphically in Figure 9.
The Am186CU USB microcontroller is a fully static
design and can be placed in static mode by stopping
the input clock. See the PLL Bypass Mode discussion
below.
The baud clock is generated by dividing the clock
source by the value of the baud rate divisor register.
The serial port logic can select its baud rate clock from
either an external pin (UCLK) or from the system clock.
Note: It is the responsibility of the system designer to
ensure that no short clock phases are generated when
starting or stopping the clock.
The system or UCLK clock is selected independent of
any other settings.
PLL Bypass Mode
The Am186CU USB microcontroller provides a PLL
Bypass mode that allows the X1 input frequency to be
anywhere from 0 to 24 MHz. When the microcontroller
is in PLL Bypass mode, the CLKOUT frequency equals
The formula for determining the baud rate divisor
register value is:
BAUDDIV = (clock frequency/(16 • baud rate))
Note: UCLK cannot be clocked at a frequency higher
than the system clock frequency.
Oversample
Clock
System Clock
Baud
Divisor
UCLK
UART/High-Speed UART
Clock Select
Divide for
Oversampling
Baud Clock
Autobaud Clock
(High-Speed UART Only)
Figure 9. UART and High-Speed UART Clocks
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35
POWER SUPPLY OPERATION
CMOS dynamic power consumption is proportional to
the square of the operating voltage multiplied by
capacitance and operating frequency. Static CPU
operation can reduce power consumption by enabling
the system designer to reduce operating frequency
when possible. However, operating voltage is always the
dominant factor in power consumption. By reducing the
operating voltage from 5 V to 3.3 V for any device, the
power consumed is reduced by 56%.
Reduction of CPU and system logic operating voltage
dramatically reduces overall system power consumption. Additional power savings can be realized as lowvoltage mass storage and peripheral devices become
available.
Two basic strategies exist in designing systems
containing the Am186CU USB microcontroller. The
first strategy is to design a homogenous system in
which all logic components operate at 3.3 V. This
provides the lowest overall power consumption.
However, system designers may need to include
devices for which 3.3-V versions are not available.
In the second strategy, the system designer must then
design a mixed 5-V/3.3-V system. This compromise
enables the system designer to minimize the system
logic power consumption while still including the
functionality of the 5-V features. The choice of a mixed
voltage system design also involves balancing design
complexity with the need for the additional features.
Power Supply Connections
Connect all V CC pins together to the 3.3-V power
supply and all ground pins to a common system
ground.
Input/Output Circuitry
To accommodate current 5-V systems, the Am186CU
USB microcontroller has 5-V tolerant I/O drivers. The
drivers produce TTL-compatible drive output (minimum
2.4-V logic High) and receive TTL and CMOS levels (up
to VCC + 2.6 V). The following are some design issues
that should be considered with mixed 3.3-V/5-V
designs:
36
n During power-up, if the 3.3-V supply has a
significant delay in achieving stable operation
relative to 5-V supply, then the 5-V circuitry in the
system may start driving the processor’s inputs
above the maximum levels (V CC + 2.6 V). The
system design should ensure that the 5-V supply
does not exceed 2.6 V above the 3.3-V supply
during a power-on sequence.
n Preferably, all inputs are driven by sources that can
be three-stated during a system reset condition.
The system reset condition should persist until
stable V CC conditions are met. This should help
ensure that the maximum input levels are not
exceeded during power-up conditions.
n Preferably, all pullup resistors are tied to the 3.3-V
supply, which ensures that inputs requiring pullups
are not over stressed during power-up.
PIO Supply Current Limit
Each programmable I/O output is able to sink or source
a sustained 16-mA drive current. However, only 40 mA
of sustained PIO current is allowed for each supply pin
(VCC), and only 60 mA is allowed for each ground pin
(VSS).
To calculate the PIO current for each supply or ground
pin, sum the applicable current (source or sink) of all
PIO pins on either side of the pin (to the adjacent
corresponding pins), and divide the sum by two. The
resulting value should not exceed 40 mA for VCC or
60 mA for VSS.
Exclude the following pins from this calculation: 72
( V S S _ A) , 82 ( V S S _U SB ) , 77 ( V C C _A ) , an d 7 9
(VCC_USB).
For example, to calculate the PIO current for pin 83
(VSS), total the sustained sinking current for all PIO
pins between pin 71 (V SS ) and pin 100 (V SS ), and
divide the sum by two.
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ABSOLUTE MAXIMUM RATINGS 1
Parameter
Symbol
2
Minimum
Maximum
Unit
0
100
°C
Temperature under bias: Commercial
TC
Industrial
TA3
–40
+85
°C
Storage temperature
—
–65
+150
°C
Voltage on 5-V-tolerant pins4 with respect to ground
—
–0.5
VCC + 2.6
V
Voltage on other pins with respect to ground
—
–0.5
VCC + 0.5
V
5
Sustained PIO current on any supply (VCC) pin
—
40
—
mA
Sustained PIO current on any ground (VSS) pin5
—
60
—
mA
Notes:
1. Stresses above those listed under Absolute Maximum Ratings can cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
2. TC = case temperature.
3. TA = ambient temperature.
4. 5 V-tolerant pins are indicated in Table 29, “Pin List Summary,” on page A-10.
5. See “Power Supply Current” on page 39.
OPERATING RANGES1
Parameter
Symbol
2
Minimum
Maximum
Unit
Commercial
TC
0
100
°C
Industrial
TA3
–40
+ 85
°C
Supply voltage with respect to ground
VCC
3.0
3.6
V
Notes:
1. Operating Ranges define those limits between which the functionality of the device is guaranteed.
2. TC = case temperature.
3. TA = ambient temperature.
DRIVER CHARACTERISTICS—UNIVERSAL SERIAL BUS
Each USBD+ and USBD– pin connects through a
series resistor directly to the USB. The series resistor
value should be selected to achieve a total driver
impedance between 29 and 44 ohms, as required by
the USB version 1.0 specification. A 36-W ±1% series
resistor is recommended for each pin.
Characteristics of these two pins are defined in the
U S B ve r s i o n 1 . 0 s p e c i f i c a t i o n . C o n s u l t t h i s
specification for details about overall USB system
design. (At the time of this writing, the current USB
specification and related information can be obtained
on the Web at www.usb.org.)
The Am186CU USB microcontroller is guaranteed to
meet all USB specifications. Required analog
transceivers are integrated into the Am186CU USB
microcontroller.
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37
DC CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL OPERATING RANGES1
Symbol
VOH
Preliminary
Parameter
Maximum
2.4
—
V
VCC – 0.2
—
V
—
0.45
V
Output High voltage (IOH = –2.4 mA)
2
Unit
Minimum
VOH
Output High voltage (IOH = –0.1 mA)
VOL
Output Low voltage (IOL = 4.0 mA)
VIH5
5-V tolerant Input High voltage
2.0
VCC + 2.6
V
VIH
Input High voltage, except 5-V tolerant
2.0
VCC+0.3
V
VIL
Input Low voltage
–0.3
0.8
V
ILI
Input leakage current (0.1 V ˆ VOUT ˆ VCC)
(all pins except those with internal pullup/pulldown resistors)
—
±10
mA
ILO
Output leakage current3
(0.1 V ˆ VOUT ˆ VCC)
—
±15
mA
PCC
Power consumption
—
1.2
W
Notes:
1. Current out of pin is stated as a negative value.
2. Characterized but not tested.
3. This parameter is for three-state outputs where VOUT is driven on the three-state output.
CAPACITANCE
Symbol
38
Preliminary
Parameter
Minimum
Maximum
Unit
CIN
Input capacitance
—
15
pF
CCLK
Clock capacitance
—
15
pF
COUT
Output capacitance
—
20
pF
CI/O
I/O pin capacitance
—
20
pF
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MAXIMUM LOAD DERATING
■ No DC loads on the output buffers
All maximum delay numbers should be increased by
0.035 ns for every pF of load over the maximum load
(up to a maximum of 150 pF) specified in Table 29, “Pin
List Summary,” on page A-10.
■ Output capacitive load set to 30 pF
■ AD bus set to data only
■ PIOs are disabled
■ Timer, serial port, refresh, and DMA are enabled
POWER SUPPLY CURRENT
Table 7 shows the values that are used to calculate the
typical power consumption value for the Am186CU
USB microcontroller.
For the following typical system specification shown in
Figure 10, ICC has been measured at 6 mA per MHz of
system clock. The typical system is measured while the
system is executing code in a typical application with
nominal voltage and maximum case temperature.
Actual power supply current is dependent on system
design and may be greater or less than the typical ICC
figure presented here.
Table 7.
Typical Power Consumption Calculation
MHz ¼ ICC ¼ Volts / 1000 = P
Typical current in Figure 10 is given by:
ICC = 6 mA ¼ freq(MHz)
Please note that dynamic ICC measurements are dependent upon chip activity, operating frequency, output
buffer logic, and capacitive/resistive loading of the outputs. For these ICC measurements, the devices were
set to the following modes:
MHz
Typical ICC
Volts
Typical Power
in Watts
25
6
3.3
0.495
40
6
3.3
0.792
50
6
3.3
0.99
320
280
240
200
ICC (mA) 160
120
80
40
0
10
20
30
40
50
Clock Frequency (MHz)
Figure 10. Typical Icc Versus Frequency
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THERMAL CHARACTERISTICS—PQFP PACKAGE
The Am186CU USB microcontroller is specified for
operation with case temperature ranges from 0•C to
+100•C for 3.3 V ± 0.3 V (commercial). Case
temperature is measured at the top center of the
pack age a s s hown in Fi gur e 11 . Th e va r i ous
temperatures and ther mal resistances can be
determined using the equations in Figure 12 with
information given in Table 8.
The total thermal resistance is qJA; qJA is the sum of
qJC, the internal thermal resistance of the assembly,
and qCA, the case-to-ambient thermal resistance.
qJA
TC q
JC
qJA = qJC + qCA
Figure 11. Thermal Resistance(•C/Watt)
The variable P is power in watts. Power supply current
(ICC) is in mA per MHz of clock frequency.
qJA = qJC + qCA
P = ICC ¼ freq (MHz) ¼ VCC
TJ = TC + (P ¼ qJC)
TJ = TA + (P ¼ qJA)
¼ qJC)
¼ qCA)
TA = TJ – (P ¼ qJA)
TA = TC – (P ¼ qCA)
TC = TJ – (P
TC = TA + (P
Figure 12.
Thermal Characteristics Equations
Table 8. Thermal Characteristics (•C/Watt)
Package/Board
PQFP/2-Layer
PQFP/4-Layer
to 6-Layer
40
Airflow
(Linear Feet
per Minute)
qJC
qCA
qJA
0 fpm
7
38
45
200 fpm
7
32
39
400 fpm
7
28
35
600 fpm
7
26
33
0 fpm
5
18
23
200 fpm
5
16
21
400 fpm
5
14
19
600 fpm
5
12
17
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qCA
COMMERCIAL AND INDUSTRIAL SWITCHING CHARACTERISTICS AND WAVEFORMS
In the switching waveforms that follow, several
abbreviations are used to indicate the specific periods
of a bus cycle. These periods are referred to as time
states. A typical bus cycle is composed of four
consecutive time states: t1, t2, t3, and t4. Wait states,
which represent multiple t3 states, are referred to as tw
states. When no bus cycle is pending, an idle (ti) state
occurs.
bus; the demultiplexed address is referred to as the A
address bus. Figure 13 defines symbols used in the
switching waveform diagrams.
Table 9 on page 42 contains an alphabetical listing of
the switching parameter symbols (grouped by
function), and Table 10 on page 45 contains a
numerical listing of the switching parameter symbols
(grouped by function).
In th e sw i tc hi n g pa r am e t e r d e s c r i p ti o n s, t h e
multiplexed address is referred to as the AD address
WAVEFORM
INPUT
OUTPUT
Must be
Steady
Will be
Steady
May change
from H to L or
from H to threestate
Will be changing
from H to L or
from H to threestate
May change
from L to H or
from L to threestate
Will be changing
from L to H or
from L to threestate
Figure 13. Key to Switching Waveforms
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Table 9. Alphabetical Key to Switching Parameter Symbols
42
Parameter
Symbol
No.
Description
tARYCH
49
ARDY resolution transition setup time
tARYCHL
51
ARDY inactive holding time
tARYHDSH
951
ARDY High to DS High
1
tARYHDV
89
tARYLCL
52
1
ARDY assert to data valid
ARDY setup time
tARYLDSH
96
tAVBL
87
A address valid to WHB, WLB Low
ARDY Low to DS High
tAVCH
14
AD address valid to clock High
tAVLL
12
AD address valid to ALE Low
tAVRL
66
A address valid to RD Low
tAVWL
65
A address valid to WR Low
tAZRL
24
AD address float to RD active
tCH1CH2
45
CLKOUT rise time
tCHAV
68
CLKOUT High to A address valid
tCHCAS
404
Change in CAS delay
tCHCK
38
X1 High time
tCHCL
44
CLKOUT High time
tCHCSV
67
CLKOUT High to LCS/UCS valid
tCHCSX
18
MCSx/PCSx inactive delay
tCHCTV
22
Control active delay 2
tCHCV
64
Command lines valid delay (after float)
tCHCZ
63
Command lines float delay
tCHDX
8
Status hold time
tCHLH
9
ALE active delay
tCHLL
11
ALE inactive delay
tCHQS0V
55
Queue status 0 output delay
tCHQS1V
56
Queue status 1 output delay
tCHRAS
403
Change in RAS delay
tCHRFD
791
CLKOUT High to RFSH valid
tCHSV
3
Status active delay
tCICO
69
X1 to CLKOUT skew
tCKHL
39
X1 fall time
tCKIN
36
X1 period
tCKLH
40
X1 rise time
tCL2CL1
46
CLKOUT fall time
tCLARX
50
ARDY active hold time
tCLAV
5
AD address and BHE valid delay
tCLAX
6
Address hold
tCLAZ
15
AD address float delay
tCLCH
43
CLKOUT Low time
tCLCK
37
X1 Low time
tCLCL
42
CLKOUT period
tCLCLX
801
LCS inactive delay
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Table 9. Alphabetical Key to Switching Parameter Symbols (Continued)
Parameter
Symbol
No.
Description
tCLCSL
811
LCS active delay
tCLCSV
16
MCSx/PCSx active delay
tCLDOX
30
Data hold time
tCLDV
7
Data valid delay
tCLDX
2
Data in hold
tCLHAV
62
HLDA valid delay
tCLRF
821
CLKOUT High to RFSH invalid
tCLRH
27
RD inactive delay
tCLRL
25
RD active delay
tCLRO
61
Reset delay
tCLSH
4
Status and BHE inactive delay
tCLSRY
48
SRDY transition hold time
tCLTMV
54
Timer output delay
tCOLV
402
Column address valid delay
tCSHARYL
881
Chip select to ARDY Low
tCVCTV
20
Control active delay 1
tCVCTX
31
Control inactive delay
tCVDEX
21
DEN/DS inactive delay
tCXCSX
17
MCSx/PCSx hold from command inactive
tDSHDIR
921
DS High to data invalid—read
tDSHDIW
98
1
DS High to data invalid—write
tDSHDX
931
DS High to data bus turn-off time
tDSHLH
41
DS inactive to ALE inactive
tDSLDD
901
DS Low to data driven
tDSLDV
911
DS Low to data valid
tDVCL
1
tDVDSL
971
Data valid to DS Low
Data in setup
tDXDL
19
DEN/DS inactive to DT/R Low
tHVCL
58
HOLD setup
tINVCH
53
Peripheral setup time
tLCRF
861
LCS inactive to RFSH active delay
tLHAV
23
ALE High to address valid
tLHLL
10
ALE width
tLLAX
13
AD address hold from ALE inactive
tLRLL
841
LCS precharge pulse width
tRESIN
57
RES setup time
tRFCY
851
RFSH cycle time
tRHAV
29
RD inactive to AD address active
tRHDX
59
RD High to data hold on AD bus
tRHDZ
941
RD High to data bus turn-off time
tRHLH
28
RD inactive to ALE High
tRLRH
26
RD pulse width
tSRYCL
47
SRDY transition setup time
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Table 9. Alphabetical Key to Switching Parameter Symbols (Continued)
Parameter
Symbol
No.
Description
tWHDEX
35
WR inactive to DEN inactive
tWHDX
34
Data hold after WR
tWHLH
33
WR inactive to ALE High
tWLWH
32
WR pulse width
USB Timing (Clocks)
tUCHCK
3
USBX1 High time
tUCKHL
4
USBX1 fall time
tUCKIN
1
USBX1 period
tUCKLH
5
USBX1 rise time
tUCLCK
2
USBX1 Low time
USB Timing (Data/Jitter)
tF
2
Fall time
tJR1
3
Consecutive transition jitter
tJR2
4
Paired transition jitter
tR
1
Rise time
tCLEV
1
CLKOUT Low to SDEN valid
SSI
tCLSL
2
CLKOUT Low to SCLK Low
tDVSH
3
Data valid to SCLK High
tSHDX
4
SCLK High to data invalid
tSLDV
5
SCLK Low to data valid
Notes:
1. Specification defined but not in use at this time.
44
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Table 10.
Numerical Key to Switching Parameter Symbols
No.
Parameter
Symbol
Description
1
tDVCL
Data in setup
2
tCLDX
Data in hold
3
tCHSV
Status active delay
4
tCLSH
Status and BHE inactive delay
5
tCLAV
AD address and BHE valid delay
6
tCLAX
Address hold
7
tCLDV
Data valid delay
8
tCHDX
Status hold time
9
tCHLH
ALE active delay
10
tLHLL
ALE width
11
tCHLL
ALE inactive delay
12
tAVLL
AD address valid to ALE Low
13
tLLAX
AD address hold from ALE inactive
14
tAVCH
AD address valid to clock High
15
tCLAZ
AD address float delay
16
tCLCSV
MCSx/PCSx active delay
17
tCXCSX
MCSx/PCSx hold from command inactive
18
tCHCSX
MCSx/PCSx inactive delay
19
tDXDL
DEN/DS inactive to DT/R Low
20
tCVCTV
Control active delay 1
21
tCVDEX
DEN/DS inactive delay
22
tCHCTV
Control active delay 2
23
tLHAV
ALE High to address valid
24
tAZRL
AD address float to RD active
25
tCLRL
RD active delay
26
tRLRH
RD pulse width
27
tCLRH
RD inactive delay
28
tRHLH
RD inactive to ALE High
29
tRHAV
RD inactive to AD address active
30
tCLDOX
Data hold time
31
tCVCTX
Control inactive delay
32
tWLWH
WR pulse width
33
tWHLH
WR inactive to ALE High
34
tWHDX
Data hold after WR
35
tWHDEX
WR inactive to DEN inactive
36
tCKIN
X1 period
37
tCLCK
X1 Low time
38
tCHCK
X1 High time
39
tCKHL
X1 fall time
40
tCKLH
X1 rise time
41
tDSHLH
DS inactive to ALE inactive
42
tCLCL
CLKOUT period
43
tCLCH
CLKOUT Low time
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Table 10.
No.
Parameter
Symbol
44
tCHCL
CLKOUT High time
45
tCH1CH2
CLKOUT rise time
46
tCL2CL1
CLKOUT fall time
47
tSRYCL
SRDY transition setup time
48
tCLSRY
SRDY transition hold time
49
tARYCH
ARDY resolution transition setup time
50
tCLARX
ARDY active hold time
51
tARYCHL
ARDY inactive holding time
52
tARYLCL
ARDY setup time
53
tINVCH
Peripheral setup time
54
tCLTMV
Timer output delay
55
tCHQS0V
Queue status 0 output delay
56
tCHQS1V
Queue status 1 output delay
Description
57
tRESIN
RES setup time
58
tHVCL
HOLD setup
59
tRHDX
RD High to data hold on AD bus
61
tCLRO
Reset delay
62
tCLHAV
HLDA valid delay
63
tCHCZ
Command lines float delay
64
tCHCV
Command lines valid delay (after float)
65
tAVWL
A address valid to WR Low
66
tAVRL
A address valid to RD Low
67
tCHCSV
CLKOUT High to LCS/UCS valid
68
tCHAV
CLKOUT High to A address valid
69
tCICO
X1 to CLKOUT skew
1
79
tCHRFD
CLKOUT High to RFSH valid
801
tCLCLX
LCS inactive delay
1
tCLCSL
LCS active delay
1
81
tCLRF
CLKOUT High to RFSH invalid
1
84
tLRLL
LCS precharge pulse width
851
tRFCY
RFSH cycle time
1
tLCRF
LCS inactive to RFSH active delay
1
tAVBL
A address valid to WHB, WLB Low
1
88
tCSHARYL
Chip select to ARDY Low
891
tARYHDV
ARDY assert to data valid
1
tDSLDD
DS Low to data driven
1
tDSLDV
DS Low to data valid
1
92
tDSHDIR
DS High to data invalid—read
931
tDSHDX
DS High to data bus turn-off time
1
tRHDZ
RD High to data bus turn-off time
1
tARYHDSH
ARDY High to DS High
1
96
tARYLDSH
ARDY Low to DS High
971
tDVDSL
82
86
87
90
91
94
95
46
Numerical Key to Switching Parameter Symbols (Continued)
Data valid to DS Low
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Table 10.
Numerical Key to Switching Parameter Symbols (Continued)
No.
Parameter
Symbol
981
tDSHDIW
Description
DS High to data invalid—write
Column address valid delay
402
tCOLV
403
tCHRAS
Change in RAS delay
404
tCHCAS
Change in CAS delay
USB Timing (Clocks)
1
tUCKIN
USBX1 period
2
tUCLCK
USBX1 Low time
3
tUCHCK
USBX1 High time
4
tUCKHL
USBX1 fall time
5
tUCKLH
USBX1 rise time
USB Timing (Data/Jitter)
1
tR
Rise time
2
tF
Fall time
3
tJR1
Consecutive transition jitter
4
tJR2
Paired transition jitter
SSI
tCLEV
CLKOUT Low to SDEN valid
2
tCLSL
CLKOUT Low to SCLK Low
3
tDVSH
Data valid to SCLK High
4
tSHDX
SCLK High to data invalid
5
tSLDV
SCLK Low to data valid
1
Notes:
1. Specification defined but not in use at this time.
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Switching Characteristics over Commercial and Industrial Operating Ranges
In this section, the following timings and timing
waveforms are shown:
■ External ready (page 58)
■ Read (page 48)
■ System clocks (page 61)
■ Write (page 51)
■ USB clocks (page 62)
■ Software halt (page 54)
■ USB (page 63)
■ Peripheral (page 55)
■ SSI (page 64)
■ Reset (page 56)
■ DRAM (page 65)
■ Bus hold (page 60)
Table 11. Read Cycle Timing1
Preliminary
Parameter
No.
Symbol
25 MHz
Description
Min
50 MHz
(Commercial Only)
40 MHz
Max
Min
Max
Min
Unit
Max
General Timing Requirements
1
tDVCL
Data in setup
10
—
5
—
5
—
ns
2
tCLDX
Data in hold2
3
—
2
—
2
—
ns
General Timing Responses
3
tCHSV
Status active delay
0
20
0
12
0
10
ns
4
tCLSH
Status and BHE
inactive delay
0
20
0
12
0
10
ns
5
tCLAV
AD address and
BHE valid delay
0
20
0
12
0
10
ns
6
tCLAX
Address hold
0
—
0
—
0
—
ns
8
tCHDX
Status hold time
0
—
0
—
0
—
ns
9
tCHLH
ALE active delay
—
20
—
12
—
10
ns
10
tLHLL
ALE width
tCLCL–10=30
—
tCLCL–5=20
—
tCLCL–5=15
—
ns
11
tCHLL
ALE inactive delay
—
20
—
12
—
10
ns
12
tAVLL
AD address valid to
ALE Low3
0.5 • tCLCH
—
0.5 • tCLCH
—
0.5 • tCLCH
—
ns
13
tLLAX
AD address hold
from ALE inactive3
tCHCL
—
tCHCL
—
tCHCL
—
ns
14
tAVCH
AD address valid to
clock High
0
—
0
—
0
—
ns
15
tCLAZ
AD address float
delay
tCLAX=0
20
tCLAX=0
12
tCLAX=0
10
ns
16
tCLCSV
MCSx/PCSx active
delay
0
20
0
12
0
10
ns
17
tCXCSX
MCSx/PCSx hold
from command
inactive
tCLCH
—
tCLCH
—
tCLCH
—
ns
18
tCHCSX
MCSx/PCSx
inactive delay
0
20
0
12
0
10
ns
19
tDXDL
DEN/DS inactive to
DT/R Low3, 4
–1
—
–1
—
–1
—
ns
20
tCVCTV
Control active
delay 1
0
20
0
12
0
10
ns
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Read Cycle Timing1 (Continued)
Table 11.
Preliminary
Parameter
25 MHz
50 MHz
(Commercial Only)
40 MHz
Unit
No.
Symbol
Description
Min
Max
Min
Max
Min
Max
21
tCVDEX
DEN/DS inactive
delay4
0
20
0
12
0
10
ns
22
tCHCTV
Control active
delay 2
0
20
0
12
0
10
ns
23
tLHAV
ALE High to
address valid
15
—
7.5
—
5
—
ns
Read Cycle Timing Responses
24
tAZRL
AD address float to
RD active
0
—
0
—
0
—
ns
25
tCLRL
RD active delay
0
20
0
10
0
10
ns
26
tRLRH
RD pulse width
2tCLCL–15=65
—
2tCLCL–10=40
—
2tCLCL–10=30
—
ns
27
tCLRH
RD inactive delay
0
20
0
12
0
10
ns
28
tRHLH
RD inactive to ALE
High3
tCLCH–3
—
tCLCH–2
—
tCLCH–2
—
ns
29
tRHAV
RD inactive to AD
address active 3
tCLCL–10=30
—
tCLCL–5=20
—
tCLCL–5=15
—
ns
59
tRHDX
RD High to data
hold on AD Bus2
3
—
2
—
0
—
ns
66
tAVRL
A address valid to
RD Low
1.5tCLCL–15=45
—
1.5tCLCL–10=
27.5
—
1.5tCLCL–10=20
—
ns
67
tCHCSV
CLKOUT High to
LCS/UCS valid
0
20
0
10
0
10
ns
68
tCHAV
CLKOUT High to A
address valid
0
20
0
10
0
10
ns
Notes:
1. All timing parameters are measured at VCC/2 with 50-pF loading on CLKOUT unless otherwise noted. All output test conditions
are with the load values shown in Table 29, “Pin List Summary,” on page A-10.
2. If either specification 2 or specification 59 is met with respect to data hold time, then the device functions correctly.
3. Testing is performed with equal loading on referenced pins.
4. The timing of this signal is the same for a read cycle, whether it is configured to be DEN or DS.
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T4
T1
T2
T3
T4
1
14
2
CLKOUT
tw
66
68
A19–A0
6
3
8
S61
23
13
5
12
AD15–AD0
15
59
24
29
Addr.
Data
11
9
10
28
ALE
27
25
26
17
RD
5
4
BHE
67
LCS, UCS
16
18
MCS3–MCS0,
PCS7–PCS0
19
20
21
DEN, DS
22
22
DT/R
3
4
S2–S0
Notes:
1. S6 is not valid for the first fetch until the timing for parameter 3 (status active delay (t CHSV)) is met.
Figure 14. Read Cycle Waveforms
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Table 12.
Write Cycle Timing1
Preliminary
Parameter
No.
Symbol
25 MHz
Description
50 MHz
(Commercial Only)
40 MHz
Min
Max
Min
Max
Min
Max
Unit
General Timing Responses
3
tCHSV
Status active delay
0
20
0
12
0
10
ns
4
tCLSH
Status and BHE
inactive delay
0
20
0
12
0
10
ns
5
tCLAV
AD address and
BHE valid delay
0
20
0
12
0
10
ns
6
tCLAX
Address hold
0
—
0
—
0
—
ns
7
tCLDV
Data valid delay
0
20
0
12
0
10
8
tCHDX
Status hold time
0
—
0
—
0
9
tCHLH
ALE active delay
—
20
—
12
—
10
ns
10
tLHLL
ALE width
tCLCL – 10 = 30
—
tCLCL – 5 = 20
—
tCLCL – 5 = 15
—
ns
11
tCHLL
ALE inactive delay
—
20
—
12
—
10
ns
12
tAVLL
AD address valid
to ALE Low2
0.5 • tCLCH
—
0.5 • tCLCH
—
0.5 • tCLCH
—
ns
13
tLLAX
AD address hold
from ALE inactive
tCHCL
—
tCHCL
—
tCHCL
—
ns
14
tAVCH
AD address valid
to clock High
0
—
0
—
0
—
ns
16
tCLCSV
MCSx/PCSx active
delay
0
20
0
12
0
10
ns
17
tCXCSX
MCSx/PCSx hold
from command
inactive
tCLCH
—
tCLCH
—
tCLCH
—
ns
18
tCHCSX
MCSx/PCSx
inactive delay
0
20
0
12
0
10
ns
19
tDXDL
DEN inactive to
DT/R2, 3
–1
—
–1
—
–1
—
ns
20
tCVCTV
Control active
delay 13,4
0
20
0
12
0
10
ns
21
tCVDEX
DS inactive
delay3,4
0
20
0
12
0
10
ns
23
tLHAV
ALE High to
address valid
15
—
7.5
—
5
—
ns
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ns
ns
51
Write Cycle Timing1 (Continued)
Table 12.
Preliminary
Parameter
No.
Symbol
25 MHz
Description
50 MHz
(Commercial Only)
40 MHz
Min
Max
Min
Max
Min
Max
Unit
Write Cycle Timing Responses
30
tCLDOX
Data hold time
0
—
0
—
0
—
ns
31
tCVCTX
Control inactive
delay3,4
0
20
0
12
0
10
ns
32
tWLWH
WR pulse width
2tCLCL – 10 = 70
—
2tCLCL – 10 = 40
—
2tCLCL – 10 = 30
—
ns
33
tWHLH
WR inactive to ALE
High2
tCLCH – 2
—
tCLCH – 2
—
tCLCH – 2
—
ns
34
tWHDX
Data hold after WR2
tCLCL – 10 = 30
—
tCLCL – 10 = 15
—
tCLCL – 10 = 10
—
ns
35
tWHDEX
WR inactive to
DEN inactive2,3
tCLCH – 3
—
tCLCH
—
tCLCH
—
ns
65
tAVWL
A address valid to
WR Low
tCLCL + tCHCL –3
—
tCLCL + tCHCL –
1.25
—
tCLCL + tCHCL –
1.25
—
ns
67
tCHCSV
CLKOUT High to
LCS/UCS valid
0
20
0
10
0
10
ns
68
tCHAV
CLKOUT High to A
address valid
0
20
0
10
0
10
ns
87
tAVBL
A address valid to
WHB, WLB Low
tCHCL – 3
20
tCHCL – 1.25
12
tCHCL – 1.25
10
ns
Notes:
1. All timing parameters are measured at VCC/2 with 50-pF loading on CLKOUT unless otherwise noted. All output test conditions
are with the load values shown in Table 29, “Pin List Summary,” on page A-10.
2. Testing is performed with equal loading on referenced pins.
3. The timing of this signal is different during a write cycle depending on whether it is configured to be DEN or DS.
4. This parameter applies to the DEN, DS, WR, WHB, and WLB signals.
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T4
T1
T2
T3
T4
14
CLKOUT
tw
87
68
65
A19–A0
6
3
S61
23
12
8
7
34
13
5
AD15—AD0
Addr.
30
Data
11
10
9
33
ALE
31
20
35
17
32
WR
20
31
5
4
WHB, WLB
BHE
67
LCS, UCS
16
18
MCS3–MCS0,
PCS7–PCS0
31
20
19
DEN
20
21
DS
20
DT/R
31
4
3
S2–S0
Notes:
1. S6 is not valid for the first fetch until the timing for parameter 3 (status active delay (t CHSV)) is met.
Figure 15.
Write Cycle Waveforms
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Table 13. Software Halt Cycle Timing1
Preliminary
Parameter
No.
25 MHz
Symbol Description
50 MHz
(Commercial Only)
40 MHz
Unit
Min
Max
Min
Max
Min
Max
3
tCHSV
Status active delay
0
20
0
12
0
10
ns
4
tCLSH
Status inactive
delay
0
20
0
12
0
10
ns
5
tCLAV
AD address invalid
delay
0
20
0
12
0
10
ns
9
tCHLH
ALE active delay
—
20
—
12
—
10
ns
10
tLHLL
ALE width
tCLCL – 10 = 30
—
tCLCL – 5 = 20
—
tCLCL – 5 = 15
—
ns
11
tCHLL
ALE inactive delay
—
20
—
12
—
10
19
tDXDL
DEN inactive to
DT/R Low2
–1
—
–1
—
–1
22
tCHCTV
Control active
delay 23
0
20
0
12
0
10
ns
68
tCHAV
CLKOUT High to A
address invalid
0
20
0
12
0
10
ns
ns
ns
Notes:
1. All timing parameters are measured at VCC/2 with 50-pF loading on CLKOUT unless otherwise noted. All output test conditions
are with the load values shown in Table 29, “Pin List Summary,” on page A-10.
2. Testing is performed with equal loading on referenced pins.
3. This parameter applies to the DEN/DS signal.
T4
T1
T2
TI
CLKOUT
68
A19–A0
Invalid Address
5
S6, AD15–AD0
Invalid Address
11
10
9
ALE
22
19
DEN, DS
DT/R
4
3
S2–S0
Figure 16.
54
Software Halt Cycle Waveforms
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TI
Table 14. Peripheral Timing1,
2
Preliminary
Parameter
25 MHz
Description
50 MHz
(Commercial Only)
40 MHz
Unit
No.
Symbol
Min
Max
Min
Max
Min
Max
53
tINVCH
Peripheral setup time
10
—
5
—
5
—
ns
54
tCLTMV
Timer output delay
—
25
—
15
—
12
ns
55
tCHQS0V
Queue status 0 output delay
—
25
—
15
—
12
ns
56
tCHQS1V
Queue status 1 output delay
—
25
—
15
—
12
ns
Notes:
1. All timing parameters are measured at VCC/2 with 50-pF loading on CLKOUT unless otherwise noted. All output test conditions
are with the load values shown in Table 29, “Pin List Summary,” on page A-10.
2. PIO outputs change anywhere from the beginning of T3 to the first half of T4 of the bus cycle in which the PIO data register is
written.
56
53
54
55
CLKOUT
INT8–INT0, NMI, TMRINx
DRQ0, DRQ1
TMROUT
QS0
QS1
Figure 17. Peripheral Waveforms
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55
Table 15. Reset Timing1
Preliminary
Parameter
25 MHz
Description
50 MHz
(Commercial Only)
40 MHz
Unit
No.
Symbol
Min
Max
Min
Max
Min
Max
57
tRESIN
RES setup time
10
—
5
—
5
—
ns
61
tCLRO
Reset delay
—
18
—
15
—
12
ns
Notes:
1. All timing parameters are measured at VCC/2 with 50-pF loading on CLKOUT unless otherwise noted. All output test conditions
are with the load values shown in Table 29, “Pin List Summary,” on page A-10.
57
RES
CLKOUT
61
RESOUT
Notes:
1. RES must be held Low for 1 ms during power-up to ensure proper device initialization.
2. Diagram is shown for the system PLL in its 2x mode of operation.
3. Diagram assumes that VCC is stable (i.e., 3.3 V ± 0.3 V) during the 1-ms RES active time.
Figure 18. Reset Waveforms
56
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RES
CLKOUT
All Pinstrap
Pins1,2
AD15–AD01
All Other
Outputs
RESOUT
Notes:
1. The pinstraps and AD bus are sampled during the assertion of RESOUT for system configuration purposes.
2. See Appendix A, “Reset Configuration Pins (Pinstraps),” on page A-8 for a list of all the pinstraps.
Figure 19.
Signals Related to Reset (System PLL in 1x or 2x Mode)
RES
CLKOUT
All Pinstrap
Pins1,2
AD15–AD01
All Other
Outputs
RESOUT
Notes:
1. The pinstraps and AD bus are sampled during the assertion of RESOUT for system configuration purposes.
2. See Appendix A, “Reset Configuration Pins (Pinstraps),” on page A-8 for a list of all the pinstraps.
Figure 20.
Signals Related to Reset (System PLL in 4x Mode)
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57
Table 16. External Ready Cycle Timing1
Preliminary
Parameter
No.
Symbol
25 MHz
Description
40 MHz
50 MHz
(Commercial Only)
Unit
Min
Max
Min
Max
Min
Max
10
—
5
—
5
—
ns
3
—
2
—
2
—
ns
Ready Timing Requirements
47
48
tSRYCL
tCLSRY
SRDY transition setup time2
2
SRDY transition hold time
3
49
tARYCH
ARDY resolution transition setup time
10
—
5
—
5
—
ns
50
tCLARX
ARDY active hold time2
4
—
3
—
3
—
ns
51
tARYCHL
ARDY inactive holding time
10
—
5
—
5
—
ns
15
—
5
—
5
—
ns
52
tARYLCL
ARDY setup time
2
Notes:
1. All timing parameters are measured at VCC/2 with 50-pF loading on CLKOUT unless otherwise noted. All output test conditions
are with the load values shown in Table 29, “Pin List Summary,” on page A-10.
2. This timing must be met to guarantee proper operation.
3. This timing must be met to guarantee recognition at the clock edge.
Case 11
Tw
Tw
Tw
T4
21
T3
Tw
Tw
T4
Case 31
T2
T3
Tw
T4
42
T1
T2
T3
Case 51
T1
T2
T3
Tw
T4
Case
Case
CLKOUT
47
Note 2
SRDY Note 1
48
Notes:
1. Normally not ready system
2. Normally ready system
Figure 21. Synchronous Ready Waveforms
58
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T4
Case 11
Tw
Tw
Tw
T4
Case 21
T3
Tw
Tw
T4
1
T2
T3
Tw
T4
Case 42
T1
T2
T3
Tw
Case 51
T1
T2
T3
T4
Case 3
T4
50
CLKOUT
49
ARDY1
(Normally Not-Ready System)
ARDY2
(Normally Ready System)
49
51
50
52
Notes:
1. In a normally not ready system, wait states are added after T3 until tARYCH (49) and tCLARX (50) are met.
2. In a normally ready system, a wait state is added if tARYCH (49) and tARYCHL (51) during T2 or tARYLCL (52)
and tCLARX (50) during T3 are met.
Figure 22.
Asynchronous Ready Waveforms
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59
Table 17. Bus Hold Timing1
Preliminary
Parameter
No.
5
15
18
58
62
63
64
Symbol
tCLAV
tCLAZ
tCHCSX
tHVCL
tCLHAV
tCHCZ
tCHCV
25 MHz
Description
AD address valid delay
AD address float delay
MCSx/PCSx inactive delay
HOLD setup2
HLDA valid delay
Command lines float delay
Command lines valid delay (after float)
Min
0
0
0
10
0
—
—
50 MHz
(Commercial Only)
Min
Max
0
10
0
10
0
10
5
—
0
10
—
10
—
10
40 MHz
Max
20
20
20
—
20
20
25
Min
0
0
0
5
0
—
—
Max
12
12
12
—
12
12
12
Unit
ns
ns
ns
ns
ns
ns
ns
Notes:
1. All timing parameters are measured at VCC/2 with 50-pF loading on CLKOUT unless otherwise noted. All output test conditions
are with the load values shown in Table 29, “Pin List Summary,” on page A-10.
2. This timing must be met to guarantee recognition at the next clock.
Ti
T4
Case 1
Case 2
Ti
Ti
Ti
Ti
CLKOUT
58
HOLD
62
HLDA
15
AD15–AD0, DEN
18
MCS3–MCS0, PCS7–PCS0
A19–A0, S6, RD, WR,
BHE, DT/R, S2–S0, WHB,
WLB, UCS, LCS, ALE
63
Figure 23. Entering Bus Hold Waveforms
Case 1
Case 2
Ti
Ti
Ti
Ti
Ti
T4
T1
T1
CLKOUT
58
HOLD
62
HLDA
5
AD15–AD0, DEN
MCS3–MCS0, PCS7–PCS0
A19–A0, S6, RD, WR,
BHE, DT/R, S2–S0, WHB,
WLB, UCS, LCS, ALE
64
Figure 24.
60
Exiting Bus Hold Waveforms
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Table 18.
System Clocks Timing1
Preliminary
Parameter
No.
Symbol
25 MHz
Description
Min
50 MHz
(Commercial Only)
40 MHz
Max
Unit
Min
Max
Min
Max
100
125
80
125
ns
CLKIN Requirements for 4x PLL Mode
36
tCKIN
X1 period2
37
tCLCK
X1 Low time (1.5 V)
45
—
35
—
ns
Not Supported
38
tCHCK
X1 High time (1.5 V)
45
—
35
—
ns
39
tCKHL
X1 fall time
(3.5 to 1.0 V)
—
5
—
5
ns
40
tCKLH
X1 rise time
(1.0 to 3.5 V)
—
5
—
5
ns
CLKIN Requirements for 2x PLL Mode
36
tCKIN
X1 period2
80
125
50
125
40
125
ns
37
tCLCK
X1 Low time (1.5 V)
35
—
20
—
15
—
ns
38
tCHCK
X1 High time (1.5 V)
35
—
20
—
15
—
ns
39
tCKHL
X1 fall time
(3.5 to 1.0 V)
—
5
—
5
—
5
ns
40
tCKLH
X1 rise time
(1.0 to 3.5 V)
—
5
—
5
—
5
ns
CLKIN Requirements for 1x PLL Mode
36
tCKIN
X1 period2
40
60
25
60
37
tCLCK
X1 Low time (1.5 V)
15
—
7.5
—
ns
38
tCHCK
X1 High time (1.5 V)
15
—
7.5
—
ns
39
tCKHL
X1 fall time
(3.5 to 1.0 V)
—
5
—
5
ns
40
tCKLH
X1 rise time
(1.0 to 3.5 V)
—
5
—
5
ns
40
—
25
—
20
—
ns
Not Supported
ns
CLKOUT Timing3
42
tCLCL
CLKOUT period
43
tCLCH
CLKOUT Low time
(CL = 50 pF)
0.5tCLCL–2 =18
—
0.5tCLCL–1.25
=11.25
—
0.5tCLCL–1 = 9
—
ns
44
tCHCL
CLKOUT High time
(CL = 50 pF)
0.5tCLCL–2 =18
—
0.5tCLCL–1.25
=11.25
—
0.5tCLCL–1 = 9
—
ns
45
tCH1CH2
CLKOUT rise time
(1.0 to 3.5 V)
—
3
—
3
—
3
ns
46
tCL2CL1
CLKOUT fall time
(3.5 to 1.0 V)
—
3
—
3
—
3
ns
69
tCICO
X1 to CLKOUT skew
—
10
—
10
—
10
ns
Notes:
1. All timing parameters are measured at VCC/2 with 50-pF loading on CLKOUT unless otherwise noted. All output test conditions
are with the load values shown in Table 29, “Pin List Summary,” on page A-10.
2. Testing is performed with equal loading on referenced pins.
3. The PLL requires a maximum of 1 ms to achieve lock after all other operating conditions (VCC) are stable, which is normally
achieved by holding RES active for at least 1 ms.
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X2
36
37
38
X1
39
40
46
45
CLKOUT
42
69
44
43
Figure 25. System Clocks Waveforms—Active Mode (PLL 1x Mode)
Table 19.
USB Clocks Timing1
Preliminary
Parameter
No.
Symbol
48 MHz
Description
Unit
Min
Max
CLKIN Requirements for 4x PLL Mode
1
tUCKIN
USBX1 period
80
85
ns
2
tUCLCK
USBX1 Low time (1.5 V)
35
—
ns
3
tUCHCK
USBX1 High time (1.5 V)
35
—
ns
4
tUCKHL
USBX1 fall time (3.5 to 1.0 V)
—
5
ns
5
tUCKLH
USBX1 rise time (1.0 to 3.5 V)
—
5
ns
CLKIN Requirements for 2x PLL Mode
1
tUCKIN
USBX1 period
40
42
ns
2
tUCLCK
USBX1 Low time (1.5 V)
15
—
ns
3
tUCHCK
USBX1 High time (1.5 V)
15
—
ns
4
tUCKHL
USBX1 fall time (3.5 to 1.0 V)
—
5
ns
5
tUCKLH
USBX1 rise time (1.0 to 3.5 V)
—
5
ns
Notes:
1. All timing parameters are measured at VCC/2 with 50-pF loading on CLKOUT unless otherwise noted. All output test conditions
are with the load values shown in Table 29, “Pin List Summary,” on page A-10.
USBX2
1
USBX1
3
5
4
Figure 26.
62
2
USB Clocks Waveforms
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Table 20. USB Timing1, 2
Preliminary
Parameter
No.
Symbol
48 MHz
Description
Min
Unit
Max
1
tR
Rise time (Cl = 50 pF)
4 ns
20 ns
ns
2
tF
Fall time (Cl = 50 pF)
4 ns
20 ns
ns
3
tJR1
Consecutive transition jitter (measured at crossover point)
–18.5 ns
18.5 ns
ns
4
tJR2
Paired transition jitter (measured at crossover point)
–9 ns
9 ns
ns
Notes:
1. All timing parameters are measured at VCC/2 with 50-pF loading on CLKOUT unless otherwise noted. All output test conditions are
with the load values shown in Table 29, “Pin List Summary,” on page A-10.
2. Parameters 3 (tJR1) and 4 (tJR2) show jitter for the receiver, not the transmitter, See the USB version 1.0 specification for more details.
Fall Time
Rise Time
90%
Differential
Data Lines (D+/D–)
10%
10%
1
2
Figure 27. USB Data Signal Rise and Fall Times
CLK
3
4
D+/D–
Consecutive Transition
Paired Transition
Figure 28. USB Receiver Jitter Tolerance
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Table 21.
SSI Timing1
Preliminary
Parameter
25 MHz
Description
40 MHz
50 MHz
(Commercial Only)
Unit
No.
Symbol
Min
Max
Min
Max
Min
Max
1
tCLEV
CLKOUT Low to SDEN valid
0
20
0
12
0
10
ns
2
tCLSL
CLKOUT Low to SCLK Low
0
20
0
15
0
12
ns
3
tDVSH
Data valid to SCLK High
10
—
5
—
5
—
ns
4
tSHDX
SCLK High to data invalid
3
—
2
—
2
—
ns
5
tSLDV
SCLK Low to data valid
—
20
—
12
—
10
ns
Notes:
1. All timing parameters are measured at VCC/2 with 50-pF loading on CLKOUT unless otherwise noted. All output test conditions
are with the load values shown in Table 29, “Pin List Summary,” on page A-10.
CLKOUT
1
SDEN
2
2
3
SCLK
4
SDATA (RX)
5
SDATA (TX)
Notes:
1. SDEN is configured to be active High.
2. SCLK is configured to be CLKOUT/2.
3. Waveforms are shown for “normal” clock mode (i.e., transmit on negative edge of SCLK and receive on
positive edge of SCLK).
Figure 29.
64
SSI Waveforms
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DRAM Timing1
Table 22.
Preliminary
Parameter
25 MHz
50 MHz
(Commercial Only)
40 MHz
Unit
No.
Symbol
Description
Min
Max
Min
Max
Min
Max
1
tDVCL
Data in setup
10
—
5
—
5
—
ns
2
tCLDX
Data in hold
3
—
2
—
2
—
ns
5
tCLAV
AD address valid delay
0
20
0
12
0
10
ns
7
tCLDV
Data valid delay
0
20
0
12
0
10
ns
15
tCLAZ
AD address float delay
0
20
0
12
0
10
ns
20
tCVCTV
Control active delay 1
0
20
0
12
0
10
ns
25
tCLRL
RD active delay
0
20
0
12
0
10
ns
27
tCLRH
RD inactive delay
0
20
0
12
0
10
ns
30
tCLDOX
Data hold time
0
—
0
—
0
—
ns
31
tCVCTX
Control inactive delay
0
20
0
12
0
10
ns
68
tCHAV
CLKOUT High to A address valid
0
20
0
12
0
10
ns
402
tCOLV
Column address valid delay
0
20
0
12
0
10
ns
403
tCHRAS
Change in RAS delay
3
20
3
12
3
10
ns
404
tCHCAS
Change in CAS delay
3
20
3
12
3
10
ns
Notes:
1. All timing parameters are measured at VCC/2 with 50-pF loading on CLKOUT unless otherwise noted. All output test conditions
are with the load values shown in Table 29, “Pin List Summary,” on page A-10.
T4
T1
T2
T3
T4
1
2
CLKOUT
5
AD15–AD0
15
Addr.
Data
68
A17, A15, A13, A11,
A9, A7, A5, A3, A1
402
Row
Column
403
403
RAS0, RAS1
404
404
CAS0, CAS1
25
27
RD
Figure 30.
DRAM Read Cycle without Wait States Waveform
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T4
T1
T2
TW
T3
T4
1
2
CLKOUT
5
15
AD15–AD0
Addr.
DATA
68
A17, A15, A13, A11,
A9, A7, A5, A3, A1
402
Row
Column
403
403
RAS0, RAS1
404
404
CAS0, RAS1
25
27
RD
Figure 31.
DRAM Read Cycle with Wait States Waveform
T4
T1
T2
T3
T4
CLKOUT
5
7
AD15–AD0
Addr.
Data
402
68
A17, A15, A13, A11,
A9, A7, A5, A3, A1
30
Row
Column
403
403
RAS0, RAS1
404
404
CAS0, CAS1
20
WR
Figure 32. DRAM Write Cycle without Wait States Waveform
66
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31
T4
T1
T2
TW
T3
T4
CLKOUT
5
7
AD15–AD0
30
Data
Addr.
68
A17, A15, A13, A11,
A9, A7, A5, A3, A1
402
Row
Column
403
403
RAS0, RAS1
404
404
CAS0, CAS1
20
31
WR
Figure 33. DRAM Write Cycle with Wait States Waveform
T4
T1
T2
TW1
TW2
TW3
T3
T4
CLKOUT
5
AD15–AD0
15
Addr.
68
A17, A15, A13, A11,
A9, A7, A5, A3, A1
402
Row (Invalid)
Column (Invalid)
403
403
RAS0, RAS1
404
404
CAS0, CAS1
25
27
RD
Figure 34.
DRAM Refresh Cycle Waveform
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68
Am186™CU USB Microcontroller Data Sheet
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APPENDIX A—PIN TABLES
This appendix contains pin tables for the Am186CU
USB microcontroller. Several different tables are
included with the following characteristics:
■ Power-on reset (POR) pin defaults including pin
numbers and multiplexed functions—Table 23 on
page A-2.
■ Multiplexed signal tradeoffs—Table 24 on page A-5.
■ Programmable I/O pins ordered by PIO pin number
and multiplexed signal name, r es pectively,
including pin numbers, multiplexed functions, and
pin configurations following system reset—Table 25
on page A-6 and Table 26 on page A-7.
■ Pinstraps and
page A-8.
pinstrap
options—Table 27
on
For pin tables showing pins sorted by pin number and
signal name, respectively, see Table 1, “PQFP Pin
Assignments—Sorted by Pin Number” on page 10 and
Table 2, “PQFP Pin Assignments—Sorted by Signal
Name” on page 11.
For s ign al de sc r ipti ons, se e Tabl e 4, “ Si gna l
Descriptions” on page 13.
In all tables the brackets, [ ], indicate alternate,
multiplexed functions, and braces, { }, indicate reset
configuration pins (pinstraps). The line over a pin name
indicates an active Low. The word pin refers to the
physical wire; the word signal refers to the electrical
signal that flows through it.
■ Pin and signal summary showing signal name and
alternate function, pin number, I/O type, maximum
load values, POR default function, reset state, POR
default operation, hold state, and voltage column—
Table 29 on page A-10.
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A-1
Table 23.
POR Default
Power-On Reset (POR) Pin Defaults1
Pin
Number
Multiplexed
Signal
Multiplexed
Signal
Multiplexed
Signal
PIO
Pinstrap
30
31
32
36
37
42
43
44
45
49
50
64
65
69
70
84
85
88
89
90
28
34
38
46
51
66
86
92
29
35
39
47
52
67
87
93
19
14
20
94
18
105
17
98
99
97
57
56
55
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PIO33
PIO8
PIO34
—
PIO30
—
PIO29
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
{ADEN}
—
—
—
—
—
{CLKSEL1}
—
{USBXCVR}
—
—
Bus Interface Unit
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
ALE
ARDY
BHE
BSIZE8
DEN
DRQ1
DT/R
HLDA
HOLD
RD
S0
S1
S2
A-2
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Table 23. Power-On Reset (POR) Pin Defaults1 (Continued)
POR Default
Pin
Number
54
15
95
96
16
S6
SRDY
WHB
WLB
WR
Chip Selects
LCS
131
127
MCS1
MCS2
128
PCS0
5
6
PCS1
PCS2
7
PCS3
8
132
UCS
Reset/Clocks
CLKOUT
60
RES
114
RESOUT
58
USBX1
75
USBX2
76
X1
73
X2
74
Interrupts
INT0
107
INT1
109
INT2
110
INT3
111
INT4
112
INT5
113
NMI
115
High-Speed UART
TXD_HU
26
Debug Support
QS0
62
QS1
63
Universal Serial Bus
USBD+
81
USBD80
PIOs
PIO0
144
PIO1
143
PIO2
10
PIO3
9
PIO4
126
PIO5
129
PIO6
147
PIO7
146
PIO9
124
PIO10
2
PIO11
3
Multiplexed
Signal
—
—
—
—
—
Multiplexed
Signal
—
—
—
—
—
Multiplexed
Signal
—
—
—
—
—
PIO
Pinstrap
—
PIO35
—
—
PIO15
RAS0
CAS1
CAS0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PIO13
PIO14
—
—
—
—
—
—
—
—
—
—
—
—
{USBSEL1}
{USBSEL2}
—
—
{ONCE}
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
UDPLS
UDMNS
—
—
—
—
—
—
—
—
TMRIN1
TMROUT1
PCS5
PCS4
MCS0
MCS3
INT8
INT7
DRQ0
SDEN
SCLK
—
—
—
—
—
RAS1
PWD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
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—
—
—
{CLKSEL2}
{UCSX8}
—
—
—
—
—
—
A-3
Table 23. Power-On Reset (POR) Pin Defaults1 (Continued)
POR Default
PIO12
PIO16
PIO17
PIO18
PIO19
PIO20
PIO21
PIO22
PIO23
PIO24
PIO25
PIO26
PIO27
PIO28
PIO31
PIO32
PIO36
PIO37
PIO38
PIO39
PIO40
PIO41
PIO42
PIO43
PIO44
PIO45
PIO46
PIO47
Reserved
RSVD_104
RSVD_103
RSVD_102
RSVD_101
RSVD_119
RSVD_118
RSVD_117
RSVD_116
Pin
Number
4
25
123
122
145
159
22
150
149
157
156
158
142
141
13
11
138
139
137
136
135
134
153
154
152
151
24
23
Multiplexed
Signal
SDATA
RXD_HU
—
—
INT6
TXD_U
UCLK
—
—
CTS_U
RTR_U
RXD_U
TMRIN0
TMROUT0
PCS7
PCS6
—
—
—
—
—
—
—
—
—
—
CTS_HU
RTR_HU
Multiplexed
Signal
—
—
—
—
—
—
USBSOF
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Multiplexed
Signal
—
—
—
—
—
—
USBSCI
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
104
103
102
101
119
118
117
116
UXVRCV
UXVOE
UTXDMNS
UTXDPLS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PIO
Notes:
1. For default reset functions and pin states refer to Table 29, “Pin List Summary,” on page A-10.
A-4
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Pinstrap
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Table 24.
DESIRED FUNCTION
Interface
Multiplexed Signal Trade-Offs
LOST FUNCTION
Name
Pin
Interface
DRAM
Name
Interface
Name
Interface
Name
Interface Name
Memory
LCS
131
RAS0
—
—
—
—
MCS1
127
CAS1
—
—
—
—
MCS2
128
CAS0
—
—
—
—
—
MCS3
129
RAS1
—
—
—
—
PIO5
CAS0
128
MCS2
—
—
—
—
—
—
CAS1
127
MCS1
—
—
—
—
—
—
RAS0
131
LCS
—
—
—
—
—
—
RAS1
129
MCS3
—
—
—
—
—
PIO5
Bus
Interface
DEN
18
—
—
—
—
—
PIO30
18
Bus
Interface
DS
DS
DEN
—
—
—
—
—
PIO30
Clocks
UCLK
22
Clocks
USBSOF
Clocks
USBSCI
—
—
PIO
—
PIO21
—
PIO21
SRAM
DRAM
SRAM
PIO
—
—
Miscellaneous
USBSOF
22
UCLK
USBSCI
—
USBSCI
22
UCLK
USBSOF
—
PIO0
144
TMRIN1
—
—
PIO1
143
TMROUT1
—
—
PIO2
10
PCS5
—
—
PIO3
9
PCS4
—
—
PIO4
126
MCS0
—
—
PIO5
129
MCS3
RAS1
—
PIO6
147
INT8
PWD
—
PIO7
146
INT7
—
—
PIO21
PIOs
PIO8
14
ARDY
—
—
PIO9
124
DRQ0
—
—
PIO10
2
SDEN
—
—
PIO11
3
SCLK
—
—
PIO12
4
SDATA
—
—
PIO13
5
PCS0
—
—
PIO14
6
PCS1
—
—
PIO15
16
WR
—
—
PIO16
25
RXD_HU
—
—
PIO19
145
INT6
—
—
PIO20
159
TXD_U
—
—
PIO21
22
UCLK
USBSOF
USBSCI
PIO24
157
CTS_U
—
—
PIO25
156
RTR_U
—
—
PIO26
158
RXD_U
—
—
PIO27
142
TMRIN0
—
—
PIO28
141
TMROUT0
—
—
PIO29
17
DT/R
—
—
PIO30
18
DEN
DS
—
PIO31
13
PCS7
—
—
PIO32
11
PCS6
—
—
PIO33
19
ALE
—
—
PIO34
20
BHE
—
—
PIO35
15
SRDY
—
—
PIO46
24
CTS_HU
—
—
PIO47
23
RTR_HU
—
—
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A-5
Table 25.
PIO No.
Pin No.
PIOs Sorted by PIO Number
Multiplexed Signal
Multiplexed Signal
Multiplexed Signal
Pin Configuration Following
System Reset1
PIO0
144
TMRIN1
—
—
Input with pullup
PIO1
143
TMROUT1
—
—
Input with pulldown
PIO2
10
PCS5
—
—
Input with pullup
PIO3
9
PCS4
—
—
Input with pullup
PIO4
126
MCS0
—
—
Input with pullup
PIO5
129
MCS3
RAS1
—
Input with pullup
PIO6
147
INT8
PWD
—
Input with pullup
PIO7
146
INT7
—
—
Input with pullup
PIO8
14
ARDY
—
—
Alternate operation2
PIO9
124
DRQ0
—
—
Input with pulldown
PIO10
2
SDEN
—
—
Input with pulldown
PIO11
3
SCLK
—
—
Input with pullup
PIO12
4
SDATA
—
—
Input with pullup
PIO13
5
PCS0
—
—
Alternate operation2
PIO14
6
PCS1
—
—
Alternate operation2
PIO15
16
WR
—
—
Alternate operation2
PIO16
25
RXD_HU
—
—
Input with pullup
PIO17
123
—
—
—
Input with pullup
PIO18
122
—
—
—
Input with pullup
PIO19
145
INT6
—
—
Input with pullup
PIO20
159
TXD_U
—
—
Input with pullup
PIO21
22
UCLK
USBSOF
PIO22
150
—
—
USBSCI
—
Input with pulldown
PIO23
149
—
—
—
Input with pulldown
PIO24
157
CTS_U
—
—
Input with pullup
PIO25
156
RTR_U
—
—
Input with pullup
PIO26
158
RXD_U
—
—
Input with pullup
PIO27
142
TMRIN0
—
—
Input with pullup
PIO28
141
TMROUT0
—
—
Input with pulldown
PIO29
17
DT/R
—
—
Alternate operation2
PIO30
18
DEN
DS
—
Alternate operation2
PIO31
13
PCS7
—
—
Input with pullup
PIO32
11
PCS6
—
—
Input with pullup
PIO33
19
ALE
—
—
Alternate operation3
PIO34
20
BHE
—
—
Alternate operation2
PIO35
15
SRDY
—
—
Alternate operation2
PIO36
138
—
—
—
Input with pullup
PIO37
139
—
—
—
Input with pullup
PIO38
137
—
—
—
Input with pullup
PIO39
136
—
—
—
Input with pullup
PIO40
135
—
—
—
Input with pullup
PIO41
134
—
—
—
Input with pullup
PIO42
153
—
—
—
Input with pulldown
PIO43
154
—
—
—
Input with pulldown
PIO44
152
—
—
—
Input with pullup
PIO45
151
—
—
—
Input with pullup
PIO46
24
CTS_HU
—
—
Input with pullup
PIO47
23
RTR_HU
—
—
Input with pullup
Input with pullup
Notes:
1. System reset is defined as a power-on reset (i.e., the RES input pin transitioning from its Low to High state) or a reset due to
a watchdog timer timeout.
2. When used as a PIO, input with pullup option available.
3. When used as a PIO, input with a pulldown option available.
A-6
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Table 26.
Signal
PIO No.
Pin No.
PIOs Sorted by Signal Name
Multiplexed Signal
Multiplexed Signal
Pin Configuration Following
System Reset1
ALE
PIO33
19
—
—
Alternate operation2
ARDY
PIO8
14
—
—
Alternate operation3
BHE
PIO34
20
—
—
CTS_HU
CTS_U
DEN
PIO46
PIO24
PIO30
24
157
18
—
—
DS
—
—
—
Alternate operation3
Input with pullup
Input with pullup
DRQ0
DT/R
PIO9
PIO29
124
17
—
—
—
—
INT6
INT7
INT8
MCS0
MCS3
PCS0
PIO19
PIO7
PIO6
PIO4
PIO5
PIO13
145
146
147
126
129
5
—
—
PWD
—
RAS1
—
—
—
—
—
—
—
PCS1
PIO14
6
—
—
PCS4
PCS5
PCS6
PCS7
PIO17
PIO18
PIO22
PIO23
PIO36
PIO37
PIO38
PIO39
PIO40
PIO41
PIO42
PIO43
PIO44
PIO45
RTR_HU
RTR_U
RXD_HU
RXD_U
SCLK
SDATA
SDEN
SRDY
PIO3
PIO2
PIO32
PIO31
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PIO47
PIO25
PIO16
PIO26
PIO11
PIO12
PIO10
PIO35
9
10
11
13
123
122
150
149
138
139
137
136
135
134
153
154
152
151
23
156
25
158
3
4
2
15
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TMRIN0
TMRIN1
TMROUT0
TMROUT1
TXD_U
UCLK
WR
PIO27
PIO0
PIO28
PIO1
PIO20
PIO21
PIO15
142
144
141
143
159
22
16
—
—
—
—
—
USBSOF
—
—
—
—
USBSCI
—
Alternate operation3
Input with pulldown
Alternate operation3
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Alternate operation3
Alternate operation3
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pulldown
Input with pulldown
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pulldown
Input with pulldown
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pullup
Input with pulldown
Alternate operation3
Input with pullup
Input with pullup
Input with pulldown
Input with pulldown
Input with pullup
Input with pullup
Alternate operation3
Notes:
1. System reset is defined as a power-on reset (i.e., the RES input pin transitioning from its Low to High state) or a reset due to
a watchdog timer timeout.
2. When used as a PIO, input with a pulldown option available.
3. When used as a PIO, input with a pullup option available.
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A-7
Reset Configuration Pins (Pinstraps)1
Table 27.
Signal Name
{ADEN}
Multiplexed
Signal(s)
BHE
PIO34
{CLKSEL1}
HLDA
{CLKSEL2}
[PCS4]
PIO3
Description
Address Enable: If {ADEN} is held High or left floating during power-on reset, the
address portion of the AD bus (AD15–AD0) is enabled or disabled during LCS, UCS, or
other memory bus cycles based on how the software configures the DA bit setting. In
this case, the memory address is accessed on the A19–A0 pins. There is a weak
internal pullup resistor on {ADEN} so no external pullup is required. This mode of
operation reduces power consumption.
If {ADEN} is held Low on power-on reset, the AD bus drives both addresses and data,
regardless of how software configures the DA bit setting.
CPU PLL Mode Select 1 determines the PLL mode for the system clock source.
CPU PLL Mode Select 2 is sampled on the rising edge of reset and determines the PLL
mode for the system clock source. This pin has an internal pullup resistor that is active
only during reset. There are four CPU PLL modes that are selected by the values of
{CLKSEL1} and {CLKSEL2} as shown below. (For details on clocks see “Clock
Generation and Control” on page 32.)
CPU PLL Modes
{CLKSEL1}
{CLKSEL2}
1
1
1
0
0
1
0
0
{ONCE}
UCS
{UCSX8}
[MCS0]
PIO4
{USBSEL1}
PCS0
PIO13
{USBSEL2}
PCS1
PIO14
ONCE Mode Request asserted Low places the Am186CU USB microcontroller into
ONCE mode. Otherwise, the controller operates normally. In ONCE mode, all pins are
three-stated and remain in that state until a subsequent reset occurs. To guarantee that
the controller does not inadvertently enter ONCE mode, {ONCE} has a weak internal
pullup resistor that is active only during a reset. A reset ending ONCE mode should be as
long as a power-on reset so that the PLL will stabilize.
Upper Memory Chip Select, 8-Bit Bus asserted Low configures the upper chip select
region for an 8-bit bus size. This pin has a pullup resistor that is active only during reset,
so no external pullup is required to set the bus to 16-bit mode.
USB Clock Mode Selects 1–2 select the USB PLL operating mode. The pins have
internal pullups that are active only during reset. The USB PLL can operate in one of
three modes. With a crystal and the internal USB oscillator or an external oscillator, the
USB PLL can output 4x or 2x the input frequency. The USB PLL can also be disabled
and the USB peripheral controller can receive its clock from the CPU PLL, which is the
default mode. The pins are encoded as shown below. (For details on clocks see “Clock
Generation and Control” on page 32.)
USB PLL Modes
{USBSEL1}
{USBSEL2}
1
1
1
0
0
{USBXCVR}
S0
CPU PLL Mode
2X, CPU PLL enabled (default)
4X, CPU PLL enabled
1X, CPU PLL enabled
PLL Bypass
0
1
0
USB PLL Mode
Use system clock (after CPU PLL mode
select), USB PLL disabled (default)
4x, USB PLL enabled
2x, USB PLL enabled
Reserved
USB External Transceiver Enable asserted Low disables the internal USB transceiver
and enables the pins needed to hook up an external transceiver. This pin has a pullup
resistor that is active only during reset, so no external pullup is required as long as the
user ensures that this input is not driven Low during a power-on reset.
Notes:
1. A pinstrap is used to enable or disable features based on the state of the pin during an external reset. The pinstrap must be
held in its desired state for at least 4.5 clock cycles after the deassertion of RES. The pinstraps are sampled in an external
reset only (when RES is asserted), not during an internal watchdog timer-generated reset.
A-8
Am186™CU USB Microcontroller Data Sheet
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Table 28. Pin List Table Definitions
Pin List Table Column Definitions
The following paragraphs describe the individual
columns of information in Table 29, “Pin List Summary,”
on page A-10. The pins are grouped alphabetically by
function.
Type
B
Bidirectional
Note: All maximum delay numbers should be increased by 0.035 ns for every pF of load (up to a maximum of 150 pF) over the maximum load specified in
Table 29.
H
High
LS
Programmable to hold last state of pin
O
Totem pole output
OD
Open drain output
Column #1—Signal Name, [Alternate Function],
{Pinstrap}
This column denotes the primar y and alternate
functions of the pins. Most of the pins that have
alternate functions are configured for these functions
via firmware modifying values in the Peripheral Control
Block. Refer to the Am186™CC/CH/CU
Microcontrollers Register Set Manual, order #21916,
for full documentation of this process.
Brackets, [ ], are used to indicate the alternate,
multiplexed function of a pin (i.e., not power-on reset
default).
Braces, { }, are used to indicate the functionality of a pin
only during a processor reset. These signals are called
pinstraps. To select the desired configuration, the
pinstraps are terminated internally with pullup resistors
or externally with pulldown resistors. Their state is
sampled during a processor reset and latched on the
rising edge of reset. The signals must be held in the
desired state for 4.5 system clock cycles after the
deassertion of reset. Based on the pinstrap’s state at
the time they are latched, certain features of the
Am186CU USB microcontroller are enabled or
d i s a bl e d . A l l ex t e r n a l t e r m i n a t i o n s h o u l d b e
implemented with 10-Kohm resistors on these signals.
T h e pi ns tr a p s a r e l i s t e d i n Ta bl e 2 7 , “ R e s e t
Configuration Pins (Pinstraps),” on page A-8.
Column #2—Pin No.
Definition
[]
Pin alternate function
{}
Pinstrap pin
OD-O
Open drain output or totem pole output
PD
Internal pulldown resistor
PU
Internal pullup resistor
STI
STI-OD
TS
Schmitt trigger Input
Schmitt trigger input or open drain output
Three-state output
Column #4—Max Load (pF)
The Max Load column designates the capacitive load
at which the I/O timing for that pin is guaranteed.
Column #5—POR Default Function
The POR Default Function column shows the status of
these pins after a power-on reset. In some cases the
pin is the function outlined in the “Signal Name” column
of the table. The signal name is listed in the POR
Default Function column if the signal is the default
function and not a PIO after a processor reset. In other
cases the pin is a PIO configured as an input.
Column #6—Reset State
The Reset State column indicates the termination
present on the signal at reset (pullup or pulldown) and
indicates whether the signal is a three-stated output or
a Sc hmitt tr igger input. Refer to Table 28 for
abbreviations used in this column.
Column #7—POR Default Operation
The pin number column identifies the pin number of the
individual I/O signal on the package.
The POR Default Operation column describes the type
of input and/or output that is default pin operation.
Refer to Table 28 for abbreviations used in this column.
Column #3—Type
Column #8—Hold State
Definitions of the abbreviations in the Type column are
shown in Table 28.
The Hold State column shows the state of the pin in
hold state. Refer to Table 28 for abbreviations used in
this column.
Column #9—5 V
A "5 V" in the 5-V column indicates 5-V tolerant inputs.
These inputs are not damaged and do not draw excess
power when driven with levels up to VCC + 2.6 volts.
These pins only drive to VCC.
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A-9
Table 29.
Signal Name
[Alternate
Function]
{Pinstrap}
Pin
No.
Type
Pin List Summary
Max
Load
(pF)
POR
Default
Function
Reset
State
POR
Default
Operation
Hold
State
5V
BUS INTERFACE/GENERAL-PURPOSE DMA REQUEST
A0
30
O
70
A0
TS-PD
O
TS-PD
5V
A1
31
O
70
A1
TS-PD
O
TS-PD
5V
A2
32
O
70
A2
TS-PD
O
TS-PD
5V
A3
36
O
70
A3
TS-PD
O
TS-PD
5V
A4
37
O
70
A4
TS-PD
O
TS-PD
5V
A5
42
O
70
A5
TS-PD
O
TS-PD
5V
A6
43
O
70
A6
TS-PD
O
TS-PD
5V
A7
44
O
70
A7
TS-PD
O
TS-PD
5V
A8
45
O
70
A8
TS-PD
O
TS-PD
5V
A9
49
O
70
A9
TS-PD
O
TS-PD
5V
A10
50
O
70
A10
TS-PD
O
TS-PD
5V
A11
64
O
70
A11
TS-PD
O
TS-PD
5V
A12
65
O
70
A12
TS-PD
O
TS-PD
5V
A13
69
O
70
A13
TS-PD
O
TS-PD
5V
A14
70
O
70
A14
TS-PD
O
TS-PD
5V
A15
84
O
70
A15
TS-PD
O
TS-PD
5V
A16
85
O
70
A16
TS-PD
O
TS-PD
5V
A17
88
O
70
A17
TS-PD
O
TS-PD
5V
A18
89
O
70
A18
TS-PD
O
TS-PD
5V
A19
90
O
70
A19
TS-PD
O
TS-PD
5V
AD0
28
B
70
AD0
TS-PD
B
TS
5V
AD1
34
B
70
AD1
TS-PD
B
TS
5V
AD2
38
B
70
AD2
TS-PD
B
TS
5V
AD3
46
B
70
AD3
TS-PD
B
TS
5V
AD4
51
B
70
AD4
TS-PD
B
TS
5V
AD5
66
B
70
AD5
TS-PD
B
TS
5V
AD6
86
B
70
AD6
TS-PD
B
TS
5V
AD7
92
B
70
AD7
TS-PD
B
TS
5V
AD8
29
B
70
AD8
TS-PD
B
TS
5V
AD9
35
B
70
AD9
TS-PD
B
TS
5V
AD10
39
B
70
AD10
TS-PD
B
TS
5V
AD11
47
B
70
AD11
TS-PD
B
TS
5V
AD12
52
B
70
AD12
TS-PD
B
TS
5V
AD13
67
B
70
AD13
TS-PD
B
TS
5V
AD14
87
B
70
AD14
TS-PD
B
TS
5V
AD15
93
B
70
AD15
TS-PD
B
TS
5V
ALE
[PIO33]
19
O
STI-PD [STI] [O]
50
ALE
TS-PD
O
TS-PD
5V
ARDY
[PIO8]
14
STI-PU
STI-PU [STI] [O]
50
ARDY
STI-PU
STI-PU
STI
5V
A-10
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Table 29.
Signal Name
[Alternate
Function]
{Pinstrap}
Pin
No.
BHE
[PIO34]
{ADEN}
20
BSIZE8
Pin List Summary (Continued)
Max
Load
(pF)
POR
Default
Function
Reset
State
POR
Default
Operation
Hold
State
5V
O
STI-PU [STI] [O]
STI
50
BHE
STI-PU
O
TS-PU
5V
Type
94
O
50
BSIZE8
TS-PU
O
—
—
DEN
[DS]
[PIO30]
18
O
O
STI-PU [STI] [O]
50
DEN
TS-PU
O
TS-PU
5V
[DRQ0]
PIO9
124
STI-PD
STI-PD [STI] [O]
50
PIO9
STI-PD
STI-PD [STI] [O]
—
5V
DRQ1
105
STI-PD
—
DRQ1
STI-PD
STI-PD
—
5V
DT/R
[PIO29]
17
O
STI-PU [STI] [O]
50
DT/R
TS-PU
O
TS-PU
5V
HLDA
{CLKSEL1}
98
O
STI
50
HLDA
STI-PU
O
H
5V
HOLD
99
STI
—
HOLD
STI-PD
STI
H
5V
RD
97
O
70
RD
TS-PU
O
TS-PU
5V
S0
{USBXCVR}
57
O
STI
50
S0
STI-PU
O
TS
5V
S1
56
O
50
S1
TS-PU
O
TS
5V
S2
55
O
50
S2
TS-PU
O
TS
5V
S6
54
O
50
S6
TS-PD
O
TS
5V
SRDY
[PIO35]
15
STI-PU
STI-PU [STI] [O]
50
SRDY
STI-PU
STI-PU
—
5V
WHB
95
O
70
WHB
TS-PU
O
TS-PU
5V
WLB
96
O
70
WLB
TS-PU
O
TS-PU
5V
WR
[PIO15]
16
O
STI-PU [STI] [O]
50
WR
STI-PU
O
TS-PU
5V
LCS
[RAS0]
131
O
O
50
LCS
TS-PU
O
TS-PU
5V
[MCS0]
PIO4
{UCSX8}
126
O
STI-PU [STI] [O]
STI
50
PIO4
STI-PU
STI-PU [STI] [O]
TS-PU
5V
MCS1
[CAS1]
127
O
O
50
MCS1
TS-PU
O
TS-PU
5V
MCS2
[CAS0]
128
O
O
50
MCS2
TS-PU
O
TS-PU
5V
[MCS3]
[RAS1]
PIO5
129
O
O
STI-PU [STI] [O]
50
PIO5
STI-PU
STI-PU [STI] [O]
TS-PU
5V
PCS0
[PIO13]
{USBSEL1}
5
O
STI-PU [STI] [O]
STI
50
PCS0
STI-PU
O
TS-PU
5V
PCS1
[PIO14]
{USBSEL2}
6
O
STI-PU [STI] [O]
STI
50
PCS1
STI-PU
O
TS-PU
5V
PCS2
7
O
50
PCS2
TS-PU
O
TS-PU
5V
CHIP SELECTS
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A-11
Table 29.
Signal Name
[Alternate
Function]
{Pinstrap}
Pin List Summary (Continued)
Max
Load
(pF)
POR
Default
Function
Reset
State
POR
Default
Operation
Hold
State
5V
O
50
PCS3
TS-PU
O
TS-PU
5V
9
O
STI-PU [STI] [O]
STI
50
PIO3
STI-PU
STI-PU [STI] [O]
TS-PU
5V
[PCS5]
PIO2
10
O
STI-PU [STI] [O]
50
PIO2
STI-PU
O
TS-PU
5V
[PCS6]
PIO32
11
O
STI-PU [STI] [O]
50
PIO32
STI-PU
STI-PU [STI] [O]
TS-PU
5V
[PCS7]
PIO31
13
O
STI-PU [STI] [O]
50
PIO31
STI-PU
STI-PU [STI] [O]
TS-PU
5V
UCS
{ONCE}
132
O
STI
50
UCS
STI-PU
O
TS-PU
5V
Pin
No.
Type
PCS3
8
[PCS4]
PIO3
{CLKSEL2}
CLOCKS/RESET/WATCHDOG TIMER
CLKOUT
60
O
70
CLKOUT
—
O
—
—
RES
114
ST
—
RES
STI
STI
—
5V
RESOUT
58
O
50
RESOUT
H
O
—
5V
[UCLK]
[USBSOF]
[USBSCI]
PIO21
22
STI
O
STI
STI-PU [STI] [O]
50
PIO21
STI-PU
STI-PU [STI] [O]
—
5V
USBX1
75
STI
—
USBX1
—
STI
—
—
USBX2
76
O
—
USBX2
—
O
—
—
X1
73
STI
—
X1
—
STI
—
—
X2
74
O
—
X2
—
O
—
—
PROGRAMMABLE TIMERS
[PWD]
[INT8]
PIO6
147
STI
STI
STI-PU [STI] [O]
50
PIO6
STI-PU
STI-PU [STI] [O]
—
5V
[TMRIN0]
PIO27
142
STI-PU
STI-PU [STI] [O]
50
PIO27
STI-PU
STI-PU [STI] [O]
—
5V
[TMRIN1]
PIO0
144
STI-PU
STI-PU [STI] [O]
50
PIO0
STI-PU
STI-PU [STI] [O]
—
5V
[TMROUT0]
PIO28
141
O
STI-PD [STI] [O]
50
PIO28
STI-PD
STI-PD [STI] [O]
TS
5V
[TMROUT1]
PIO1
143
O
STI-PD [STI] [O]
50
PIO1
STI-PD
STI-PD [STI] [O]
TS
5V
INT0
107
STI
—
INT0
STI-PU
STI
—
5V
INT1
109
STI
—
INT1
STI-PU
STI
—
5V
INT2
110
STI
—
INT2
STI-PU
STI
—
5V
INT3
111
STI
—
INT3
STI-PU
STI
—
5V
INT4
112
STI
—
INT4
STI-PU
STI
—
5V
INT5
113
STI
—
INT5
STI-PU
STI
—
5V
[INT6]
PIO19
145
STI
STI-PU [STI] [O]
50
PIO19
STI-PU
STI-PU [STI] [O]
—
5V
INTERRUPTS
A-12
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Table 29.
Signal Name
[Alternate
Function]
{Pinstrap}
Pin
No.
[INT7]
PIO7
146
[INT8]
[PWD]
PIO6
NMI
Pin List Summary (Continued)
Max
Load
(pF)
POR
Default
Function
Reset
State
POR
Default
Operation
Hold
State
5V
STI
STI-PU [STI] [O]
50
PIO7
STI-PU
STI-PU [STI] [O]
—
5V
147
STI
STI
STI-PU [STI] [O]
50
PIO6
STI-PU
STI-PU [STI] [O]
—
5V
115
STI
—
NMI
STI-PU
STI
—
5V
Type
ASYNCHRONOUS SERIAL PORTS (UART AND HIGH-SPEED UART)
UART
[RXD_U]
PIO26
158
STI
STI-PU [STI] [O]
50
PIO26
STI-PU
STI-PU [STI] [O]
—
5V
[TXD_U]
PIO20
159
O
STI-PU [STI] [O]
50
PIO20
STI-PU
STI-PU [STI] [O]
—
5V
[CTS_U]
PIO24
157
STI
STI-PU [STI] [O]
50
PIO24
STI-PU
STI-PU [STI] [O]
—
5V
[RTR_U]
PIO25
156
O
STI-PU [STI] [O]
30
PIO25
STI-PU
STI-PU [STI] [O]
—
5V
[RXD_HU]
PIO16
25
STI
STI-PU [STI] [O]
50
PIO16
STI-PU
STI-PU [STI] [O]
—
5V
TXD_HU
HIGH-SPEED UART
26
O
30
TXD_HU
TS-PU
O
—
5V
[CTS_HU]
PIO46
24
STI
STI-PU [STI] [O]
50
PIO46
STI-PU
STI-PU [STI] [O]
—
5V
[RTR_HU]
PIO47
23
O
STI-PU [STI] [O]
30
PIO47
STI-PU
STI-PU [STI] [O]
—
5V
QS0
62
O
30
QS0
TS-PD
O
—
5V
QS1
63
O
30
QS1
TS-PD
O
—
5V
DEBUG SUPPORT
UNIVERSAL SERIAL BUS
USBD+
[UDPLS]
81
B
STI
—
USBD+
TS
B
—
—
USBD–
[UDMNS]
80
B
STI
—
USBD–
TS
B
—
—
SYNCHRONOUS SERIAL INTERFACE (SSI)
[SCLK]
PIO11
3
O
STI-PU [STI] [O]
50
PIO11
STI-PU
STI-PU [STI] [O]
—
5V
[SDATA]
PIO12
4
O
STI-PU [STI] [O]
50
PIO12
STI-PU
STI-PU [STI] [O]
—
5V
[SDEN]
PIO10
2
O
STI-PD [STI] [O]
50
PIO10
STI-PD
STI-PD [STI] [O]
—
5V
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A-13
Table 29.
Signal Name
[Alternate
Function]
{Pinstrap}
Pin List Summary (Continued)
Max
Load
(pF)
POR
Default
Function
Reset
State
POR
Default
Operation
Hold
State
5V
—
—
STI-PU
—
—
—
—
TS-PU
—
—
—
—
PU
—
—
—
—
PU
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
117
—
—
—
—
—
—
—
116
—
—
—
—
—
—
—
VCC
12
—
—
—
—
—
—
—
VCC
27
—
—
—
—
—
—
—
VCC
40
—
—
—
—
—
—
—
VCC
48
—
—
—
—
—
—
—
VCC
59
—
—
—
—
—
—
—
VCC
68
—
—
—
—
—
—
—
VCC
78
—
—
—
—
—
—
—
VCC
91
—
—
—
—
—
—
—
VCC
106
—
—
—
—
—
—
—
VCC
120
—
—
—
—
—
—
—
VCC
125
—
—
—
—
—
—
—
VCC
133
—
—
—
—
—
—
—
VCC
148
—
—
—
—
—
—
—
VCC
160
—
—
—
—
—
—
—
VCC_A
77
—
—
—
—
—
—
—
VCC_USB
79
—
—
—
—
—
—
—
VSS
1
—
—
—
—
—
—
—
VSS
21
—
—
—
—
—
—
—
VSS
33
—
—
—
—
—
—
—
VSS
41
—
—
—
—
—
—
—
VSS
53
—
—
—
—
—
—
—
VSS
61
—
—
—
—
—
—
—
VSS
71
—
—
—
—
—
—
—
VSS
83
—
—
—
—
—
—
—
VSS
100
—
—
—
—
—
—
—
VSS
108
—
—
—
—
—
—
—
VSS
121
—
—
—
—
—
—
—
VSS
130
—
—
—
—
—
—
—
VSS
140
—
—
—
—
—
—
—
VSS
155
—
—
—
—
—
—
—
Pin
No.
Type
RSVD_104
[UXVRCV]
104
—
STI
RSVD_103
[UXVOE]
103
—
O
50
RSVD_102
[UTXDMNS]
102
—
O
50
RSVD_101
[UTXDPLS]
101
—
O
50
RSVD_119
119
—
RSVD_118
118
RSVD_117
RSVD_116
RESERVED PINS
POWER AND GROUND
A-14
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Table 29.
Signal Name
[Alternate
Function]
{Pinstrap}
Pin
No.
Type
VSS_A
72
VSS_USB
82
Pin List Summary (Continued)
Max
Load
(pF)
POR
Default
Function
Reset
State
POR
Default
Operation
Hold
State
5V
—
—
—
—
—
—
—
—
—
—
—
—
—
—
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A-16
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APPENDIX B—PHYSICAL DIMENSIONS: PQR160, PLASTIC QUAD FLAT PACK (PQFP)
Pin 160
25.35
REF
27.90
28.10
31.00
31.40
Pin 120
Pin 1 I.D.
25.35
REF
27.90
28.10
31.00
31.40
Pin 40
Pin 80
3.20
3.60
0.65 BASIC
0.25
Min
3.95
MAX
SEATING PLANE
16-038-PQR-1
PQR160
12-22-95 lv
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B-2
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APPENDIX C—CUSTOMER SUPPORT
AMD-K6™-2E
Microprocessor
AMD-K6™E
Microprocessor
Am5x86®
Microprocessor
Am486®DX
Microprocessor
ÉlanSC400
Microcontroller
Am386®SX/DX
Microprocessors
Élan™SC310
Microcontroller
ÉlanSC520
Microcontroller
ÉlanSC410
Microcontroller
ÉlanSC300
Microcontroller
Am186CC
Communications
Controller
Am186CH HDLC
Microcontroller
Am186™CU USB
Microcontroller
Am186EM and
Am188™EM
Microcontrollers
80C186 and 80C188
Microcontrollers
Am186EMLV &
Am188EMLV
Microcontrollers
Am186ES and
Am188ES
Microcontrollers
Am186ER and
Am188ER
Microcontrollers
Am186ESLV &
Am188ESLV
Microcontrollers
80L186 and 80L188
Microcontrollers
Am186ED
Microcontroller
Am186EDLV
Microcontroller
— Microprocessors
— 16- and 32-bit microcontrollers
— 16-bit microcontrollers
E86™ Family of Embedded Microprocessors and Microcontrollers
Related AMD Products—E86™ Family Devices
Device
80C186/80C188
80L186/80L188
Am186™EM/Am188™EM
Am186EMLV/Am188EMLV
Am186ES/Am188ES
Am186ESLV/Am188ESLV
Am186ED
Am186EDLV
Am186ER/Am188ER
Am186CC
Am186CH
Am186CU
Élan™SC300
ÉlanSC310
ÉlanSC400
ÉlanSC410
ÉlanSC520
Am386®DX
Am386®SX
Am486®DX
Am5x86
AMD-K6™E
AMD-K6™-2E
Description
16-bit microcontroller
Low-voltage, 16-bit microcontroller
High-performance, 16-bit embedded microcontroller
High-performance, 16-bit embedded microcontroller
High-performance, 16-bit embedded microcontroller
High-performance, 16-bit embedded microcontroller
High-performance, 80C186- and 80C188-compatible, 16-bit embedded microcontroller
with 8- or 16-bit external data bus
High-performance, 80C186- and 80C188-compatible, low-voltage, 16-bit embedded
microcontroller with 8- or 16-bit external data bus
High-performance, low-voltage, 16-bit embedded microcontroller with 32 Kbyte of
internal RAM
High-performance, 16-bit embedded communications controller
High-performance, 16-bit embedded HDLC microcontroller
High-performance, 16-bit embedded USB microcontroller
High-performance, highly integrated, low-voltage, 32-bit embedded microcontroller
High-performance, single-chip, 32-bit embedded PC/AT microcontroller
Single-chip, low-power, PC/AT-compatible microcontroller
Single-chip, PC/AT-compatible microcontroller
High-performance, 32-bit embedded microcontroller
High-performance, 32-bit embedded microprocessor with 32-bit external data bus
High-performance, 32-bit embedded microprocessor with 16-bit external data bus
High-performance, 32-bit embedded microprocessor with 32-bit external data bus
High-performance, 32-bit embedded microprocessor with 32-bit external data bus
High-performance, 32-bit embedded microprocessor with 64-bit external data bus
High-performance, 32-bit embedded microprocessor with 64-bit external data bus and
3DNow!™ technology
Notes:
1. 186 = 16-bit microcontroller and 80C186-compatible (except where noted otherwise); 188 = 16-bit microcontroller with 8-bit
external data bus and 80C188-compatible (except where noted otherwise); LV = low voltage
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Related Documents
The following documents provide additional information
regarding the Am186CU USB microcontroller.
■ Am186™CC/CH/CU Microcontrollers User’s Manual,
order #21914
■ Am186™CC/CH/CU Microcontrollers Register Set
Manual, order #21916
■ Am186™ and Am188™ Family Instruction Set
Manual, order #21267
■ Interfacing an Am186™CC Communications
Controller to an AMD SLAC™ Device Using the
Enhanced SSI Application Note, order #21921
Other information of interest includes:
■ E86™ Family Products and Development Tools CD,
order #21058
Am186CC/CH/CU Microcontroller
Customer Development Platform
The Am186CC/CH/CU customer development
platform (CDP) is provided as a test and development
platform for the Am186CC/CH/CU microcontrollers
Am186CU USB microcontroller. The Am186CC/CH/CU
CDP ships with the Am186CC microcontroller.
Because this device suppor ts a superset of the
features of the Am186CU USB microcontroller, the
development platform can be used to evaluate the
Am186CU device.
The CDP is divided into two major sections: a main
board and a development module. The main board
serves as the primary platform for silicon evaluation
and software development. The board provides
connectors for accessing the major communications
pe r i ph era l s, sw it ch e s to ea s il y c on fi gu r e th e
microcontroller, logic analyzer, and debug headers.
The development module, which attaches to the top of
the main board, provides ready-to-run hardware for
three of the most common communications
requirements:
UARTs, PCnet-ISA II (AMD’s single-chip Ethernet
solution), and several other common peripherals. The
CodeKit software comes complete with instructions,
royalty-free distribution rights, and software in both
binary and source code formats.
Third-Party Development Support Products
The FusionE86 S M Program of Par tnerships for
Application Solutions provides the customer with an
array of products designed to meet critical time-tomarket needs. Products and solutions available from
the AMD FusionE86 partners include protocol stacks,
emulators, hardware and software debuggers, boardlevel products, and software development tools, among
others.
In addition, mature development tools and applications
for the x86 platform are widely available in the general
marketplace.
Customer Service
The AMD customer service network includes U.S.
offices, international offices, and a customer training
center. Expert technical assistance is available from
the AMD worldwide staff of field application engineers
and factor y suppor t staff to answer E86™ and
Comm86™ family hardware and software development
questions.
Note: The support telephone numbers listed below
are subject to change. For current telephone numbers,
refer to www.amd.com/support/literature.
Hotline and World Wide Web Support
For answers to technical questions, AMD provides
e-mail support as well as a toll-free number for direct
access to our corporate applications hotline.
The AMD World Wide Web home page provides the
latest product infor mation, including technical
information and data on upcoming product releases. In
addition, EPD CodeKit software on the Web site
provides tested source code example applications.
■ A 10 Mbit/s Ethernet connection
Corporate Applications Hotline
■ An ISDN connection (with both an S/T and a
U interface)
(800) 222-9323
Toll-free for U.S. and Canada
■ Two POTS interfaces
44-(0) 1276-803-299
U.K. and Europe hotline
The CDP provides a good starting point for hardware
designers, and software development can begin
immediately without the normal delay that occurs while
waiting for prototypes.
Additional contact information is listed on the back of
this datasheet. For technical support questions on all
E86 and Comm86 products, send e-mail to
[email protected]
The CDP also comes with AMD’s CodeKit software
that provides customers with pre-written driver
software for the major communications peripherals
associated with a typical Am186Cx design. Included
are drivers for the HDLC channels, USB peripheral
controller (for the Am186CU USB microcontroller),
C-2
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World Wide Web Home Page
To access the AMD home page go to: www.amd.com.
Then follow the Embedded Processors link for
information about E86 and Comm86 products.
Questions, requests, and input concerning AMD’s
WWW pages can be sent via e-mail to
[email protected]
Documentation and Literature
Free information such as data books, user’s manuals,
data sheets, application notes, the E86™ Family
Products and Development Tools CD, order #21058,
and other literature is available with a simple phone
call. Internationally, contact your local AMD sales office
for product literature. Additional contact information is
listed on the back of this data sheet.
Literature Ordering
(800) 222-9323
Toll-free for U.S. and Canada
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INDEX
A
B
A19–A0 signals, 13
absolute maximum ratings, 37
AD15–AD0 signals, 13
address and data bus (AD15–AD0)
description, 13
address bus (A19–A0)
address bus disable in effect, 29
default operation, 29
description, 13
ADEN signal, A-8
ALE signal, 13
Am186CU USB microcontroller
applications, 31
block diagram (microcontroller), 24
DC characteristics, 38
detailed description, 24
distinctive characteristics, 1
documentation, C-2
general description, 1
I/O circuitry, 36
logic diagram by default pin function, 7
logic diagram by interface, 6
ordering information, 2
overview (architectural), 24
physical dimensions, B-1
pin assignment tables, 10
pin connection diagram, 8
pin tables (Appendix A), A-1
PQFP package, B-1
related AMD E86 family devices, C-1
signal description table, 13
applications, 31
architectural overview, 24
ARDY signal, 13
asynchronous communications
asynchronous ready waveforms, 59
asynchronous serial ports (description), 26
baud clock, 35
High-Speed UART clocks, 35
High-Speed UART signal descriptions, 22
UART signal descriptions, 22
BHE signal, 14
block diagram (microcontroller), 24
BSIZE8 signal, 14
bus
address bus description, 13
bus hold timing, 60
bus status pins, 16
entering bus hold waveforms, 60
exiting bus hold waveforms, 60
bus interface
description, 30
signal list, 13
byte write enables, 30
C
capacitance, 38
CAS1–CAS0 signals, 20
characteristics
See DC characteristics.
chip selects
description, 30
ranges and DRAM configuration, 13, 20
signal descriptions, 19
CLKOUT signal, 17
CLKSEL2–CLKSEL1 signals, A-8
clock
See also CPU.
CLKOUT signal description, 17
clock generation and control, 32
clock sharing by system and USB, 33
control, 31
crystal parameters, 34
crystal-driven clock source, 34
external clock source, 35
external interface to support clocks, 34–35
features, 32
High-Speed UART clocks, 35
PLL Bypass mode, 35
suggested system clock frequencies, clock modes
and crystal frequencies, 34
system clock, 32
system interfaces and clock control, 28
UART baud clock, 35
USB clock, 32
USB clock timing waveforms, 62
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USB clocks timing, 62
CPU
Am186 embedded CPU, 25
CPU PLL modes, A-8
system clock, 32
system clock timing waveforms, 62
system clocks timing, 61
crystal
crystal-driven clock source, 34
parameters, 34
suggested crystal frequencies, 34
CTS_HU signal, 22
CTS_U signal, 22
customer support
documentation and literature, C-3
hotline and web, C-2
literature ordering, C-3
ordering the microcontroller, 2
third-party development support products, C-2
web home page, C-3
D
DC characteristics over commercial and industrial
operating ranges, 38
debug
debug support signals, 18
DEN signal, 14
derating, 39
DMA (direct memory access)
DMA request signals, 14
general-purpose DMA channels, 27
SmartDMA channels, 26
timing waveforms, 55
documentation, C-3
DRAM
chip selects and DRAM configuration, 13
description, 30
read cycle with wait states waveform, 66
read cycle without wait states waveform, 65
refresh cycle waveform, 67
signal descriptions, 20
support, 30
timing, 65
write cycle with wait states waveform, 67
write cycle without wait states waveform, 66
DRQ1–DRQ0 signals, 14
DS signal, 14
DT/R signal, 14
Index-2
E
emulation
in-circuit emulator support, 31
signals used by emulators, 18
enables
byte write, 30
output, 30
evaluation platform, C-2
external ready
See ready.
H
halt
See software halt.
High-Speed UART
signal descriptions, 22
HLDA signal, 15
HOLD latency, 15
HOLD signal, 15
hotline and world wide web support, C-2
I
I/O
See also memory.
I/O circuitry, 36
I/O space, 25
programmable I/O (PIO), 27
ICE (in-circuit emulator)
support, 31
INT8–INT0 signals, 20
interrupts
interrupt controller, 27
signal descriptions, 20
L
LCS signal, 19
logic diagram
by default pin function, 7
by interface, 6
M
MCS3–MCS0 signals, 19
memory
memory and peripheral interface, 28
memory organization, 25
segment register selection rules, 25
multiplexed functions
signal trade-offs, A-5
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N
power
ground pins, 18
power consumption calculation, 39
power pins, 18
power supply operation, 36
supply connections, 36
supply current, 39
typical ICC versus frequency, 39
PQFP package
physical dimensions, B-1
pulldowns, in Pin List Summary table, Type column, A10
pullups, in Pin List Summary table, Type column, A-10
PWD signal, 21
NMI signal, 20
O
ONCE signal, A-8
operating ranges, 37
ordering information, 2
output enable, 30
P
package
PQFP physical dimensions, B-1
PCS7–PCS0 signals, 19
peripherals
memory and peripheral interface, 28
peripheral timing, 55
peripheral timing waveforms, 55
system interfaces, 27
pins
See also signals.
pin and signal tables, 9
pin assignments sorted by pin number, 10
pin assignments sorted by signal name, 11
pin connection diagram, 8
pin defaults, A-2
pin list summary, A-10
pin tables (Appendix A), A-1
Multiplexed Signal Trade-Offs table, A-5
Pin List Summary table, A-10
PIOs Sorted by PIO Number table, A-6
PIOs Sorted by Signal Name table, A-7
Power-On Reset (POR) Pin Defaults table, A-2
Reset Configuration Pins (Pinstraps) table, A-8
reserved, 18
pinstraps, A-8
PIO47–PIO0 signals, 21
PIOs (programmable I/Os)
description, 27
signal descriptions, 21
sorted by pin number, A-6
sorted by signal name, A-7
PLL (phase-locked loop)
modes, A-8
PLL bypass (CPU), A-8
PLL Bypass mode, 35
system PLL, 32
USB PLL, 32
POR (power-on reset)
pin defaults, A-2
Q
QS1–QS0 signals, 18
R
RAS1–RAS0 signals, 20
RD signal, 15
read cycle timing, 48
read cycle waveforms, 50
ready
external ready timing, 58
synchronous ready waveforms, 58
RES signal, 17
reserved pins, 18
reset
definition of types, 12
power-on reset pin defaults table, A-2
signals related to reset, 57
timing, 56
waveforms, 56
reset configuration pins
See pinstraps.
RESOUT signal, 17
RSVD_x–RSVD_x pins, 18
RTR_HU signal, 22
RTR_U signal, 22
RXD_HU signal, 22
RXD_U signal, 22
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Index-3
S
S2–S0 signals, 16
S6 signal, 16
SCLK signal, 23
SDATA signal, 23
SDEN signal, 23
serial communications
See also HDLC, UART.
asynchronous serial ports, 26
description, 26
synchronous serial port, 26
USB, 26
signals
See also pins.
multiplexed signal trade-offs table, A-5
pin and signal tables, 9
pin assignments sorted by signal name, 11
signal descriptions, 13
signals related to reset, 57
software halt cycle timing, 54
software halt cycle waveforms, 54
SRDY signal, 16
SSI (synchronous serial interface)
signal descriptions, 23
synchronous ready waveforms, 58
synchronous serial port, 26
timing, 64
waveforms, 64
static operation, 35
switching characteristics and waveforms
alphabetical key, 42
key to switching waveforms, 41
numerical key to switching parameter symbols, 45
over commercial/industrial operating ranges, 48
parameter symbols, 42
system clock, 32
See CPU.
system interface, 28
T
thermal characteristics, 40
equations, 40
thermal resistance, 40
timers
See also watchdog timer.
programmable timers, 27
signal descriptions, 21
Index-4
timing
asynchronous ready waveforms, 59
bus hold, 60
DMA, 55
DRAM, 65
external ready cycle, 58
peripheral timing, 55
read cycle timing, 48
reset, 56
software halt cycle, 54
SSI, 64
synchronous ready waveforms, 58
system clocks timing, 61
USB, 63
USB clocks, 62
write cycle timing, 51
TMRIN1–TMRIN0 signals, 21
TMROUT1–TMROUT0 signals, 21
TXD_HU signal, 22
TXD_U signal, 22
U
UART
asynchronous ready waveforms, 59
asynchronous serial ports (description), 26
baud clock, 35
High-Speed UART clocks, 35
High-Speed UART signal descriptions, 22
signal descriptions, 22
UART and High-Speed UART Clocks, 35
UART Baud Clock, 35
UCLK signal, 17
UCS signal, 19
UCSX8 signal, A-8
UDMNS signal, 23
UDPLS signal, 23
USB
clock, 32
clock timing waveforms, 62
clocks timing, 62
data signal rise and fall times, 63
description, 26
driver characteristics, 37
external transceiver signals, 23
PLL modes, A-8
receiver jitter tolerance, 63
signal descriptions, 23
system and USB clock generation, 33
timing, 63
USBD– signal, 23
USBD+ signal, 23
USBSCI signal, 23
USBSEL2–USBSEL1 signals, A-8
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USBSOF signal, 23
USBXCVR signal, A-8
UTXDMNS signal, 23
UTXDPLS signal, 23
UXVOE signal, 23
UXVRCV signal, 23
V
VCC description, 18
VCC_A description, 18
VCC_USB description, 18
VSS description, 18
VSS_A description, 18
VSS_USB description, 18
W
watchdog timer
description, 27
RES and watchdog timer reset, 17
WHB signal, 16
WLB signal, 16
WR signal, 16
write cycle timing, 51
write cycle waveforms, 53
www
home page, C-3
support, C-2
X
X1 signal, 17
X2 signal, 17
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Index-5
Trademarks
È 2000 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.
Am5x86, Am386, and Am486 are registered trademarks, and AMD-K6, 3DNow!, Am186, Am188, Comm86, E86, Élan, PCnet, SLAC, and
SmartDMA are trademarks of Advanced Micro Devices, Inc.
FusionE86 is a service mark of Advanced Micro Devices, Inc.
Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
Disclaimer
The contents of this document are provided in connection with Advanced Micro Devices, Inc. ("AMD") products. AMD makes no representations
or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. Except as set forth in AMD's Standard Terms and Conditions of Sale, AMD assumes no
liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of
merchantability, fitness for a particular purpose, or infringement of any intellectual property right.
AMD's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the
body, or in other applications intended to support or sustain life, or in any other application in which the failure of AMD's product could create a
situation where personal injury, death, or severe property or environmental damage may occur. AMD reserves the right to discontinue or make
changes to its products at any time without notice.
© 2000 Advanced Micro Devices, Inc.
All rights reserved.
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