MSSP MODULE MSSP Module Silicon/Data Sheet Errata The PICmicro® microcontrollers you have received all exhibit anomalous behavior in their Master SSP (MSSP) modules, as described in this document. They otherwise conform functionally to the descriptions provided in their respective Device Data Sheets and Reference Manuals, as amended by silicon release errata for particular devices. Users are encouraged to review the latest Device Data Sheets and errata available for additional information concerning an individual device. These documents may be obtained directly from the Microchip corporate web site, at www.microchip.com. This issue is expected to be resolved in future silicon revisions of the designated parts. This issue effects all silicon revisions of the following devices: 1. Issue: I2C™ (Slave Mode) In its current implementation, the module may fail to correctly recognize certain Repeated START conditions. For this discussion, a Repeated START is defined as a START condition presented to the bus after an initial valid START condition has been recognized and the START status bit (SSPSTAT<3>) has been set, and before a valid STOP condition is received. If a Repeated START is not recognized, a loss of synchronization between the Master and Slave may occur; the condition may continue until the module is reset. A NACK condition, generated by the Slave for any reason, will not reset the module. This failure has been observed only under two circumstances: • PIC16C717 • PIC18C801 • PIC16C770 • PIC18C658 • PIC16C771 • PIC18C858 • PIC16C773 • PIC18F2220 • PIC16C774 • PIC18F2320 • PIC16F872 • PIC18F242 • PIC16F873 • PIC18F2439 • PIC16F873A • PIC18F248 • PIC16F874 • PIC18F252 • PIC16F874A • PIC18F2539 • A Repeated START occurs within the frame of a data or address byte. The unexpected START condition may be erroneously interpreted as a data bit, provided that the required conditions for setup and hold times are met. • A Repeated START condition occurs between two back-to-back slave address matches in the same Slave, with the R/W bit set to Read (= 1) in both cases. (This circumstance is regarded as being unlikely in normal operation.) • PIC16F876 • PIC18F258 Work around • PIC16F876A • PIC18F4220 • PIC16F877 • PIC18F4320 • PIC16F877A • PIC18F442 • PIC17C752 • PIC18F4439 • PIC17C756 • PIC18F448 A time-out routine should be used to monitor the module's operation. The timer is enabled upon the receipt of a valid START condition; if a time-out occurs, the module is reset. The length of the timeout period will vary from application to application, and will need to be determined by the user. • PIC17C756A • PIC18F452 Two methods are suggested to reset the module: • PIC17C762 • PIC18F4539 • PIC17C766 • PIC18F458 • PIC18C242 • PIC18F6620 • PIC18C252 • PIC18F6720 • PIC18C442 • PIC18F8620 • PIC18C452 • PIC18F8720 1. Change the mode of the module to something other than the desired mode by changing the settings of bits SSPM3:SSPM0 (SSPCON1<3:0>); then, change the bits back to desired configuration. 2. Disable the module by clearing the SSPEN bit (SSPCON1<5>); then, re-enable the module by setting the bit. • PIC18C601 Other methods may be available. 2003 Microchip Technology Inc. DS80131C-page 1 MSSP MODULE Clarifications/Corrections to the Data Sheets Note: All corrections apply to the Data Sheets for the following devices: • • • • • • • • • • • • • • PIC16C717/770/771 (DS41120B) PIC16C773/774 (DS30275A) PIC16F872 (DS30221B) PIC16F873/874/876/877 (DS30292C) PIC16F873A/874A/876A/877A (DS39582A) PIC17C752/756A/762/766 (DS30289B) PIC18C242/252/442/452 (DS39026C) PIC18C601/801 (DS39541A) PIC18C658/858 (DS30475A) PIC18F242/252/442/452 (DS39564B) PIC18F248/258/448/458 (DS41159C) PIC18F2220/2320/4220/4320 (DS39599B) PIC18F2439/2539/4439/4539 (DS30485A) PIC18F6620/6720/8620/8720 (DS39580A) 1. Module: MSSP (SPI Mode) The description of the operation of the CKE bit (SSPSTAT<6>) is clarified. Please substitute the description in Register 1, below, for all occurrences of the existing text for the SSPSTAT register, bit 6 (new text in bold). Note: This text refers only to the operation of the CKE bit in SPI mode; its operation in I2C mode is unchanged. For those data sheets that describe the SSPSTAT register in separate locations for SPI and I2C modes, this description applies only to the register titled “SSPSTAT Register (SPI Mode)”. 2. Module: MSSP (SPI Slave Mode) The description of the operation of SPI Slave mode is clarified as follows: the state of the clock line (SCK) must match the polarity for the IDLE state before enabling the module. The subsection of the “MSSP Module” chapter entitled “Slave Mode” (Subsection 3.6 in the majority of data sheets, Subsection 3.5 in others) is amended by adding the following paragraph to the end of the existing text: “Before enabling the module in SPI Slave mode, the clock line must match the proper IDLE state. The clock line can be observed by reading the SCK pin. The IDLE state is determined by the CKP bit (SSPCON1<4>) .” REGISTER 1: bit 6 SSPSTAT: MSSP STATUS REGISTER (EXCERPT) CKE: SPI Clock Select bit 1 = Transmit occurs on transition from active to IDLE clock state 0 = Transmit occurs on transition from IDLE to active clock state Note: DS80131C-page 2 Polarity of clock state is set by the CKP bit (SSPCON1<4>). 2003 Microchip Technology Inc. MSSP MODULE REVISION HISTORY Revision A Document (7/2002): Original version (I2C Slave Issue) Revision B Document (1/2003): Clarification of original issue to include Restart conditions. Addition of data sheet clarification 1 (SPI Mode, CKE bit). Revision C Document (3/2003): Addition of data sheet clarification 2 (SPI Slave Mode, operation). 2003 Microchip Technology Inc. DS80131C-page 3 MSSP MODULE NOTES: DS80131C-page 4 2003 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, KEELOQ, MPLAB, PIC, PICmicro, PICSTART, PRO MATE and PowerSmart are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Accuron, Application Maestro, dsPIC, dsPICDEM, dsPICDEM.net, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICC, PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPIC, Select Mode, SmartSensor, SmartShunt, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2003, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. 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