ETC X84041SI2.7

MPS™ EEPROM
X84041
4K
Micro Port Saver EEPROM
FEATURES
DESCRIPTION
• Direct interface to micros
—Eliminates I/O port requirements
—No interface glue logic required
—Eliminates need for parallel to serial converters
• 3.3Mbps data transfer rate
• Low power CMOS
—2.7V to 5.5V operation
—Standby current less than 50µA
—Active current less than 1mA
• 45ns read access time
• 8-byte page write mode
• Typical nonvolatile write cycle time: 5ms
• High reliability
—100,000 endurance cycles
—Guaranteed data retention: 100 years
• 8-lead PDIP, 8-lead SOIC, and 14-lead TSSOP
packages
The X84041 Micro Port Saver is a 4096-bit CMOS
EEPROM designed for a direct interface to port limited
microcontroller or I/O limited microprocessor designs.
The X84041 provides all of the benefits of serial memories, such as low cost, low power, low voltage operation, and small package size, while featuring higher
data transfer rates and reduced interface code requirements—without the need for a dedicated serial bus.
The X84041 is organized as a 512 x 8, but is also suitable in 16-bit or 32-bit environments, due to the bit
serial nature of the interface.
The X84041 directly connects to the processor bus
and communicates over a single data line using a
sequence of standard bus read and write operations.
This eliminates the need for dedicated port pins, parallel to serial converters, complicated ASIC implementations, or other glue logic, lowering system cost.
BLOCK DIAGRAM
WP
H.V. Generation
Timing & Control
CE
OE
WE
I/O
Command
Decode
and
Control
Logic
X
DEC
EEPROM
Array
512 x 8
Y Decode
Data Register
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Characteristics subject to change without notice.
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X84041
PIN NAMES
Write Enable (WE)
I/O
Data Input/Output
CE
Chip Enable Input
OE
Output Enable Input
WE
Write Enable Input
WP
Write Protect Input
VCC
Supply Voltage
VSS
Ground
NC
No Connect
The Write Enable input must be LOW to write either
data or command sequences to the X84041.
Data In/Data Out (I/O)
Data and command sequences are serially written to
or serially read from the X84041 through the I/O pin.
Write Protect (WP)
When the Write Protect input is LOW, nonvolatile writes
to the X84041 are disabled. When WP is HIGH, all
functions, including nonvolatile writes, operate normally. If a nonvolatile write cycle is in progress, WP
going LOW will have no effect on the cycle already
underway, but will inhibit any additional nonvolatile
write cycles.
PIN CONFIGURATION
DIP/SOIC
CE
I/O
1
2
WP
VSS
3
4
X8401
8
7
6
5
VCC
NC
OE
WE
DEVICE OPERATION
The X84041 is a serial 512 x 8 bit EEPROM designed
to interface directly with most microprocessor buses.
Standard CE, OE, and WE signals control the read and
write operations, and a single l/O line is used to send
and receive data and commands serially.
TSSOP
CE
I/O
1
NC
3
X8401 11
4
10
5
9
6
NC
NC
WP
VSS
2
7
14
13
12
8
VCC
NC
NC
NC
NC
Data Timing
Data input on the l/O line is latched on the rising edge
of either WE or CE, whichever occurs first. Data output
on the l/O line is active whenever both OE and CE are
LOW. Care should be taken to ensure that WE and OE
are never both LOW while CE is LOW.
OE
WE
A Write Protect (WP) pin provides hardware protection
against inadvertent writes to the memory.
Xicor EEPROMs are designed and tested for applications requiring extended endurance. Inherent data
retention is greater than 100 years.
PIN DESCRIPTIONS
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, the chip is deselected, the I/O pin is in the high impedance state, and
unless a nonvolatile write operation is underway, the
X84041 is in the standby power mode.
Output Enable (OE)
The Output Enable input must be LOW to enable the
output buffer and to read data from the X84041 on the
I/O line.
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Read Sequence
A read sequence consists of sending a 16-bit address
followed by the reading of data serially. The address is
written by issuing 16 separate write cycles (WE and
CE LOW, OE HIGH) to the part without a read cycle
between the write cycles. The address is sent serially,
most significant bit first, over the I/O line. Note that this
sequence is fully static, with no special timing restrictions, and the processor is free to perform other tasks
on the bus whenever the X84041 CE pin is HIGH.
Once the 16 address bits are sent, a byte of data can
be read on the I/O line by issuing 8 separate read
cycles (OE and CE LOW, WE HIGH). At this point,
issuing a reset sequence will terminate the read
sequence, otherwise the X84041 will await further
reads in the sequential read mode.
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Characteristics subject to change without notice.
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X84041
Sequential Read
The byte address is automatically incremented to the
next higher address after each byte of data is read.
The data stored in the memory at the next address can
be read sequentially by continuing to issue read
cycles. When the highest address is reached ($1FF),
the address counter rolls over to address $000 and
reading may be continued indefinitely.
Reset Sequence
The reset sequence resets the X84041 and sets an
internal write enable latch. A reset sequence can be
sent at any time by performing a read/write “0”/read
sequence (see Figs. 1 and 2). This sequence breaks
the multiple read or write cycle sequences that are normally used when reading from or writing to the part.
This sequence can be used at any time to interrupt or
end a sequential read or page load. As soon as the
write “0” cycle is complete, the part is reset (unless a
nonvolatile write cycle is in progress). The second read
cycle in this sequence, and any further read cycles, will
read a HIGH on the l/O pin until a valid read sequence
is issued. The reset sequence must be issued at the
beginning of both read and write sequences to be sure
the X84041 initiates these operations properly.
Figure 1. Read Sequence
CE
OE
WE
I/O (IN)
"0"
X
X
X
X
X
X
X A8
A7 A6 A5 A4 A3 A2 A1 A0
I/O (OUT)
D7 D6 D5 D4 D3 D2 D1 D0
RESET
Load Address
Write Sequence
A nonvolatile write sequence consists of sending a
reset sequence, a 16-bit address (the first 7 of which
are don’t cares), up to 8 bytes of data, and then a special “start nonvolatile write cycle” command sequence.
The reset sequence is issued first (as described in the
Reset Sequence section) to set the internal write
enable latch. The address is written serially by issuing
16 separate write cycles (WE and CE LOW, OE HIGH)
to the part without any read cycles between the writes.
The address is sent serially, most significant bit first, on
the l/O pin. Up to eight bytes of data are written by
issuing either 8, 16, 24, 32, 40, 48, 56, or 64 separate
write cycles. Again, no read cycles are allowed
between writes. The nonvolatile write cycle is initiated
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Read Data
by issuing a special read/write “1”/read sequence. The
first read cycle ends the page load, then the write “1”
followed by a read starts the nonvolatile write cycle.
The X84041 recognizes 8-byte pages beginning at
addresses XXXXXX000. When sending data to the
part, attempts to exceed the upper address of the page
will result in the address counter “wrapping-around” to
the first address on the page, where data loading can
continue. For this reason, sending more than 64 consecutive data bits will result in overwriting previous
data. A nonvolatile write cycle will not start if a partial
or incomplete write sequence is issued. The internal
write enable latch is reset when the nonvolatile write
cycle is completed to prevent inadvertent writes. Note
that this sequence is fully static, with no special timing
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Characteristics subject to change without notice.
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X84041
restrictions. The processor is free to perform other
tasks on the bus whenever the chip enable pin (CE) is
HIGH.
Nonvolatile Write Status
The status of a nonvolatile write cycle can be determined at any time by simply reading the state of the l/O
pin on the X84041. This pin is read when OE and CE
are LOW and WE is HIGH. During a nonvolatile write
cycle the l/O pin is LOW. When the nonvolatile write
cycle is complete, the l/O pin goes HIGH. A reset
sequence can also be issued during a nonvolatile write
cycle with the same result: I/O is LOW as long as a
nonvolatile write cycle is in progress, and l/O is HIGH
when the nonvolatile write cycle is done.
Figure 2. Write Sequence
CE
OE
WE
I/O (IN)
"0"
X
X
X
X
X
X
X A8
A7 A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
"1"
"0"
I/O (OUT)
RESET
Load Address
Write Protection
The following circuitry has been included to prevent
inadvertent nonvolatile writes:
Load Data
SYMBOL TABLE
WAVEFORM
– The internal Write Enable latch is reset upon power-up.
– A reset sequence must be issued to set the internal
write enable latch before starting a write sequence.
– A special “start nonvolatile write” command sequence
is required to start a nonvolatile write cycle.
– The internal Write Enable latch is reset automatically
at the end of a nonvolatile write cycle.
– The internal Write Enable latch is reset and remains
reset as long as the WP pin is LOW, which blocks all
nonvolatile write cycles.
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START
Nonvolatile
Write
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INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW to
HIGH
Will change
from LOW to
HIGH
May change
from HIGH to
LOW
Will change
from HIGH to
LOW
Don’t Care:
Changes
Allowed
N/A
Changing:
State Not
Known
Center Line
is High
Impedance
Characteristics subject to change without notice.
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X84041
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias ................... –65°C to +135°C
Storage temperature ........................ –65°C to +150°C
Terminal voltage with respect to VSS ..........–1V to +7V
DC output current ................................................. 5mA
Lead temperature (soldering, 10 seconds)........ 300°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; the functional operation of the
device at these or any other conditions (above those indicated in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature
Min.
Max.
Supply Voltage
Limits
Commercial
0°C
+70°C
X84041
5V ±10%
Industrial
–40°C
+85°C
X84041-3
3V ±10%
†
2.7V to 5.5V
X84041-2.7
† Contact
factory for availability
D.C. OPERATING CHARACTERISTICS (VCC = 5V ±10%)
(Over the recommended operating conditions, unless otherwise specified.)
Limits
Symbol
Parameter
ICC1
Min.
Max.
Unit
Test Conditions
VCC supply current (read)
1
mA
OE = VIL, WE = VIH, I/O = Open, CE clocking
@ 2MHz
ICC2
VCC supply current (write)
3
mA
ICC during nonvolatile write cycle all inputs at
CMOS levels
ISB
VCC standby current
50
µA
CE = VCC, other inputs = VCC or VSS
VCC = 5V ±10%
ILI
Input leakage current
10
µA
VIN = VSS to VCC
ILO
Output leakage current
10
µA
VOUT = VSS to VCC
(1)
Input LOW voltage
–1
VCC x 0.3
V
(1)
VIH
Input HIGH voltage
VCC x 0.7
VCC + 0.5
V
VOL
Output LOW voltage
0.4
V
IOL = 2.1mA, VCC = 5V ±10%
VOH
Output HIGH voltage
V
IOH = –1mA, VCC = 5V ±10%
VlL
Note:
VCC – 0.8
(1) VIL min. and VIH max. are for reference only and are not tested.
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Characteristics subject to change without notice.
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X84041
D.C. OPERATING CHARACTERISTICS (VCC = 3V ±10%)
(Over the recommended operating conditions, unless otherwise specified.)
Limits
Symbol
Parameter
ICC1
Max.
Unit
Test Conditions
VCC supply current (read)
250
µA
OE = VIL, WE = VIH, I/O = Open, CE clocking
@ 2MHz
ICC2
VCC supply current (write)
1
mA
ICC during nonvolatile write cycle All inputs at
CMOS levels
ISB1
VCC standby current
10
µA
CE = VCC, Other inputs = VCC or VSS,
VCC = 3V ±10%
ILI
Input leakage current
10
µA
VIN = VSS to VCC
ILO
Output leakage current
10
µA
VOUT = VSS to VCC
VCC x 0.3
V
VCC x 0.7 VCC + 0.5
V
(1)
Input low voltage
(1)
VIH
Input high voltage
VOL
Output low voltage
VOH
Output high voltage
VlL
Note:
Min.
–1
0.4
VCC – 0.4
V
IOL = 1mA, VCC = 3V ±10%
V
IOH = –400µA, VCC = 3V ±10%
(1) VIL min. and VIH max. are for reference only and are not tested.
CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V
Symbol
(2)
(2)
CI/O
CIN
Parameter
Max.
Unit
Test Conditions
Input/Output capacitance
8
pF
VI/O = 0V
Input capacitance
6
pF
VIN = 0V
POWER-UP TIMING
Symbol
(3)
(3)
tPUR
tPUW
Note:
Parameter
Max.
Unit
Power-up to read operation
2
ms
Power-up to write operation
5
ms
(3) Time delays required from the time the VCC is stable until the specific operation can be initiated. Periodically sampled, but not 100%
tested.
A.C. CONDITIONS OF TEST
EQUIVALENT A.C. LOAD CIRCUITS
Input pulse levels
VCC x 0.1 to VCC x 0.9
Input rise and fall times
5ns
Input and output timing levels
VCC x 0.5
5V
2.06KΩ
Output
3.03KΩ
REV 1.0 6/29/00
3V
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2.39KΩ
Output
30pF
4.58KΩ
Characteristics subject to change without notice.
30pF
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X84041
A.C. CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.)
Read Cycle Limits—X84041
Symbol
Parameter
tRC
Read cycle time
tCE
CE access time
tOE
OE access time
VCC = 5V ±10%
VCC = 3V ±10%
Min.
Min.
Max.
300
Max.
300
Unit
ns
45
45
65
ns
65
ns
tLOW
CE LOW time
70
70
ns
tHIGH
CE HIGH time
70
70
ns
(4)
CE LOW to output In low Z
0
0
ns
(4)
tLZ
CE HIGH to output In high Z
0
(4)
OE LOW to output In low Z
0
(4)
OE HIGH to output In high Z
0
Output hold from CE or OE HIGH
0
tHZ
tOLZ
tOHZ
tOH
30
0
35
0
30
ns
ns
0
35
ns
0
ns
tWES
WE HIGH setup time
25
25
ns
tWEH
WE HIGH hold time
25
25
ns
Note:
(4) Periodically sampled, but not 100% tested. tHZ and tOHZ are measured from the point where CE or OE goes HIGH (whichever
occurs first) to the time when I/O is no longer being driven into a 5pF load.
Read Cycle
tRC
tLOW
tHIGH
tCE
CE
WE
tWES
tOE
OE
tWEH
tOHZ
I/O
tOLZ
tLZ
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HIGH Z
Data
tOH
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tHZ
Characteristics subject to change without notice.
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X84041
Write Cycle Limits—X84041
Symbol
(5)
tNVWC
Parameter
VCC = 5V ±10%
VCC = 3V ±10%
Min.
Min.
Nonvolatile write cycle time
Max.
10
Max.
Unit
10
ms
tWC
Write cycle time
300
300
ns
tWP
WE pulse width
30
30
ns
WE HIGH recovery time
200
200
ns
tWPH
tCS
Write setup time
0
0
ns
tCH
Write hold time
0
0
ns
tCP
CE pulse width
30
30
ns
tCPH
CE HIGH recovery time
200
200
ns
tOES
OE HIGH setup time
50
50
ns
tOEH
OE HIGH hold time
50
50
ns
(6)
Data setup time
30
30
ns
(6)
Data hold time
5
5
ns
tDS
tDH
(7)
WP HIGH before CE
500
500
ns
(7)
WP HIGH after CE
500
500
ns
(7)
WP HIGH before WE
(7)
WP HIGH after WE
tWPCS
tWPCH
tWPWS
tWPWH
500
500
500
500
ns
ns
Notes: (5) tNVWC is the time from the falling edge of OE or CE (whichever occurs last) of the second read cycle in the “start nonvolatile write
cycle” sequence until the self-timed, internal nonvolatile write cycle is completed.
(6) Data is latched into the X84041 on the rising edge of CE or WE, whichever occurs first.
(7) Periodically sampled, but not 100% tested.
CE Controlled Write Cycle
tCPH
tCP
CE
tOES
tOEH
OE
tCS
WE
WP
tCH
tWP
tWPCS
tWPH
tWPCH
tDS
I/O
tDH
HIGH Z
Data
tWC
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Characteristics subject to change without notice.
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X84041
WE Controlled Write Cycle
tCPH
tCP
CE
tOES
tCS
OE
WE
tCH
tOEH
tWPH
tWP
tWPWH
WP
tWPWS
tDS
I/O
tDH
HIGH Z
Data
tWC
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Characteristics subject to change without notice.
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X84041
PACKAGING INFORMATION
8-Lead Plastic Dual In-Line Package Type P
0.430 (10.92)
0.360 (9.14)
0.260 (6.60)
0.240 (6.10)
Pin 1 Index
Pin 1
0.300
(7.62) Ref.
Half Shoulder Width On
All End Pins Optional
0.145 (3.68)
0.128 (3.25)
Seating
Plane
0.025 (0.64)
0.015 (0.38)
0.065 (1.65)
0.045 (1.14)
0.150 (3.81)
0.125 (3.18)
0.110 (2.79)
0.090 (2.29)
.073 (1.84)
Max.
0.060 (1.52)
0.020 (0.51)
0.020 (0.51)
0.016 (0.41)
0.325 (8.25)
0.300 (7.62)
0°
15°
Typ. 0.010 (0.25)
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
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Characteristics subject to change without notice.
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X84041
PACKAGING INFORMATION
8-Lead Plastic Small Outline Gull Wing Package Type S
0.150 (3.80) 0.228 (5.80)
0.158 (4.00) 0.244 (6.20)
Pin 1 Index
Pin 1
0.014 (0.35)
0.019 (0.49)
0.188 (4.78)
0.197 (5.00)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.010 (0.25)
0.050 (1.27)
0.010 (0.25)
X 45°
0.020 (0.50)
0.050" Typical
0.050"
Typical
0° - 8°
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.410)
0.037 (0.937)
0.030"
Typical
8 Places
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
REV 1.0 6/29/00
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Characteristics subject to change without notice.
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X84041
PACKAGING INFORMATION
14-Lead Plastic, TSSOP, Package Type V
.025 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.193 (4.9)
.200 (5.1)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
0° - 8°
Seating Plane
.019 (.50)
.029 (.75)
Detail A (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
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Characteristics subject to change without notice.
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X84041
Ordering Information
X84041
X
X
-X
VCC Range
Blank = 4.5V to 5.5V
3 = 2.7V to 3.3V
2.7 = 2.7V to 5.5V
Device
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
Package
P = 8-Lead plastic DIP
S = 8-Lead SOIC
V = 14-Lead TSSOP
Part Mark Convention
8-Lead PDIP
8-Lead SOIC
X84041P
X84041
MYYWWES X
Blank = 4.5V to 5.5V, 0°C to + 70°C
F = 2.7V to 5.5V, 0°C to + 70°C
D = 2.7V to 3.3V, 0°C to + 70°C
I = 4.5V to 5.5V, 40°C to + 85°C
G = 2.7V to 5.5V, 40°C to + 85°C
E = 2.7V to 3.3V, 40°C to + 85°C
EYWW
8-Lead TSSOP
84041
X
Blank = 4.5V to 5.5V, 0°C to + 70°C
F= 2.7V to 5.5V, 0°C to + 70°C
D = 2.7V to 3.3V, 0°C to + 70°C
I = 4.5V to 5.5V, 40°C to + 85°C
G = 2.7V to 5.5V, 40°C to + 85°C
E = 2.7V to 3.3V, 40°C to + 85°C
LIMITED WARRANTY
EYWW
X
Blank = 4.5V to 5.5V, 0°C to + 70°C
D = 2.7V to 3.3V, 0°C to + 70°C
I = 4.5V to 5.5V, 40°C to + 85°C
E = 2.7V to 3.3V, 40°C to + 85°C
©Xicor, Inc. 2000 Patents Pending
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
REV 1.0 6/29/00
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Characteristics subject to change without notice.
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