DS75325 Memory Drivers General Description The DS75325 is a monolithic memory driver which features high current outputs as well as internal decoding of logic inputs. This circuit is designed for use with magnetic memories. The circuit contains two 600 mA sink-switch pairs and two 600 mA source-switch pairs. Inputs A and B determine source selection while the source strobe (S1) allows the selected source turn on. In the same manner, inputs C and D determine sink selection while the sink strobe (S2) allows the selected sink turn on. Sink-output collectors feature an internal pull-up resistor in parallel with a clamping diode connected to VCC2. This protects the outputs from voltage surges associated with switching inductive loads. The source stage features Node R which allows extreme flexibility in source current selection by controlling the amount of base drive to each source transistor. This method of setting the base drive brings the power associated with the resistor outside the package thereby allowing the circuit to operate at higher source currents for a given junction temperature. If this method of source current setting is not desired, then Nodes R and RINT can be shorted externally, activating an internal resistor connected from VCC2 to Node R. This provides adequate base drive for source currents up to 375 mA with VCC2 e 15V or 600 mA with VCC2 e 24V. Connection Diagram Truth Table Dual-In-Line Package Features Y Y Y Y Y Y Y 600 mA output capability 24V output capability Dual sink and dual source outputs Fast switching times Source base drive externally adjustable Input clamping diodes TTL compatible Address Inputs Source Sink A B C D L H X X H L X X X X L H X X H L X X X X H H H H Strobe Inputs Source Sink S1 S2 L H L H H L H L H H X X Outputs Source Sink W X Y Z ON OFF OFF OFF OFF ON OFF OFF OFF OFF ON OFF OFF OFF OFF ON OFF OFF OFF OFF OFF OFF OFF OFF H e High Level, L e Low Level, X e Irrelevant Note: Not more than one output is to be on at any one time. TL/F/9755 – 2 Top View Order Number DS75325N See NS Package Number N14A C1995 National Semiconductor Corporation TL/F/9755 RRD-B30M115/Printed in U. S. A. DS75325 Memory Drivers June 1992 Absolute Maximum Ratings (Note 1) Storage Temperature Range If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage VCC1 (Note 5) Supply Voltage VCC2 (Note 5) Input Voltage (Any Address or Strobe Input) Maximum Power Dissipation* at 25§ C Cavity Package Molded Package b 65§ C to a 150§ C Lead Temperature (Soldering, 10 seconds) 7V 25V 5.5V 300§ C Operating Conditions Temperature (TA) DS75325 1509 mW 1476 mW Min Max Units 0 a 70 §C *Derate Cavity Package 10.1 mW/§ C above 25§ C; derate molded package 11.8 mW/§ C above 25§ C. Electrical Characteristics (Notes 2 and 3) Symbol Parameter Conditions VIH High Level Input Voltage (Figures 1 and 2) VIL Low Level Input Voltage (Figures 3 and 4) VI Input Clamp Voltage VCC1 e 4.5V, VCC2 e 24V, IIN e b12 mA TA e 25§ C (Figure 5) Source Collectors Terminal ‘‘Off’’ State Current VCC1 e 4.5V, VCC2 e 24V IOFF Min Full Range (Figure 1) TA e 25§ C b 1.7 V 500 mA mA DS55325 3 150 mA DS75325 3 200 mA VCC1 e 4.5V, VCC2 e 24V, IOUT e 0 mA (Figure 2) VCC1 e 4.5V, VCC2 e 15V, RL e 24X, ISOURCE & b600 mA (Figure 3) (Notes 4 and 6) IIL V 200 Saturation Voltage Source Outputs IIH 0.8 DS55325 High Level Sink Output Voltage II Units DS75325 VSAT Saturation Voltage Sink Outputs Max VCC1 e 4.5V, VCC2 e 15V, RL e 24X, ISINK & 600 mA (Figure 4) (Notes 4 and 6) V b 1.3 VOH VSAT Typ 2 19 23 Full Range TA e 25§ C 0.9 V DS55325 0.43 0.7 V DS75325 0.43 0.75 V 0.9 V Full Range TA e 25§ C V DS55325 0.43 0.7 V DS75325 0.43 0.75 V Input Current at Maximum Input Voltage VCC1 e 5.5V, VCC2 e 24V, VI e 5.5V (Figure 5) Address Inputs 1 mA Strobe Inputs 2 mA High Level Input Current VCC1 e 5.5V, VCC2 e 24V, VI e 2.4V (Figure 5) Address Inputs 3 40 mA Strobe Inputs 6 80 mA Address Inputs b1 b 1.6 mA Strobe Inputs b2 b 3.2 mA VCC1 14 22 mA VCC2 7.5 20 mA Low Level Input Current VCC1 e 5.5V, VCC2 e 24V, VI e 0.4V (Figure 5) Supply Current, All Sources and Sinks ‘‘Off’’ VCC1 e 5.5V, VCC2 e 24V, TA e 25§ C (Figure 6) ICC1 Supply Current from VCC1, Either Sink ‘‘On’’ VCC1 e 5.5V, VCC2 e 24V, ISINK e 50 mA, TA e 25§ C (Figure 7) 55 70 mA ICC2 Supply Current from VCC2, Either Source ‘‘On’’ VCC1 e 5.5V, VCC2 e 24V, ISOURCE e b50 mA TA e 25§ C (Figure 8) 32 50 mA ICC OFF Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation. Note 2: Unless otherwise specified min/max limits apply across the b 55§ C to a 125§ C temperature range for the DS55325 and across the 0§ C to a 70§ C range for the DS75325. All typical values are at TA e 25§ C. Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown as max or min on absolute value basis. Note 4: Only one output at a time should be shorted. Note 5: Voltage values are with respect to network ground terminal. Note 6: These parameters must be measured using pulse techniques. tW e 200 ms, duty cycle s 2%. 2 Switching Characteristics VCC1 e 5V, TA e 25§ C Symbol tPLH Parameter Conditions Typ Max Units Source Collectors 25 50 ns Sink Outputs 20 45 ns VCC2 e 15V, RL e 24X, CL e 25 pF (Figure 9) Source Collectors 25 50 ns Sink Outputs 20 45 ns CL e 25 pF Source Outputs, VCC2 e 20V, RL e 1 kX (Figure 10) 55 Sink Outputs, VCC2 e 15V, RL e 24X (Figure 9) 7 Source Outputs, VCC2 e 20V, RL e 1 kX (Figure 10) 7 Sink Outputs, VCC2 e 15V, RL e 24X (Figure 9) 9 20 ns 15 30 ns Propagation Delay Time, Low-to-High Level Output VCC2 e 15V, RL e 24X, CL e 25 pF (Figure 9) tPHL Propagation Delay Time, High-to-Low Level Output tTLH Transition Time, Low-to-High Level Output tTHL tS Transition Time, High-to-Low Level Output Storage Time, Sink Outputs CL e 25 pF VCC2 e 15V, RL e 24X, CL e 25 pF (Figure 9) Min DC Test Circuits TL/F/9755 – 3 Test Table A B GND GND 2V 2V S1 2V GND FIGURE 1. IOFF 3 ns 15 ns ns DC Test Circuits (Continued) Test Table C D S2 Y Z 2V 4.5V GND VOH OPEN GND 4.5V 2V VOH OPEN 4.5V 2V GND OPEN VOH 4.5V GND 2V OPEN VOH A B S1 0.8V 4.5V 4.5V 0.8V TL/F/9755 – 4 FIGURE 2. VIH and VOH Test Table W X 0.8V GND OPEN 0.8V OPEN GND TL/F/9755 – 5 Note 1: Figure 3 and 4 parameters must be measured using pulse techniques, tW e 200 ms, duty cycle s 2%. FIGURE 3. VIL and Source VSAT 4 DC Test Circuits (Continued) TL/F/9755 – 6 Note 1: Figure 3 and 4 parameters must be measured using pulse techniques, tW e 200 ms, duty cycle s 2%. Test Table C D S2 Y Z 0.8V 4.5V 0.8V RL OPEN 4.5V 0.8V 0.8V OPEN RL FIGURE 4. VIL and Sink VSAT 5 DC Test Circuits (Continued) TL/F/9755 – 7 Test Tables II, IIH Apply VI e 5.5V Measure II Ground VI, IIL Apply VI e 0.4V Measure IIL Apply 5.5V Apply VI e 2.4V Measure IIH Apply 5.5V Apply II e b10 mA Measure VI A S1 B, C, S2, D A S1 B S1, B, C, S2, D A, B C, S2, D S1 A, B, C, S2, D S1 A, C, S2, D B A, S1, C, S2, D C S2 A, S1, B, D C A, S1, B, S2, D S2 C, D A, S1, B S2 A, S1, B, C, D D S2 A, S1, B, C D A, S1, B, C, S2 FIGURE 5. VI, II, IIH and IIL 6 DC Test Circuits (Continued) TL/F/9755 – 8 FIGURE 6. ICC1 (OFF) and ICC2 (OFF) 7 DC Test Circuits (Continued) TL/F/9755 – 9 Test Table C D S2 Y Z GND 5V 5V GND GND ISINK OPEN GND OPEN ISINK FIGURE 7. ICC1, Either Sink On 8 DC Test Circuits (Continued) TL/F/9755 – 10 Test Table A B S1 GND 5V GND 5V GND GND FIGURE 8. ICC2, Either Source On 9 DC Test Circuits (Continued) TL/F/9755 – 11 Note 1: The pulse generator has the following characteristics: ZOUT e 50X, duty cycle s 1%. Note 2: CL includes probe and jig capacitance. Voltage Waveforms TL/F/9755 – 12 Test Table Parameter tPLH and tPHL tPLH, tPHL, tTLH, tTHL and tS Output Under Test Source Collectors Input Connect to 5V A and S1 B, C, D and S2 B and S1 A, C, D and S2 Sink Output Y C and S2 A, B, D and S1 Sink Output Z D and S2 A, B, C and S1 FIGURE 9. Switching Times 10 DC Test Circuits (Continued) TL/F/9755 – 13 Note 1: The pulse generator has the following characteristics: ZOUT e 50X, duty cycle s 1%. Note 2: CL includes probe and jig capacitance. Voltage Waveforms TL/F/9755 – 14 Test Table Parameter tTLH and tTHL Input Connect to 5V Source Output W Output Under Test A and S1 B, C, D and S2 Source Output X B and S1 A, C, D and S2 FIGURE 10. Transition Times of Source Outputs 11 Schematic Diagram TL/F/9755 – 1 12 Applications After solving for Rext, the magnitude of the source collector current (ICS) is determined from Equation 3. ICS & 0.94 IL (3) where: ICS is in mA. As an example, let VCC2(Min) e 20V and VL e 3V while IL of 500 mA flows. Using Equation 1: 16 (20 b 3 b 2.2) e 0.5 kX Rext e 500 b 1.6 (20 b 3 b 2.9) EXTERNAL RESISTOR CALCULATION A typical magnetic-memory word drive requirement is shown in Figure 11 . A source-output transistor of one DS75325 delivers load current (IL). The sink-output transistor of another DS75325 sinks this current. The value of the external pull-up resistor (Rext) for a particular memory application may be determined using the following equation: 16 [VCC2(Min) b VS b 2.2] Rext e (1) IL b1.6 [VCC2(Min) b VS b 2.9] and from Equation 2: where: Rext is in kX, VCC2(Min) is the lowest expected value of VCC2 in volts, VS is the source output voltage in volts with respect to ground, IL is in mA. The power dissipated in resistor Rext during the load current pulse duration is calculated using Equation 2. IL [VCC2(Min) b VS b 2] PRext & 16 where: PRext is in mW. PRext & 500 [20 b 3 b 2] & 470 mW 16 The amount of the memory system current source (ICS) from Equation 3 is: ICS & 0.94 (500) & 470 mA In this example the regulated source-output transistor base current through the external pull-up resistor (Rext) and the source gate is approximately 30 mA. This current and ICS comprise IL. (2) TL/F/9755 – 15 Note 1: For clarity, partial logic diagrams of two DS55325s are shown. Note 2: Source and sink shown are in different packages. FIGURE 11. Typical Application Data 13 DS75325 Memory Drivers Physical Dimensions inches (millimeters) (Continued) Molded Dual-In-Line Package (N) Order Number DS75325N NS Package Number N14A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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