ETC ARM966E-S?(CW001105)

CW001105 - 200 MHz
Synthesized ARM966E-S Core
The CW001105 processor core is a 200 MHz implementation of the popular
ARM966E-S™, synthesized onto LSI Logic’s G12P 0.18 micron high performance
process technology.
• 200 MHz Operating frequency
The ARM966E-S, which is based on the five stage pipeline ARM9E-S™
Harvard architecture processor, also contains a complete memory subsystem of
tightly coupled instruction and data RAMs, an Embedded Trace Macrocell
(ETM) interface, and an AMBA™ (Advanced Microprocessor Bus Architecture)
AHB (Advanced High performance Bus) interface unit. This high level of integration helps ease the task of integrating the core into your System on Chip
(SoC) design. Tight coupling of the RAM allows for high speed operation and
predictable memory timing. This makes the core an ideal choice for real time
systems needing timing critical execution. The instruction and data RAM sizes
are user configurable up to 512 KBytes. The AHB interface includes a write
buffer capable of burst transfers and split transactions. The ETM interface, when
used with the optional ETM core, provides extensive real-time trace capabilities.
Tj =115 C, Vdd =1.8 V, slow process
• Implemented on LSI Logic’s G12P
0.18 micron, 1.8 V process
• 0.9mW/MHz power dissipation,
(excluding memories)
• ARM966E-S Industry Standard
• Fully configurable memory subsystem
for maximum flexibility
• Synthesized core for optimal timing
accuracy and ASIC compatible
design flow
• Complete AMBA subsystem
reference design available
• Extensive portfolio of AMBA
ETM (Embedded Trace Macrocell)
• Regional ARM CoreWare design
RAM Control
Data RAM
Write Buffer and AHB Interface
ARM966E-S™ Block Diagram
200 MHz ARM966E-S Synthesized Core
The ARM966E-S supports the ARMv5TE instruction set including all of the
ARM9E-S family DSP instruction extensions. The core supports both the ARM®
32-bit and Thumb® 16-bit instruction sets, making it upwardly code-compatible
with both the ARM7TDMI™ and ARM9TDMI™ families. The ability to switch on
the fly between ARM and Thumb instruction sets allows the user to trade
between high performance and code density.
The built in AMBA bus interface of the ARM966E-S core is an ideal standard
bus for building a complete CPU subsystem design. LSI Logic offers both an
AMBA subsystem reference design, and a library of popular AMBA CPU
peripherals for use by customers on SoC designs. Customers can also
incorporate their own AMBA-based blocks onto this widely used industry
standard bus.
The ARM966E-S is supported by a wide array of software development
tools available from ARM Limited as well as third party vendors.
For more information please call:
LSI Logic Corporation
North American Headquarters
Milpitas, CA
Tel: 800 574 4286
LSI Logic Europe Ltd.
European Headquarters
United Kingdom
Tel: 44 1344 426544
Fax: 44 1344 481039
LSI Logic KK Headquarters
Tokyo, Japan
Tel: 81 3 5463 7165
Fax: 81 3 5463 7820
LSI Logic web site:
The core is implemented in LSI Logic’s G12P high performance 0.18 micron
(drawn) process, giving a maximum speed of 200 MHz (worst case commercial
conditions) and making it ideal for high performance applications. Power
consumption for the core is 0.9 mW/MHz.
The CW001105 core is synthesized onto the G12P SoC cell library and
is provided complete with highly accurate timing models that fully support
Static Timing Analysis (STA) through the core. This can be a significant benefit
for achieving timing closure on high performance designs. The core is fully
compatible with LSI Logic’s entire FlexStream® SoC ASIC design flow making
it straightforward to integrate into complex customer designs. The core comes
complete with built-in full scan chains for good testability, and is provided
with a comprehensive set of deliverables including design files, STA and
ATPG scripts, and detailed integration guidelines. To further assist customers
with their designs, LSI Logic provides specialized ARM CoreWare® integration
support through our team of regionally based Field CoreWare Engineers.
LSI Logic logo design, CoreWare and FlexStream
are registered trademarks and G12 is a trademark of LSI Logic Corporation. ARM and Thumb
are registered trademarks of ARM Limited.
ARM9TDMI are trademarks of ARM Limited. All
other brand and product names may be trademarks of their respective companies.
LSI Logic Corporation reserves the right to make
changes to any products and services herein at
any time without notice. LSI Logic does not assume
any responsibility or liability arising out of the
application or use of any product or service
described herein, except as expressly agreed to in
writing by LSI Logic; nor does the purchase, lease,
or use of a product or service from LSI Logic convey a license under any patent rights, copyrights,
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property rights of LSI Logic or of third parties.
Copyright ©2001 by LSI Logic Corporation.
All rights reserved.
O rder No. C20042
601.1K.SR.IK - Printed in USA