EDI88257C HI-RELIABILITY PRODUCT 256Kx8 Monolithic SRAM FEATURES ■ 256Kx8 CMOS Static The EDI88257C is a 2 Megabit 256Kx8 bit Monolithic CMOS Static RAM. ■ Random Access Memory The 32 pin DIP pinout adheres to the JEDEC standard for the two megabit device, and is a pin replacement for the 256Kx8 module, EDI88257C. The device is upgradeable to the 512Kx8 SRAM, the EDI88512C. Pin 1 becomes the higher order address. • Access Times of 70, 85, 100ns • Data Retention Function (LP Versions) • TTL Compatible Inputs and Outputs A Low Power version, EDI88257LP, offers a data retention function for battery back-up opperation. Military product is available compliant to Appendix A of MIL-PRF-38535. • Fully Static, No Clocks ■ JEDEC Approved Pinout • 32 pin Ceramic DIP, 0.6 mils wide (Package 9) ■ Single +5V (±10%) Supply Operation FIG. 1 PIN CONFIGURATION PIN DESCRIPTION 32 DIP TOP VIEW NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 AØ DQØ DQ1 DQ2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 VCC 31 A15 30 A17 29 W 28 A13 27 A8 26 A9 25 A11 24 G 23 A10 22 E 21 DQ7 20 DQ6 19 DQ5 18 DQ4 17 DQ3 BLOCK DIAGRAM A0-17 Address Inputs W Write Enable E Chip Enable G Output Enable DQ0-7 Data Inputs/Outputs VCC Power (+5V ±10%) VSS Ground NC Not Connected Memory Array AØ-17 Address Buffer Address Decoder I/O Circuits DQØ-7 W E G September 1999 Rev. 2 1 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com EDI88257C TRUTH TABLE ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss Unit G E W Mode Output Power V X H L X H L L L X H H L Standby Output Deselect Read Write High Z High Z Data Out Data In Icc 2 , Icc 3 Icc 1 Icc 1 Icc 1 -0.5 to 7.0 Operating Temperature TA (Ambient) Industrial -40 to +85 °C Military -55 to +125 °C Storage Temperature, Ceramic -65 to +150 °C Power Dissipation 1 W Output Current 20 mA Junction Temperature, TJ 175 °C RECOMMENDED OPERATING CONDITIONS Parameter NOTE: Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Symbol Min Typ Max Supply Voltage VCC 4.5 5.0 5.5 Unit V Supply Voltage VSS 0 0 0 V Input High Voltage VIH 2.2 — Vcc +0.5 V Input Low Voltage VIL -0.3 — +0.8 V CAPACITANCE Parameter Symbol Condition Max Unit CI VIN = Vcc or Vss, f = 1.0MHz 30 pF CD/Q VOUT = Vcc or Vss, f = 1.0MHz 14 pF Address Lines Data Lines These parameters are sampled, not 100% tested. DC CHARACTERISTICS (VCC = 5V, TA = +25°C) Parameter Symbol Conditions Units Min Typ Max Input Leakage Current ILI VIN = 0V to VCC — — ±10 Output Leakage Current ILO VI/O = 0V to VCC — — ±10 µA Operating Power Supply Current I CC1 W, E = VIL, II/O = 0mA, Min Cycle (70-100ns) — 45 75 mA Standby (TTL) Power Supply Current I CC2 E ≥ VIH, VIN ≤ VIL , VIN ≥ VIH — 3 10 mA I CC3 E ≥ VCC -0.2V VIN ≥ Vcc -0.2V or VIN ≤ 0.2V C — — 5 mA LP — — 1 mA Output Low Voltage VOL IOL = 2.1mA — — 0.4 V Output High Voltage VOH IOH = -1.0mA 2.4 — — V Full Standby Power Supply Current AC TEST CONDITIONS Figure 1 Figure 2 Vcc Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load Vcc 480Ω 480Ω VSS to 3.0V 5ns 1.5V Figure 1 NOTE: For tEHQZ, tGHQZ and tWLQZ, CL = 5pF Figure 2) Q Q 255Ω 30pF 255Ω White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com 5pF 2 µA EDI88257C AC CHARACTERISTICS – READ CYCLE (VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)) Parameter Symbol JEDEC Alt. Min 70ns 85ns Read Cycle Time tAVAV tRC 70 Address Access Time tAVQV tAA 70 85 100 ns Chip Select Access Time tELQV tACS 70 85 100 ns Chip Select to Output in Low Z (1) tELQX tCLZ Chip Disable to Output in High Z (1) tEHQZ tCHZ Output Hold from Address Change tAVQX tOH Max Min 85 10 10 10 tGLQV tOE Output Enable to Output in Low Z (1) tGLQX tOLZ 5 Output Disable to Output in High Z (1) tGHQZ tOHZ 0 Max ns 30 30 10 35 50 5 0 30 0 Max Min ns ns 45 5 Units ns 10 10 25 Min 100 25 Output Enable to Output Valid 100ns Max ns ns 30 ns Max Units 1. This parameter is guaranteed by design but not tested. AC CHARACTERISTICS – WRITE CYCLE (VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C) Parameter Symbol JEDEC Alt. Min 70ns 85ns Write Cycle Time tAVAV tWC 70 85 100 ns Chip Select to End of Write tELWH tELEH tCW tCW 60 60 70 70 80 80 ns ns Address Setup Time tAVWL tAVEL tAS tAS 0 0 0 0 0 0 ns ns Address Valid to End of Write tAVWH tAVEH tAW tAW 65 65 70 70 80 80 ns ns Write Pulse Width tWLWH tWLEH tWP tWP 50 50 55 55 60 60 ns ns Write Recovery Time tWHAX tEHAX tWR tWR 0 0 0 0 0 0 ns ns Data Hold Time tWHDX tEHDX tDH tDH 0 0 0 0 0 0 ns ns Max 25 Min 0 100ns Write to Output in High Z (1) tWLQZ tWHZ 0 Data to Write Time tDVWH tDVEH tDW tDW 40 30 40 35 30 40 40 0 30 ns ns ns Output Active from End of Write (1) tWHQX tWLZ 5 5 5 ns 1. This parameter is guaranteed by design but not tested. 3 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com EDI88257C FIG. 2 TIMING WAVEFORM - READ CYCLE tAVAV A tAVQV E tAVAV A ADDRESS 1 ADDRESS 2 tAVQV tAVQX tELQV tELQX tEHQZ tGLQV tGLQX tGHQZ G Q DATA 1 Q DATA 2 READ CYCLE 2 (W HIGH) READ CYCLE 1 (W HIGH; G, E LOW) FIG. 3 WRITE CYCLE - W CONTROLLED tAVAV A tAVWH tELWH tWHAX E tAVWL tWLWH W tDVWH D tWHDX DATA VALID tWLQZ tWHQX HIGH Z Q WRITE CYCLE 1, W CONTROLLED FIG. 4 WRITE CYCLE - E CONTROLLED tAVAV WS32K32-XHX A tAVEH tELEH tEHAX E tAVEL tWLEH W tDVEH D tEHDX DATA VALID HIGH Z Q WRITE CYCLE 2, E CONTROLLED White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com 4 EDI88257C DATA RETENTION CHARACTERISTICS (EDI88257LP ONLY) (TA = -55°C to +125°C) Characteristic Low Power Version only Sym Conditions Min Typ Max Units Data Retention Voltage VDD VDD = 2.0V 2 – – V Data Retention Quiescent Current ICCDR E ≥ VDD -0.2V – – 185 µA Chip Disable to Data Retention Time TCDR VIN ≥ VDD -0.2V Operation Recovery Time or VIN ≤ 0.2V TR 0 – – ns TAVAV – – ns FIG. 5 DATA RETENTION - E CONTROLLED Data Retention Mode 4.5V Vcc WS32K32-XHX VDD 4.5V tCDR E tR E = VDD -0.2V DATA RETENTION, E CONTROLLED 5 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com EDI88257C PACKAGE 9: 32 PIN SIDEBRAZED CERAMIC DIP (600mils wide) 1.616 1.584 0.175 0.125 0.061 0.017 0.620 0.600 0.060 0.040 Pin 1 Indicator 0.100 TYP 0.020 0.016 0.155 0.115 0.600 NOM 15 x 0.100 = 1.500 ALL DIMENSIONS ARE IN INCHES ORDERING INFORMATION EDI 8 8 257 C X X X WHITE ELECTRONIC DESIGNS SRAM ORGANIZATION, 256Kx8 TECHNOLOGY: C = CMOS Standard Power LP = Low Power ACCESS TIME (ns) PACKAGE TYPE: C = 32 lead Sidebrazed DIP, 600 mil (Package 9) DEVICE GRADE: B = MIL-STD-883 Compliant M = Military Screened -55°C to +125°C I = Industrial -40°C to +85°C C = Commercial 0°C to +70°C White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com 6