LM98714 Three Channel, 16-Bit, 45 MSPS Digital Copier Analog Front End with Integrated CCD/CIS Sensor Timing Generator and LVDS Output General Description The LM98714 is a fully integrated, high performance 16-Bit, 45 MSPS signal processing solution for digital color copiers, scanners, and other image processing applications. Highspeed signal throughput is achieved with an innovative architecture utilizing Correlated Double Sampling (CDS), typically employed with CCD arrays, or Sample and Hold (S/H) inputs (for Contact Image Sensors and CMOS image sensors). The signal paths utilize 8 bit Programmable Gain Amplifiers (PGA), a +/-9-Bit offset correction DAC and independently controlled Digital Black Level correction loops for each input. The PGA and offset DAC are programmed independently allowing unique values of gain and offset for each of the three inputs. The signals are then routed to a 45MHz high performance analog-to-digital converter (ADC). The fully differential processing channel shows exceptional noise immunity, having a very low noise floor of -74dB. The 16-bit ADC has excellent dynamic performance making the LM98714 transparent in the image reproduction chain. Applications n n n n Multi-Function Peripherals Facsimile Equipment Flatbed or Handheld Color Scanners High-speed Document Scanner n n n n Independent Gain/Offset Correction for Each Channel Digital Black Level Correction Loop for Each Channel Programmable Input Clamp Voltage Flexible CCD/CIS Sensor Timing Generator Key Specifications n n n n n n n n n n n n n n n n Maximum Input Level 1.2 or 2.4 Volt Modes (both with + or - polarity option) ADC Resolution 16-Bit ADC Sampling Rate 45 MSPS INL +/- 23 LSB (typ) Channel Sampling Rate 15/22.5/30 MSPS PGA Gain Steps 256 Steps PGA Gain Range 0.7 to 7.84x Analog DAC Resolution +/-9 Bits Analog DAC Range +/-300mV or +/-600mV Digital DAC Resolution +/-6 Bits Digital DAC Range -1024 LSB to + 1008 LSB SNR -74dB (@0dB PGA Gain) Power Dissipation 505mW (LVDS) 610mW (CMOS) Operating Temp 0 to 70˚C Supply Voltage 3.3V Nominal (3.0V to 3.6V range) Features n LVDS/CMOS Outputs n LVDS/CMOS Pixel Rate Input Clock or ADC Input Clock n CDS or S/H Processing for CCD or CIS sensors System Block Diagram 20105370 © 2006 National Semiconductor Corporation DS201053 www.national.com LM98714 - Three Channel, 16-Bit, 45 MSPS Digital Copier Analog Front End with Integrated CCD/CIS Sensor Timing Generator and LVDS Output October 2006 LM98714 LM98714 Overall Chip Block Diagram 20105301 FIGURE 1. Chip Block Diagram www.national.com 2 LM98714 LM98714 Pin Out Diagram 20105302 FIGURE 2. LM98714 Pin Out Diagram 3 www.national.com www.national.com 4 Typical Application Diagram FIGURE 3. Typical Application Diagram 20105373 LM98714 LM98714 Pin Descriptions Pin Name I/O Typ Res Description 1 CLK3 O D PU Configurable sensor control output. 2 CLK2 O D PD Configurable sensor control output. 3 CLK1 O D PU Configurable sensor control output. 4 SH O D PD Sensor - Shift or transfer control signal for CCD and CIS sensors. 5 RESET I D PU Active-low master reset. NC when function not being used. 6 SH_R I D PD 7 SDIO I/O D 8 SCLK I D PD Serial Interface shift register clock. 9 SEN I D PU Active-low chip enable for the Serial Interface. 10 AGND P Analog ground return. 11 VA P Analog power supply. Bypass voltage source with 4.7µF and pin with 0.1µF to AGND. 12 VREFB O A Bottom of ADC reference. Bypass with a 0.1µF capacitor to ground. 13 VREFT O A Top of ADC reference. Bypass with a 0.1µF capacitor to ground. 14 VA P Analog power supply. Bypass voltage source with 4.7µF and pin with 0.1µF to AGND. 15 AGND P Analog ground return. 16 VCLP A Input Clamp Voltage. Normally bypassed with a 0.1µF, and a 4.7µF capacitor to AGND. An external reference voltage may be applied to this pin. 17 VA P Analog power supply. Bypass voltage source with 4.7µF and pin with 0.1µF to AGND. 18 AGND 19 OSR 20 AGND 21 OSG 22 AGND 23 OSB 24 AGND 25 IO External request for an SH pulse. Serial Interface Data Input P Analog ground return. I A Analog input signal. Typically sensor Red output AC-coupled thru a capacitor. P Analog ground return. I A Analog input signal. Typically sensor Green output AC-coupled thru a capacitor. P Analog ground return. A Analog input signal. Typically sensor Blue output AC-coupled thru a capacitor. P Analog ground return. DGND P Digital ground return. 26 VR P Power supply input for internal voltage reference generator. Bypass this supply pin with a 0.1µF capacitor. 27 DVB O P Digital Core Voltage bypass. Not an input. Bypass with 0.1µF capacitor to DGND. 28 INCLK+ I D Clock Input. Non-Inverting input for LVDS clocks or CMOS clock input. CMOS clock is selected when pin 29 is held at DGND, otherwise clock is configured for LVDS operation. 29 INCLK- I D Clock Input. Inverting input for LVDS clocks, connect to DGND for CMOS clock. DOUT7/ O D Bit 7 of the digital video output bus in CMOS Mode, LVDS Frame Clock+ in LVDS Mode. O D Bit 6 of the digital video output bus in CMOS Mode, LVDS Frame Clock- in LVDS Mode. O D Bit 5 of the digital video output bus in CMOS Mode, LVDS Data Out2+ in LVDS Mode. O D Bit 4 of the digital video output bus in CMOS Mode, LVDS Data Out2- in LVDS Mode. O D Bit 3 of the digital video output bus in CMOS Mode, LVDS Data Out1+ in LVDS Mode. O D Bit 2 of the digital video output bus in CMOS Mode, LVDS Data Out1- in LVDS Mode. 30 I TXCLK+ 31 DOUT6/ TXCLK- 32 DOUT5/ TXOUT2+ 33 DOUT4/ TXOUT2- 34 DOUT3/ TXOUT1+ 35 DOUT2/ TXOUT1- 5 www.national.com LM98714 Pin Descriptions Pin 36 Name DOUT1/ I/O (Continued) Typ Res D Bit 1 of the digital video output bus in CMOS Mode, LVDS Data Out0+ in LVDS Mode. O D Bit 0 of the digital video output bus in CMOS Mode, LVDS Data Out0- in LVDS Mode. TXOUT0+ 37 DOUT0/ Description O TXOUT038 DGND P Digital ground return. 39 VD P Power supply for the digital circuits. Bypass this supply pin with 0.1µF capacitor. A single 4.7µF capacitor should be used between the supply and the VD, VR and VC pins. 40 CLKOUT/ CLK10 O D PD Output clock for registering output data when using CMOS outputs, or configurable sensor control output. 41 CLK9 O D PD Configurable sensor control output. 42 CLK8 O D PD Configurable sensor control output. 43 CLK7 O D PD Configurable sensor control output. 44 CLK6 O D PU Configurable sensor control output. 45 CLK5 O D PD Configurable sensor control output. 46 DGND P Digital ground return. 47 VC P Power supply for the sensor control outputs. Bypass this supply pin with 0.1µF capacitor. 48 CLK4 O D PD Configurable sensor control output. (I=Input), (O=Output), (IO=Bi-directional), (P=Power), (D=Digital), (A=Analog), (PU=Pull Up with an internal resistor), (PD=Pull Down with an internal resistor.). www.national.com 6 Thermal Resistance (θJA) (Notes 2, Package Dissipation at TA = 25˚C (Note 4) 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VA,VR,VD,VC) −0.3V to (VA + 0.3V) Voltage on Any Output Pin (execpt DVB and not to exceed 4.2V) −0.3V to (VA + 0.3V) DVB Output Pin Voltage Human Body Model 2500V Machine Model 250V Storage Temperature −65˚C to +150˚C Soldering process must comply with National Semiconductor’s Reflow Temperature Profile specifications. Refer to www.national.com/packaging. (Note 6) 2.0V Input Current at any pin other than Supply Pins (Note 3) ± 25 mA Package Input Current (except Supply Pins) (Note 3) ± 50 mA Maximum Junction Temperature (TA) 1.89W ESD Rating (Note 5) 4.2V Voltage on Any Input Pin (Not to exceed 4.2V) 66˚C/W Operating Ratings (Notes 1, 2) Operating Temperature Range All Supply Voltage 0˚C ≤ TA ≤ +70˚C +3.0V to +3.6V 150˚C Electrical Characteristics The following specifications apply for VA = VD = VR = VC = 3.3V, CL = 10pF, and fINCLK = 15MHz unless otherwise specified. Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25˚C. Symbol Parameter Conditions Min Typ (Note 8) Max Units CMOS Digital Input DC Specifications (RESETb, SH_R, SCLK, SENb) VIH Logical “1” Input Voltage VIL Logical “0” Input Voltage IIH Logical “1” Input Current IIL 2.0 V 0.8 V VIH = VD Logical “0” Input Current RESET 235 SH_R, SCLK 70 µA SEN 130 nA nA VIL = DGND RESET 70 µA SH_R, SCLK 235 nA SEN 70 µA CMOS Digital Output DC Specifications (SH, CLK1 to CLK10, CMOS Data Outputs) VOH Logical “1” Output Voltage IOUT = -0.5mA VOL Logical “0” Output Voltage IOUT = 1.6mA IOS Output Short Circuit Current VOUT = DGND 16 VOUT= VD -20 IOZ CMOS Output TRI-STATE Current 2.95 V 0.25 VOUT = DGND 20 VOUT = VD -25 V mA nA CMOS Digital Input/Output DC Specifications (SDIO) IIH Logical “1” Input Current VIH = VD 90 nA IIL Logical “0” Input Current VIL = DGND 90 nA LVDS/CMOS Clock Receiver DC Specifications (INCLK+ and INCLK- Pins) VIHL VILL Differential LVDS Clock RL = 100W High Threshold Voltage VCM (LVDS Input Common Mode Voltage)= 1.25V Differential LVDS Clock 100 -100 mV mV Low Threshold Voltage 7 www.national.com LM98714 Absolute Maximum Ratings LM98714 Electrical Characteristics (Continued) The following specifications apply for VA = VD = VR = VC = 3.3V, CL = 10pF, and fINCLK = 15MHz unless otherwise specified. Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25˚C. Symbol Parameter Conditions Min VIHC CMOS Clock INCLK- = DGND 2.0 Typ (Note 8) Max Units V High Threshold Voltage VILC CMOS Clock 0.8 V 280 µA -150 µA Low Threshold Voltage IIHL CMOS Clock Input High Current IILC CMOS Clock Input Low Current LVDS Output DC Specifications VOD Differential Output Voltage VOS LVDS Output Offset Voltage IOS Output Short Circuit Current RL = 100Ω 180 328 450 mV 1.17 1.23 1.3 V VOUT = 0V, RL = 100Ω 7.9 mA Power Supply Specifications IA VA Analog Supply Current VA Normal State 60 97 125 mA VA Low Power State 12 23 32 mA 30 64 75 mA 15 47 55 mA (Powerdown) IR VR Digital Supply Current VR Normal State (LVDS Outputs) CMOS Output Data Format ID LVDS Output Data Format with Data Outputs Disabled 47 mA VD Digital Output Driver Supply LVDS Output Data Format 0.05 mA Current CMOS Output Data Format 12 40 mA 0.5 12 mA (ATE Loading of CMOS Outputs > 50pF) IC VC CCD Timing Generator Output Driver Supply Current Typical sensor outputs: SH, CLK1=Φ1A, CLK2=Φ2A, CLK3=ΦB, CLK4=ΦC, CLK5=RS, CLK6=CP (ATE Loading of CMOS Outputs > 50pF) PWR Average Power Dissipation LVDS Output Data Format 350 505 650 mW CMOS Output Data Format 380 610 700 mW (ATE Loading of CMOS Outputs > 50pF) Input Sampling Circuit Specifications VIN www.national.com Input Voltage Level CDS Gain=1x, PGA Gain=1x 2.3 CDS Gain=2x, PGA Gain= 1x 1.22 8 Vp-p (Continued) The following specifications apply for VA = VD = VR = VC = 3.3V, CL = 10pF, and fINCLK = 15MHz unless otherwise specified. Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25˚C. Typ (Note 8) Symbol Parameter Conditions Min Max Units IIN_SH Sample and Hold Mode Source Followers Off 50 70 µA CDS Gain = 1x (-70) (-40) Source Followers Off 75 105 CDS Gain = 2x (-105) (-75) Input Leakage Current OSX = VA (OSX = AGND) µA OSX = VA (OSX = AGND) Source Followers On -200 CDS Gain = 2x -10 200 nA -16 OSX = VA (OSX = AGND) CSH Sample/Hold Mode CDS Gain = 1x 2.5 pF Equivalent Input Capacitance IIN_CDS RCLPIN (see Figure 11) CDS Gain = 2x CDS Mode Source Followers Off Input Leakage Current OSX = VA (OSX = AGND) 4 -300 7 pF 300 nA 50 Ω (-25) CLPIN Switch Resistance 16 (OSX to VCLP Node in Figure 8) VCLP Reference Circuit Specifications VCLP DAC Resolution 4 VCLP DAC Step Size VVCLP VCLP DAC Voltage Min Output Bits 0.16 VCLP Config. Register = V 0.14 0.26 0.43 V 2.38 2.68 2.93 V 1.54 VA / 2 1.73 V 0001 0000b VCLP DAC Voltage Max Output VCLP Config. Register = 0001 1111b Resistor Ladder Enabled VCLP Config. Register = 0010 xxxxb ISC VCLP DAC Short Circuit Output Current VCLP Config. Register = 30 mA 10 Bits 0001 xxxxb Black Level Offset DAC Specifications Resolution Monotonicity Guaranteed by characterization Offset Adjustment Range CDS Gain = 1x Referred to AFE Input Minimum DAC Code = 0x000 -614 Maximum DAC Code = 0x3FF 614 mV CDS Gain = 2x -307 Maximum DAC Code = 0x3FF 307 mV Offset Adjustment Range Minimum DAC Code = 0x000 -16000 -18200 Referred to AFE Output Maximum DAC Code = 0x3FF 16000 18200 DAC LSB Step Size DNL Minimum DAC Code = 0x000 LSB CDS Gain = 1x 1.2 mV Referred to AFE Output (32) (LSB) Differential Non-Linearity -0.95 9 3.25 LSB www.national.com LM98714 Electrical Characteristics LM98714 Electrical Characteristics (Continued) The following specifications apply for VA = VD = VR = VC = 3.3V, CL = 10pF, and fINCLK = 15MHz unless otherwise specified. Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25˚C. Symbol Parameter INL Integral Non-Linearity Conditions Min Typ (Note 8) -3.1 Max Units 2.65 LSB PGA Specifications Gain Resolution 8 Monotonicity Maximum Gain Minimum Gain Bits Guaranteed by characterization CDS Gain = 1x 7.18 7.9 8.77 CDS Gain = 1x 17.1 17.9 18.9 dB CDS Gain = 1x 0.56 0.7 0.82 V/V CDS Gain = 1x -5 -3 -1.72 dB PGA Function V/V Gain (V/V) = (196/(280-PGA Code)) Gain (dB) = 20LOG10(196/(280-PGA Code)) Channel Matching Minimum PGA Gain 3 Maximum PGA Gain 12.7 % ADC Specifications VREFT Top of Reference VREFB Bottom of Reference VREFT VREFB Differential Reference Voltage 2.07 V 0.89 1.07 1.18 Overrange Output Code 65535 Underrange Output Code 0 V 1.29 V Digital Offset “DAC” Specifications 7 Bits Digital Offset DAC LSB Step Size Resolution Referred to AFE Output 16 LSB Offset Adjustment Range Min DAC Code =7b0000000 -1024 Referred to AFE Output Mid DAC Code =7b1000000 0 Max DAC Code = 7b1111111 1008 LSB Full Channel Performance Specifications DNL Differential Non-Linearity -0.99 0.8/-0.6 2.55 LSB INL Integral Non-Linearity -73 +/-23 78 LSB SNR Total Output Noise Minimum PGA Gain PGA Gain = 1x -79 dB 7.2 LSB RMS -74 13 Maximum PGA Gain Channel to Channel Crosstalk dB 30 LSB RMS -56 dB 104 LSB RMS Mode 3 47 Mode 2 16 LSB Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the Operating Ratings is not recommended. Note 2: All voltages are measured with respect to AGND = DGND = 0V, unless otherwise specified. Note 3: When the input voltage (VIN) at any pin exceeds the power supplies (VIN < GND or VIN > VA or VD), the current at that pin should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can simultaneously safely exceed the power supplies with an input current of 25 mA to two. www.national.com 10 Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through 0Ω. Note 6: Reflow temperature profiles are different for lead-free and non-lead-free packages. Note 7: The analog inputs are protected as shown below. Input voltage magnitudes beyond the supply rails will not damage the device, provided the current is limited per note 3. However, input errors will be generated If the input goes above VA and below AGND. 20105371 Note 8: Typical figures are at TA = 25˚C, and represent most likely parametric norms at the time of product characterization. The typical specifications are not guaranteed. 11 www.national.com LM98714 Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA and the ambient temperature, TA. The maximum allowable power dissipation at any temperature is PD = (TJMAX – TA)/θJA. The values for maximum power dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Such conditions should always be avoided. LM98714 - Three Channel, 16-Bit, 45 MSPS Digital Copier Analog Front End with Integrated CCD/CIS Sensor Timing Generator and LVDS Output Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead TSSOP NS Package Number MTD48 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. 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