ETC AT49SN3208(T)

Features
• 64-megabit (4M x 16) and 32-megabit (2M x 16) Flash Memories
• 1.65V - 1.95V Read/Write
• High Performance
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– Random Access Time – 90 ns
– Page Mode Read Time – 20 ns
– Synchronous Burst Frequency – 54 MHz
– Configurable Burst Operation
Sector Erase Architecture
– Eight 4K Word Sectors with Individual Write Lockout
– 32K Word Main Sectors with Individual Write Lockout
Typical Sector Erase Time: 32K Word Sectors – 500 ms; 4K Word Sectors – 100 ms
32M, Dual Plane Organization, Permitting Concurrent Read while Program/Erase
– Memory Plane A: 25% of Memory Including Eight 4K Word Sectors
– Memory Plane B: 75% of Memory Consisting of 32K Word Sectors
64M, Four Plane Organization, Permitting Concurrent Read in Any of the Three
Planes not Being Programmed/Erased
– Memory Plane A: 25% of Memory Including Eight 4K Word Sectors
– Memory Plane B: 25% of Memory Consisting of 32K Word Sectors
– Memory Plane C: 25% of Memory Consisting of 32K Word Sectors
– Memory Plane D: 25% of Memory Consisting of 32K Word Sectors
Suspend/Resume Feature for Erase and Program
– Supports Reading and Programming Data from Any Sector by Suspending Erase
of a Different Sector
– Supports Reading Any Word by Suspending Programming of Any Other Word
Low-power Operation
– 30 mA Active
– 10 µA Standby
Data Polling and Toggle Bit for End of Program Detection
VPP Pin for Write Protection and Accelerated Program/Erase Operations
RESET Input for Device Initialization
CBGA Package
Top or Bottom Boot Block Configuration Available
128-bit Protection Register
Common Flash Interface (CFI)
64-megabit
(4M x 16) and
32-megabit
(2M x 16)
Burst/Page
Mode 1.8-volt
Flash Memory
AT49SN6416
AT49SN6416T
AT49SN3208
AT49SN3208T
Description
The AT49SN6416(T) and AT49SN3208(T) are 1.8-volt 64-megabit and 32-megabit
Flash memories respectively. The memories are divided into multiple sectors and
planes for erase operations. The devices can be read or reprogrammed off a single
1.8V power supply, making them ideally suited for in-system programming. The
devices can be configured to operate in the asynchronous/page read (default mode)
or burst read mode. The burst read mode is used to achieve a faster data rate than is
possible in the asynchronous/page read mode. If the AVD and the CLK signals are
both tied to GND, the device will behave like a standard asynchronous Flash memory.
In the page mode, the AVD signal can be tied to GND or can be pulsed low to latch the
page address. In both cases the CLK can be tied to GND.
Advance
Information
The AT49SN3208(T) is segmented into two memory planes. Reads from memory
plane B may be performed even while program or erase functions are being executed
in memory plane A and vice versa. The AT49SN6416(T) is divided into four memory
planes. A read operation can occur in any of the three planes which is not being programmed or erased. This concurrent operation allows improved system performance
by not requiring the system to wait for a program or erase operation to complete
before a read is performed. To further increase the flexibility of the device, it contains
Rev. 1605C–FLASH–03/02
1
an Erase Suspend and Program Suspend feature. This feature will put the erase or program
on hold for any amount of time and let the user read data from or program data to any of the
remaining sectors. There is no reason to suspend the erase or program operation if the data to
be read is in the other memory plane. The end of program or erase is detected by Data Polling
or toggle bit.
The VPP pin provides data protection and faster programming and erase times. When the VPP
input is below 0.8V, the program and erase functions are inhibited. When V PP is at 1.65V or
above, normal program and erase operations can be performed. With VPP at 12.0V, the program and erase operations are accelerated.
With V PP at 12V, a six-byte command (Enter Single Pulse Program Mode) to remove the
requirement of entering the three-byte program sequence is offered to further improve programming time. After entering the six-byte code, only single pulses on the write control lines
are required for writing into the device. This mode (Single Pulse Word Program) is exited by
powering down the device, by taking the RESET pin to GND or by a high-to-low transition on
the VPP input. Erase, Erase Suspend/Resume, Program Suspend/Resume and Read Reset
commands will not work while in this mode; if entered they will result in data being programmed into the device. It is not recommended that the six-byte code reside in the software
of the final product but only exist in external programming code.
Pin Configurations
Pin Name
Pin Function
I/O0 - I/O15
Data Inputs/Outputs
A0 - A21
Addresses(1)
CE
Chip Enable
OE
Output Enable
WE
Write Enable
AVD
Address Latch Enable
CBGA
Top View
Clock
RESET
Reset
D
WP
Write Protect
VPP
Write Protection and Power Supply for
Accelerated Program/Erase Operations
F
RDY
Ready
G
VCCQ
Output Power Supply
2
3
4
5
6
7
8
A11
A8
VSS
VCC
VPP
A18
A6
A4
A12
A9
A20
CLK RESET A17
A5
A3
A13
A10
A21*
AVD
WE
A19
A7
A2
A15
A14
RDY
A16
I/O12
WP
I/O6
I/O4
I/O2
I/O1
CE
A0
I/O9
I/O0
OE
B
CLK
1. For the AT49SN6416(T), the address bits are
A0 - A21, and for the AT49SN3208(T), the address
bits are A0 - A20. In the following text, address bits
A0 - A21 will be used when referring to both devices.
2
A
C
Note:
1
A1
E
VCCQ I/O15
VSS
I/O14 I/013 I/O11 I/O10
I/O7 VSSQ I/O5
VCC
I/O3 VCCQ I/O8 VSSQ
*A21 is a NC for the AT49SN3208(T).
AT49SN6416(T)/3208(T)
1605C–FLASH–03/02
AT49SN6416(T)/3208(T)
Device
Operation
COMMAND SEQUENCES: The device powers on in the read mode. Command sequences
are used to place the device in other operating modes such as program and erase. After the
completion of a program or an erase cycle, the device enters the read mode. The command
sequences are written by applying a low pulse on the WE input with CE low and OE high or by
applying a low-going pulse on the CE input with WE low and OE high. Prior to the low-going
pulse on the CE or WE signal, the address input may be latched by a low-to-high transition on
the AVD signal or the rising edge of the first clock pulse when AVD is low, whichever occurs
first. If the AVD is not pulsed low, the address will be latched on the falling edge of the WE or
CE pulse whichever occurs first. Valid data is latched on the rising edge of the WE or the CE
pulse, whichever occurs first. The addresses used in the command sequences are not
affected by entering the command sequences.
BURST CONFIGURATION COMMAND: The Program Burst Configuration Register command
is used to program the burst configuration register. The burst configuration register determines
several parameters that control the read operation of the device. Bit B15 determines whether
synchronous burst reads are enabled or asynchronous reads are enabled. Since the page
read operation is an asynchronous operation, bit B15 must be set for asynchronous reads to
enable the page read feature. Bit B14 determines whether a four word page or an eight word
page will be used. The rest of the bits in the burst configuration register are used only for the
burst read mode. Bits B13 - B11 of the burst configuration register determine the clock latency
for the burst mode. The latency can be set to two, three, four, five or six cycles. The clock
latency versus input clock frequency table is shown on page 15. The “Burst Read Waveform”
as shown on page 28 illustrates a clock latency of four; the data is output from the device four
clock cycles after the first low-to-high clock edge following the high-to-low AVD edge. The B10
bit of the configuration register determines the polarity of the RDY signal. The B9 bit of the
burst configuration register determines the number of clocks that data will be held valid (see
Figure 1). The B8 bit of the burst configuration register determines when the RDY signal will
be asserted. When synchronous burst reads are enabled, an interleaved or linear burst
sequence can be selected by setting bit B7. Table 4 shows the difference between the interleaved and burst sequence. Bit B6 selects whether the burst starts and the data output will be
relative to the falling edge or the rising edge of the clock. Bits B2 - B0 of the burst configuration
register determine whether a continuous or fixed-length burst will be used and also determine
whether a four- or eight-word length will be used in the fixed-length mode. When a four or
eight word burst length is selected, Bit B3 can be used to select whether burst accesses wrap
within the burst length boundary or whether they cross word length boundaries to perform linear accesses. Please see Table 4. All other bits in the burst configuration register should be
programmed as shown on page 15. The default state (after power-up or reset) of the burst
configuration register is also shown on page 15. To read the burst configuration register, the
Product ID Entry command is given, followed by a normal read operation from address location 00005H. After reading the burst configuration register, the Product ID Exit command must
be given prior to performing any other operation.
ASYNCHRONOUS READ: There are two types of asynchronous reads – AVD pulsed and
standard asynchronous reads. The AVD pulsed read operation of the device is controlled by
CE, OE, and AVD inputs. The outputs are put in the high-impedance state whenever CE or OE
is high. This dual-line control gives designers flexibility in preventing bus contention. The data
at the address location defined by A0 - A21 and captured by the AVD signal will be read when
CE and OE are low. The address location passes into the device when CE and AVD are low;
the address is latched on the low-to-high transition of AVD. Low input levels on the OE and CE
pins allow the data to be driven out of the device. The access time is measured from stable
address, falling edge of AVD or falling edge of CE, whichever occurs last. During the AVD
pulsed read, the CLK signal may be static high or static low. For standard asynchronous
reads, the AVD and CLK signal should be tied to GND. The asynchronous read diagrams are
shown on page 25.
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1605C–FLASH–03/02
PAGE READ: The page read operation of the device is controlled by CE, OE, and AVD inputs.
The CLK input is ignored during a page read operation and should be tied to GND. The page
size can be four words (default value) or eight words depending on what value bit B14 of the
burst configuration register is programmed to. During a page read, the AVD signal can transition low and then transition high, transition low and remain low, or can be tied to GND. If a
high to low transition on the AVD signal occurs, as shown in Page Read Cycle Waveform 1,
the page address is latched by the low-to-high transition of the AVD signal. However, if the
AVD signal remains low after the high-to-low transition or if the AVD signal is tied to GND, as
shown in Page Read Cycle Waveform 2, then the page address (determined by A21 - A3 for
an eight word page and A21 - A2 for a four word page) cannot change during a page read
operation. The first word access of the page read is the same as the asynchronous read. The
first word is read at an asynchronous speed of 90 ns. Once the first word is read, toggling A0
and A1 (four word page mode) or toggling A0, A1, and A2 (eight word page mode) will result in
subsequent reads within the page being output at a speed of 20 ns. If the AVD and the CLK
pins are both tied to GND, the device will behave like a standard asynchronous Flash memory.
The page read diagrams are shown on page 26.
SYNCHRONOUS READS: Synchronous reads are used to achieve a faster data rate than is
possible in the asynchronous/page read mode. The device can be configured for continuous
or fixed-length burst access. The burst read operation of the device is controlled by CE, OE,
CLK and AVD inputs. The initial read location is determined as for the AVD pulsed asynchronous read operation; it can be any memory location in the device. In the burst access, the
address is latched on the rising edge of the first clock pulse when AVD is low or the rising edge
of the AVD signal, whichever occurs first. The CLK input signal controls the flow of data from
the device for a burst operation. After the clock latency cycles, the data at the next burst
address location is read for each following clock cycle.
CONTINUOUS BURST READ: During a continuous burst read, any number of addresses can
be read from the memory. When a page boundary in the memory is transitioned, additional
time may be required for the device to continue the burst read. To indicate that it is not ready
to continue the burst, the device will drive the RDY pin low (B10 = 0) during the clock cycles in
which new data is not being presented. Once the RDY pin is driven high (B10 = 0), the next
data will be valid. Starting with address zero, page boundaries occur every 128 words in the
memory. During a continuous burst read, the first page boundary transition may occur before
128 words are read, depending on the initial burst address. The RDY signal will be tri-stated
when the CE or OE signal is high.
In the “Burst Read Waveform” as shown on page 28, data D0 is valid asynchronously from
point A, the time when the addresses are latched. D0 is valid within 13.5 ns of the clock edge
for the specified clock latency (the waveforms show a clock latency of four). The low-to-high
transition of the clock at point C results in D1 being read. The transition of the clock at point D
results in a burst read of the last word of the page, D127. The clock transition at point E does
not cause new data to appear on the output lines because the RDY signal goes low (B10 and
B8 = 0) after the clock transition, which signifies that a page boundary in the memory has been
crossed and that new data is not available. The clock transition at point F does cause a burst
read of data D128 because the RDY signal goes high (B10 and B8 = 0) after the clock transition indicating that new data is available. Additional clock transitions, like at point G, will
continue to result in burst reads until the next page boundary is crossed between words D255
and D256.
FIXED-LENGTH BURST READS: During a fixed-length burst mode read, four or eight words
of data may be burst from the device, depending upon the configuration. The device supports
a linear or interleaved burst mode. The burst sequence is shown on page 16. The RDY output
remains high (B10 = 0) during fixed-length bursts. The “Four-word Burst Read Waveform” on
page 28 illustrates a fixed-length burst cycle. As in the continuous burst read, the data D0 is
valid asynchronously from point A, the time when the addresses are latched. D0 is valid within
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AT49SN6416(T)/3208(T)
1605C–FLASH–03/02
AT49SN6416(T)/3208(T)
13.5 ns of the clock edge for the specified clock latency (shown for the case of a latency of
four). The low-to-high transition of the clock at point C results in D1 being read. Similarly, D2
and D3 are output following the next two clock cycles. Returning CE high ends the read cycle.
RESET: A RESET input pin is provided to ease some system applications. When RESET is at
a logic high level, the device is in its standard operating mode. A low level on the RESET pin
halts the present device operation and puts the outputs of the device in a high-impedance
state. When a high level is reasserted on the RESET pin, the device returns to read or standby
mode, depending upon the state of the control pins.
ERASE: Before a word can be reprogrammed it must be erased. The erased state of the
memory bits is a logical “1”. The entire memory can be erased by using the Chip Erase command or individual planes or sectors can be erased by using the Plane Erase or Sector Erase
commands.
CHIP ERASE: Chip Erase is a six-bus cycle operation. The automatic erase begins on the rising edge of the last WE pulse. Chip Erase does not alter the data of the protected sectors.
After the full chip erase the device will return back to the read mode. The hardware reset during Chip Erase will stop the erase but the data will be of unknown state. Any command during
Chip Erase except Erase Suspend will be ignored.
PLANE ERASE: As a alternative to a full chip erase, the device is organized into two planes
(32M) or four planes (64M) that can be individually erased. The plane erase command is a sixbus cycle operation. The plane whose address is valid at the sixth falling edge of WE will be
erased provided none of the sectors within the plane are protected.
SECTOR ERASE: As an alternative to a full chip erase or a plane erase, the device is organized into multiple sectors that can be individually erased. The Sector Erase command is a
six-bus cycle operation. The sector whose address is valid at the sixth falling edge of WE will
be erased provided the given sector has not been protected.
WORD PROGRAMMING: The device is programmed on a word-by-word basis. Programming
is accomplished via the internal device command register and is a four-bus cycle operation.
The programming address and data are latched in the fourth cycle. The device will automatically generate the required internal programming pulses. Please note that a “0” cannot be
programmed back to a “1”; only erase operations can convert “0”s to “1”s.
FLEXIBLE SECTOR PROTECTION: The AT49SN6416(T)/3208(T) offers two sector protection modes, the Softlock and the Hardlock. The Softlock mode is optimized as sector
protection for sectors whose content changes frequently. The Hardlock protection mode is
recommended for sectors whose content changes infrequently. Once either of these two
modes is enabled, the contents of the selected sector is read-only and cannot be erased or
programmed. Each sector can be independently programmed for either the Softlock or Hardlock sector protection mode. At power-up and reset, all sectors have their Softlock protection
mode enabled.
SOFTLOCK AND UNLOCK: The Softlock protection mode can be disabled by issuing a twobus cycle Unlock command to the selected sector. Once a sector is unlocked, its contents can
be erased or programmed. To enable the Softlock protection mode, a six-bus cycle Softlock
command must be issued to the selected sector.
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1605C–FLASH–03/02
HARDLOCK AND WRITE PROTECT (WP): The Hardlock sector protection mode operates in
conjunction with the Write Protection (WP) pin. The Hardlock sector protection mode can be
enabled by issuing a six-bus cycle Hardlock software command to the selected sector. The
state of the Write Protect pin affects whether the Hardlock protection mode can be overridden.
• When the WP pin is low and the Hardlock protection mode is enabled, the sector cannot be
unlocked and the contents of the sector is read-only.
• When the WP pin is high, the Hardlock protection mode is overridden and the sector can be
unlocked via the Unlock command.
To disable the Hardlock sector protection mode, the chip must be either reset or power cycled.
Table 1. Hardlock and Softlock Protection Configurations in Conjunction with WP
WP
Hard
lock
Soft
lock
Erase/
Prog
Allowed?
VCC/5V
0
0
0
Yes
No sector is locked
VCC/5V
0
0
1
No
Sector is Softlocked. The
Unlock command can unlock
the sector.
VCC/5V
0
1
1
No
Hardlock protection mode is
enabled. The sector cannot be
unlocked.
VCC/5V
1
0
0
Yes
No sector is locked.
VCC/5V
1
0
1
No
Sector is Softlocked. The
Unlock command can unlock
the sector.
VCC/5V
1
1
0
Yes
Hardlock protection mode is
overridden and the sector is
not locked.
VCC/5V
1
1
1
No
Hardlock protection mode is
overridden and the sector can
be unlocked via the Unlock
command.
VIL
x
x
x
No
Erase and Program Operations
cannot be performed.
VPP
Comments
SECTOR PROTECTION DETECTION: A software method is available to determine if the sector protection Softlock or Hardlock features are enabled. When the device is in the software
product identification mode (see Software Product Identification Entry and Exit sections) a
read from the I/O0 and I/O1 at address location 00002H within a sector will show if the sector
is unlocked, softlocked, or hardlocked.
Table 2. Sector Protection Status
6
I/O1
I/O0
Sector Protection Status
0
0
Sector Not Locked
0
1
Softlock Enabled
1
0
Hardlock Enabled
1
1
Both Hardlock and Softlock Enabled
AT49SN6416(T)/3208(T)
1605C–FLASH–03/02
AT49SN6416(T)/3208(T)
PROGRAM/ERASE STATUS: The device provides several bits to determine the status of a
program or erase operation: I/O2, I/O3, I/O5, I/O6, and I/O7. The Table 3 on page 12 and the
following four sections describe the function of these bits. To provide greater flexibility for
system designers, the AT49SN6416(T)/3208(T) contains a programmable configuration register. The configuration register allows the user to specify the status bit operation. The
configuration register can be set to one of two different values, “00” or “01”. If the configuration
register is set to “00”, the part will automatically return to the read mode after a successful program or erase operation. If the configuration register is set to a “01”, a Product ID Exit
command must be given after a successful program or erase operation before the part will
return to the read mode. It is important to note that whether the configuration register is set to
a “00” or to a “01”, any unsuccessful program or erase operation requires using the Product ID
Exit command to return the device to read mode. The default value (after power-up) for the
configuration register is “00”. Using the four-bus cycle set configuration register command as
shown in the Command Definition table on page 13, the value of the configuration register can
be changed. Voltages applied to the reset pin will not alter the value of the configuration register. The value of the configuration register will affect the operation of the I/O7 status bit as
described below.
DATA POLLING: The AT49SN6416(T)/3208(T) features Data Polling to indicate the end of a
program cycle. If the status configuration register is set to a “00”, during a program cycle an
attempted read of the last byte/word loaded will result in the complement of the loaded data on
I/O7. Once the program cycle has been completed, true data is valid on all outputs and the
next cycle may begin. During a chip or sector erase operation, an attempt to read the device
will give a “0” on I/O7. Once the program or erase cycle has completed, true data will be read
from the device. Data Polling may begin at any time during the program cycle. Please see
Table 3 on page 12 for more details.
If the status bit configuration register is set to a “01”, the I/O7 status bit will be low while the
device is actively programming or erasing data. I/O7 will go high when the device has completed a program or erase operation. Once I/O7 has gone high, status information on the other
pins can be checked.
The Data Polling status bit must be used in conjunction with the erase/program and VPP status
bit as shown in the algorithm in Figures 2 and 3.
TOGGLE BIT: In addition to Data Polling, the AT49SN6416(T)/3208(T) provides another
method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the memory will result in I/O6 toggling between
one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data
will be read. Examining the toggle bit may begin at any time during a program cycle. Please
see Table 3 on page 12 for more details.
The toggle bit status bit should be used in conjunction with the erase/program and VPP status
bit as shown in the algorithm in Figures 4 and 5 on page 11.
ERASE/PROGRAM STATUS BIT: The device offers a status bit on I/O5 that indicates
whether the program or erase operation has exceeded a specified internal pulse count limit. If
the status bit is a “1”, the device is unable to verify that an erase or a byte/word program operation has been successfully performed. The device may also output a “1” on I/O5 if the system
tries to program a “1” to a location that was previously programmed to a “0”. Only an erase
operation can change a “0” back to a “1”. If a program (Sector Erase) command is issued to a
protected sector, the protected sector will not be programmed (erased). The device will go to a
status read mode and the I/O5 status bit will be set high, indicating the program (erase) operation did not complete as requested. Once the erase/program status bit has been set to a “1”,
the system must write the Product ID Exit command to return to the read mode. The
erase/program status bit is a “0” while the erase or program operation is still in progress.
Please see Table 3 on page 12 for more details.
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1605C–FLASH–03/02
VPP STATUS BIT: The AT49SN6416(T)/3208(T) provides a status bit on I/O3 that provides
information regarding the voltage level of the VPP pin. During a program or erase operation, if
the voltage on the VPP pin is not high enough to perform the desired operation successfully,
the I/O3 status bit will be a “1”. Once the VPP status bit has been set to a “1”, the system must
write the Product ID Exit command to return to the read mode. On the other hand, if the voltage level is high enough to perform a program or erase operation successfully, the VPP status
bit will output a “0”. Please see Table 3 on page 12 for more details.
ERASE SUSPEND/ERASE RESUME: The Erase Suspend command allows the system to
interrupt a sector erase operation and then program or read data from a different sector within
the same plane. Since this device has a dual plane architecture, there is no need to use the
erase suspend feature while erasing a sector when you want to read data from a sector in the
other plane. After the Erase Suspend command is given, the device requires a maximum time
of 15 µs to suspend the erase operation. After the erase operation has been suspended, the
plane that contains the suspended sector enters the erase-suspend-read mode. The system
can then read data or program data to any other sector within the device. An address is not
required during the Erase Suspend command. During a sector erase suspend, another sector
cannot be erased. To resume the sector erase operation, the system must write the Erase
Resume command. The Erase Resume command is a one-bus cycle command, which does
require the plane address. The device also supports an erase suspend during a complete chip
erase. While the chip erase is suspended, the user can read from any sector within the memory that is protected. The command sequence for a chip erase suspend and a sector erase
suspend are the same.
PROGRAM SUSPEND/PROGRAM RESUME: The Program Suspend command allows the
system to interrupt a programming operation and then read data from a different word within
the memory. After the Program Suspend command is given, the device requires a maximum
of 10 µs to suspend the programming operation. After the programming operation has been
suspended, the system can then read from any other word within the device. An address is not
required during the program suspend operation. To resume the programming operation, the
system must write the Program Resume command. The program suspend and resume are
one-bus cycle commands. The command sequence for the erase suspend and program suspend are the same, and the command sequence for the erase resume and program resume
are the same.
128-BIT PROTECTION REGISTER: The AT49SN6416(T)/3208(T) contains a 128-bit register
that can be used for security purposes in system design. The protection register is divided into
two 64-bit blocks. The two blocks are designated as block A and block B. The data in block A
is non-changeable and is programmed at the factory with a unique number. The data in block
B is programmed by the user and can be locked out such that data in the block cannot be
reprogrammed. To program block B in the protection register, the four-bus cycle Program Protection Register command must be used as shown in the Command Definition in Hex table on
page 13. To lock out block B, the four-bus cycle lock protection register command must be
used as shown in the Command Definition in Hex table. Data bit D1 must be zero during the
fourth bus cycle. All other data bits during the fourth bus cycle are don’t cares. To determine
whether block B is locked out, the Product ID Entry command is given followed by a read operation from address 80H. If data bit D1 is zero, block B is locked. If data bit D1 is one, block B
can be reprogrammed. Please see the Protection Register Addressing Table on page 14 for
the address locations in the protection register. To read the protection register, the Product ID
Entry command is given followed by a normal read operation from an address within the protection register. After determining whether block B is protected or not or reading the protection
register, the Product ID Exit command must be given prior to performing any other operation.
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AT49SN6416(T)/3208(T)
1605C–FLASH–03/02
AT49SN6416(T)/3208(T)
CFI: Common Flash Interface (CFI) is a published, standardized data structure that may be
read from a flash device. CFI allows system software to query the installed device to determine the configurations, various electrical and timing parameters, and functions supported by
the device. CFI is used to allow the system to learn how to interface to the flash device most
optimally. The two primary benefits of using CFI are ease of upgrading and second source
availability. The command to enter the CFI Query mode is a one-bus cycle command which
requires writing data 98h to address 55h. The CFI Query command can be written when the
device is ready to read data or can also be written when the part is in the product ID mode.
Once in the CFI Query mode, the system can read CFI data at the addresses given in Table 5
on page 34. To exit the CFI Query mode, the product ID exit command must be given. If the
CFI Query command is given while the part is in the product ID mode, then the product ID exit
command must first be given to return the part to the product ID mode. Once in the product ID
mode, it will be necessary to give another product ID exit command to return the part to the
read mode.
HARDWARE DATA PROTECTION: Hardware features protect against inadvertent programs
to the AT49SN6416(T)/3208(T) in the following ways: (a) VCC sense: if VCC is below 1.4V (typical), the program function is inhibited. (b) VCC power-on delay: once VCC has reached the VCC
sense level, the device will automatically time-out 10 ms (typical) before programming. (c) Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (d) Noise
filter: pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program
cycle. (e) VPP is less than VILPP.
INPUT LEVELS: While operating with a 1.8V to 1.95V power supply, the address inputs and
control inputs (OE, CE and WE) may be driven from 0 to 2.5V without adversely affecting the
operation of the device. The I/O lines can be driven from 0 to VCCQ + 0.6V.
OUTPUT LEVELS: For the AT49SN6416(T)/3208(T), output high levels are equal to VCCQ 0.1V (not VCC). VCCQ must be regulated between 1.8V - 2.25V.
Figure 1. Output Configuration
CLK
1 CLK
Data Hold
(B9 = 0)
I/00 - I/015
2 CLK
Data Hold
(B9 = 1)
I/00 - I/015
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
9
1605C–FLASH–03/02
Figure 2. Data Polling Algorithm
(Configuration Register = 00)
Figure 3. Data Polling Algorithm
(Configuration Register = 01)
START
START
Read I/O7 - I/O0
Addr = VA
Read I/O7 - I/O0
Addr = VA
NO
YES
I/O7 = 1?
I/O7 = Data?
YES
NO
NO
I/O3, I/O5 = 1?
I/O3, I/O5 = 1?
YES
YES
Read I/O7 - I/O0
Addr = VA
I/O7 = Data?
Notes:
10
Program/Erase
Operation Not
Successful, Write
Product ID
Exit Command
YES
NO
Program/Erase
Operation Not
Successful, Write
Product ID
Exit Command
NO
Note:
Program/Erase
Operation
Successful,
Device in
Read Mode
Program/Erase
Operation
Successful,
Write Product ID
Exit Command
1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector
address within the sector being erased. During
chip erase, a valid address is any non-protected
sector address.
1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector
address within the sector being erased. During chip
erase, a valid address is any non-protected sector
address.
2. I/O7 should be rechecked even if I/O5 = “1”
because I/O7 may change simultaneously with
I/O5.
AT49SN6416(T)/3208(T)
1605C–FLASH–03/02
AT49SN6416(T)/3208(T)
Figure 5. Toggle Bit Algorithm
(Configuration Register = 01)
Figure 4. Toggle Bit Algorithm
(Configuration Register = 00)
START
START
Read I/O7 - I/O0
Read I/O7 - I/O0
Read I/O7 - I/O0
Read I/O7 - I/O0
Toggle Bit =
Toggle?
NO
Toggle Bit =
Toggle?
YES
YES
NO
NO
I/O3, I/O5 = 1?
Read I/O7 - I/O0
Twice
Read I/O7 - I/O0
Twice
Toggle Bit =
Toggle?
NO
Note:
NO
YES
YES
Program/Erase
Operation Not
Successful, Write
Product ID
Exit Command
I/O3, I/O5 = 1?
YES
YES
Toggle Bit =
Toggle?
NO
Program/Erase
Operation Not
Successful, Write
Product ID
Exit Command
Program/Erase
Operation
Successful,
Device in
Read Mode
1. The system should recheck the toggle bit even if
I/O5 = “1” because the toggle bit may stop toggling
as I/O5 changes to “1”.
Note:
Program/Erase
Operation
Successful,
Write Product ID
Exit Command
1. The system should recheck the toggle bit even
if I/O5 = “1” because the toggle bit may stop
toggling as I/O5 changes to “1”.
11
1605C–FLASH–03/02
Table 3. Status Bit Table(1)
I/O7
Configuration
Register:
I/O6
I/O2
00/01
00/01
00/01
00/01
00/01
00/01
00/01
00/01
00/01
00/01
00/01
00/01
Plane A
Plane B
Plane C
Plane D
Plane A
Plane B
Plane C
Plane D
Plane A
Plane B
Plane C
Plane D
Programming
in Plane A
I/O7/0
DATA
DATA
DATA
TOGGLE
DATA
DATA
DATA
1
DATA
DATA
DATA
Programming
in Plane B
DATA
I/O7/0
DATA
DATA
DATA
TOGGLE
DATA
DATA
DATA
1
DATA
DATA
Programming
in Plane C
DATA
DATA
I/O7/0
DATA
DATA
DATA
TOGGLE
DATA
DATA
DATA
1
DATA
Programming
in Plane D
DATA
DATA
DATA
I/O7/0
DATA
DATA
DATA
TOGGLE
DATA
DATA
DATA
1
Erasing in
Plane A
0/0
DATA
DATA
DATA
TOGGLE
DATA
DATA
DATA
TOGGLE
DATA
DATA
DATA
Erasing in
Plane B
DATA
0/0
DATA
DATA
DATA
TOGGLE
DATA
DATA
DATA
TOGGLE
DATA
DATA
Erasing in
Plane C
DATA
DATA
0/0
DATA
DATA
DATA
TOGGLE
DATA
DATA
DATA
TOGGLE
DATA
Erasing in
Plane D
DATA
DATA
DATA
0/0
DATA
DATA
DATA
TOGGLE
DATA
DATA
DATA
TOGGLE
Erase
Suspended &
Read Erasing
Sector
1
1
1
1
1
1
1
1
TOGGLE
TOGGLE
TOGGLE
TOGGLE
Erase
Suspended &
Read Nonerasing Sector
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
Erase
Suspended &
Program Nonerasing Sector
in Plane A
I/O7/0
DATA
DATA
DATA
TOGGLE
DATA
DATA
DATA
TOGGLE
DATA
DATA
DATA
Erase
Suspended &
Program Nonerasing Sector
in Plane B
DATA
I/O7/0
DATA
DATA
DATA
TOGGLE
DATA
DATA
DATA
TOGGLE
DATA
DATA
Erase
Suspended &
Program Nonerasing Sector
in Plane C
DATA
DATA
I/O7/0
DATA
DATA
DATA
TOGGLE
DATA
DATA
DATA
TOGGLE
DATA
Erase
Suspended &
Program Nonerasing Sector
in Plane D
DATA
DATA
DATA
I/O7/0
DATA
DATA
DATA
TOGGLE
DATA
DATA
DATA
TOGGLE
Read Address
In
While
Note:
12
1. For the AT49SN3208(T) only plane A and plane B apply in the table above.
AT49SN6416(T)/3208(T)
1605C–FLASH–03/02
AT49SN6416(T)/3208(T)
Command Definition in (Hex)(1)
1st Bus
Cycle
Bus
Cycles
Addr
Data
Read
1
Addr
DOUT
Chip Erase
6
555
Plane Erase
6
555
Command Sequence
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
5th Bus
Cycle
Addr
Data
Addr
Data
Addr
Data
Addr
Data
AA
AAA(2)
55
555
80
555
AA
AAA
AA
AAA
55
555
80
555
AA
AAA
6th Bus
Cycle
Addr
Data
55
555
10
55
PA(6)
20
AAA
55
SA
(4)
30
Sector Erase
6
555
AA
AAA
55
555
80
555
AA
Word Program
4
555
AA
AAA
55
555
A0
Addr
DIN
Enter Single-pulse Program
Mode
6
555
AA
AAA
55
555
80
555
AA
AAA
55
555
A0
Single-pulse Word Program
Mode
1
Addr
DIN
Sector Softlock
6
555
AA
AAA
55
555
80
555
AA
AAA
55
SA(4)
40
(4)
70
80
555
AA
AAA
55
SA(4)(5)
60
Sector Unlock
2
555
AA
SA
Sector Hardlock
6
555
AA
AAA
55
555
Erase/Program Suspend
1
xxx
B0
Erase/Program Resume
1
PA(6)
30
Product ID Entry
3
555
AA
AAA
55
xxx(7)
90
(3)
Product ID Exit
3
555
AA
AAA
55
555
F0
Product ID Exit(3)
1
xxx
FX
Program Burst
Configuration Register
4
555
AA
AAA
55
555
D0
xxx
(8)
Read Burst Configuration
Register
4
555
AA
AAA
55
xxx(7)
90
005
DOUT
Program Protection
Register – Block B
4
555
AA
AAA
55
555
C0
Addr
DIN
Lock Protection
Register – Block B
4
555
AA
AAA
55
555
C0
080
X0
Status of Block B
Protection
4
555
AA
AAA
55
555
90
80
DOUT(9)
Set Configuration Register
4
555
AA
AAA
55
555
E0
xxx
00/01(10)
CFI Query
1
X55
98
Notes:
1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex). The ADDRESS FORMAT in each bus cycle
is as follows: A11 - A0 (Hex), A11 - A21 (Don’t Care).
2.
3.
4.
5.
6.
Since A11 is a Don’t Care, AAA can be replaced with 2AA.
Either one of the Product ID Exit commands can be used.
SA = sector address. Any word address within a sector can be used to designate the sector address (see pages 17 - 22 for details).
Once a sector is in the Hardlock protection mode, it cannot be disabled unless the chip is reset or power cycled.
PA is the plane address (A21 - A20 for the AT49SN6416(T), A20 - A19 for the AT49SN3208(T)).
7. For the AT49SN3208:
For the AT49SN3208T:
xxx = 0XX555 Status Read from Plane A
xxx = 1XX555 Status Read from Plane A
xxx = 1XX555 Status Read from Plane B
xxx = 0XX555 Status Read from Plane B
For the AT49SN6416:
For the AT49SN6416T:
xxx = 0XX555 Status Read from Plane A
xxx = 3XX555 Status Read from Plane A
xxx = 1XX555 Status Read from Plane B
xxx = 2XX555 Status Read from Plane B
xxx = 2XX555 Status Read from Plane C
xxx = 1XX555 Status Read from Plane C
xxx = 3XX555 Status Read from Plane D
xxx = 0XX555 Status Read from Plane D
8. See “Burst Configuration Register” on page 15.
9. If data bit D1 is “0”, block B is locked. If data bit D1 is “1”, block B can be reprogrammed.
10. The default state (after power-up) of the configuration register is “00”.
13
1605C–FLASH–03/02
Absolute Maximum Ratings*
*NOTICE:
Temperature under Bias ................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages Except VPP
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
VPP Input Voltage
with Respect to Ground ......................................... 0V to 13.0V
All Output Voltages
with Respect to Ground ...........................-0.6V to V CCQ + 0.6V
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Voltage on OE
with Respect to Ground ...................................-0.6V to +13.5V
Protection Register Addressing Table
Word
Use
Block
A7
A6
A5
A4
A3
A2
A1
A0
0
Factory
A
1
0
0
0
0
0
0
1
1
Factory
A
1
0
0
0
0
0
1
0
2
Factory
A
1
0
0
0
0
0
1
1
3
Factory
A
1
0
0
0
0
1
0
0
4
User
B
1
0
0
0
0
1
0
1
5
User
B
1
0
0
0
0
1
1
0
6
User
B
1
0
0
0
0
1
1
1
User
B
1
0
0
0
1
0
0
0
7
Note:
14
1. All address lines not specified in the above table must be 0 when accessing the Protection Register, i.e., A21 - A8 = 0.
AT49SN6416(T)/3208(T)
1605C–FLASH–03/02
AT49SN6416(T)/3208(T)
Burst Configuration Register
B15
0
1(1)
Synchronous Burst Reads Enabled
Asynchronous Reads Enabled
B14
0(1)
1
Four Word Page
Eight Word Page
B13 - B11:
010
011
100
101
110(1)
Clock Latency of Two
Clock Latency of Three
Clock Latency of Four
Clock Latency of Five
Clock Latency of Six
B10
0
1(1)
RDY Signal is Active Low
RDY Signal is Active High
B9
0
1(1)
Hold Data for One Clock
Hold Data for Two Clocks
B8
0
1(1)
RDY Asserted during Clock Cycle in which Data is Valid
RDY Asserted One Clock Cycle before Data is Valid
B7
0
1(1)
Interleaved Burst Sequence
Linear Burst Sequence
B6
0
1(1)
Burst Starts and Data Output on Falling Clock Edge
Burst Starts and Data Output on Rising Clock Edge
B5 - B4
00(1)
Reserved for Future Use
B3
0
1(1)
Wrap Burst Within Burst length set by B2 - B0
Don’t Wrap Accesses Within Burst Length set by B2 - B0
B2 - B0
001
010
111(1)
Four-word Burst
Eight-word Burst
Continuous Burst
Note:
1. Default State
Clock Latency versus Input Clock Frequency
Minimum Clock Latency
(Minimum Number of Clocks Following Address Latch)
Input Clock Frequency
6
≤ 54 MHz
4
≤ 40 MHz
2
≤ 20 MHz
15
1605C–FLASH–03/02
Table 4. Sequence and Burst Length
Burst Addressing Sequence (Decimal)
Start Addr.
(Decimal)
Wrap
B3 = 0
0
8-word Burst Length
B2 – B0 = 010
Continuous Burst
B2 – B0 = 111
Linear
Interleaved
Linear
Interleaved
Linear
0
0-1-2-3
0-1-2-3
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6...
1
0
1-2-3-0
1-0-3-2
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
1-2-3-4-5-6-7...
2
0
2-3-0-1
2-3-0-1
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
2-3-4-5-6-7-8...
3
0
3-0-1-2
3-2-1-0
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
3-4-5-6-7-8-9...
4
0
4-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
4-5-6-7-8-9-10...
5
0
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
5-6-7-8-9-10-11...
6
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
6-7-8-9-10-11-12...
7
0
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
7-8-9-10-11-12-13...
...
...
...
...
...
14
0
14-15-16-17-18-19-20
15
0
15-16-17-18-19-20-21
...
...
...
...
...
...
...
...
...
...
...
0
1
0-1-2-3
N/A
0-1-2-3-4-5-6-7
N/A
0-1-2-3-4-5-6...
1
1
1-2-3-4
N/A
1-2-3-4-5-6-7-8
N/A
1-2-3-4-5-6-7...
2
1
2-3-4-5
N/A
2-3-4-5-6-7-8-9
N/A
2-3-4-5-6-7-8...
3
1
3-4-5-6
N/A
3-4-5-6-7-8-9-10
N/A
3-4-5-6-7-8-9...
4
1
4-5-6-7-8-9-10-11
N/A
4-5-6-7-8-9-10...
5
1
5-6-7-8-9-10-11-12
N/A
5-6-7-8-9-10-11...
6
1
6-7-8-9-10-11-1213
N/A
6-7-8-9-10-11-12...
7
1
7-8-9-10-11-12-1314
N/A
7-8-9-10-11-12-13...
...
...
...
...
16
Wrap
B3 = 1
4-word Burst Length
B2 – B0 = 001
...
...
...
...
14
1
14-15-16-17-18-19-20
15
1
15-16-17-18-19-20-21
AT49SN6416(T)/3208(T)
1605C–FLASH–03/02
AT49SN6416(T)/3208(T)
Memory Organization – AT49SN3208 (Continued)
Memory Organization – AT49SN3208
x16
x16
Plane
Sector
Size (Words)
Address Range (A20 - A0)
Plane
Sector
Size (Words)
Address Range (A20 - A0)
A
SA0
4K
00000 - 00FFF
B
SA36
32K
E8000 - EFFFF
A
SA1
4K
01000 - 01FFF
B
SA37
32K
F0000 - F7FFF
A
SA2
4K
02000 - 02FFF
B
SA38
32K
F8000 - FFFFF
A
SA3
4K
03000 - 03FFF
B
SA39
32K
100000 - 107FFF
A
SA4
4K
04000 - 04FFF
B
SA40
32K
108000 - 10FFFF
A
SA5
4K
05000 - 05FFF
B
SA41
32K
110000 - 117FFF
A
SA6
4K
06000 - 06FFF
B
SA42
32K
118000 - 11FFFF
A
SA7
4K
07000 - 07FFF
B
SA43
32K
120000 - 127FFF
A
SA8
32K
08000 - 0FFFF
B
SA44
32K
128000 - 12FFFF
A
SA9
32K
10000 - 17FFF
B
SA45
32K
130000 - 137FFF
A
SA10
32K
18000 - 1FFFF
B
SA46
32K
138000 - 13FFFF
A
SA11
32K
20000 - 27FFF
B
SA47
32K
140000 - 147FFF
A
SA12
32K
28000 - 2FFFF
B
SA48
32K
148000 - 14FFFF
A
SA13
32K
30000 - 37FFF
B
SA49
32K
150000 - 157FFF
A
SA14
32K
38000 - 3FFFF
B
SA50
32K
158000 - 15FFFF
A
SA15
32K
40000 - 47FFF
B
SA51
32K
160000 - 167FFF
A
SA16
32K
48000 - 4FFFF
B
SA52
32K
168000 - 16FFFF
A
SA17
32K
50000 - 57FFF
B
SA53
32K
170000 - 177FFF
A
SA18
32K
58000 - 5FFFF
B
SA54
32K
178000 - 17FFFF
A
SA19
32K
60000 - 67FFF
B
SA55
32K
180000 - 187FFF
A
SA20
32K
68000 - 6FFFF
B
SA56
32K
188000 - 18FFFF
A
SA21
32K
70000 - 77FFF
B
SA57
32K
190000 - 197FFF
A
SA22
32K
78000 - 7FFFF
B
SA58
32K
198000 - 19FFFF
B
SA23
32K
80000 - 87FFF
B
SA59
32K
1A0000 - 1A7FFF
B
SA24
32K
88000 - 8FFFF
B
SA60
32K
1A8000 - 1AFFFF
B
SA25
32K
90000 - 97FFF
B
SA61
32K
1B0000 - 1B7FFF
B
SA26
32K
98000 - 9FFFF
B
SA62
32K
1B8000 - 1BFFFF
B
SA27
32K
A0000 - A7FFF
B
SA63
32K
1C0000 - 1C7FFF
B
SA28
32K
A8000 - AFFFF
B
SA64
32K
1C8000 - 1CFFFF
B
SA29
32K
B0000 - B7FFF
B
SA65
32K
1D0000 - 1D7FFF
B
SA30
32K
B8000 - BFFFF
B
SA66
32K
1D8000 - 1DFFFF
B
SA31
32K
C0000 - C7FFF
B
SA67
32K
1E0000 - 1E7FFF
B
SA32
32K
C8000 - CFFFF
B
SA68
32K
1E8000 - 1EFFFF
B
SA33
32K
D0000 - D7FFF
B
SA69
32K
1F0000 - 1F7FFF
B
SA34
32K
D8000 - DFFFF
B
SA70
32K
1F8000 - 1FFFFF
B
SA35
32K
E0000 - E7FFF
17
1605C–FLASH–03/02
Memory Organization – AT49SN3208T
Memory Organization – AT49SN3208T (Continued)
x16
Plane
18
Sector
x16
Size (Words)
Address Range (A20 - A0)
Plane
Sector
Size (Words)
Address Range (A20 - A0)
B
SA0
32K
00000 - 07FFF
B
SA36
32K
120000 - 127FFF
B
SA1
32K
08000 - 0FFFF
B
SA37
32K
128000 - 12FFFF
B
SA2
32K
10000 - 17FFF
B
SA38
32K
130000 - 137FFF
B
SA3
32K
18000 - 1FFFF
B
SA39
32K
138000 - 13FFFF
B
SA4
32K
20000 - 27FFF
B
SA40
32K
140000 - 147FFF
B
SA5
32K
28000 - 2FFFF
B
SA41
32K
148000 - 14FFFF
B
SA6
32K
30000 - 37FFF
B
SA42
32K
150000 - 157FFF
B
SA7
32K
38000 - 3FFFF
B
SA43
32K
158000 - 15FFFF
B
SA8
32K
40000 - 47FFF
B
SA44
32K
160000 - 167FFF
B
SA9
32K
48000 - 4FFFF
B
SA45
32K
168000 - 16FFFF
B
SA10
32K
50000 - 57FFF
B
SA46
32K
170000 - 177FFF
B
SA11
32K
58000 - 5FFFF
B
SA47
32K
178000 - 17FFFF
B
SA12
32K
60000 - 67FFF
A
SA48
32K
180000 - 187FFF
B
SA13
32K
68000 - 6FFFF
A
SA49
32K
188000 - 18FFFF
B
SA14
32K
70000 - 77FFF
A
SA50
32K
190000 - 197FFF
B
SA15
32K
78000 - 7FFFF
A
SA51
32K
198000 - 19FFFF
B
SA16
32K
80000 - 87FFF
A
SA52
32K
1A0000 - 1A7FFF
B
SA17
32K
88000 - 8FFFF
A
SA53
32K
1A8000 - 1AFFFF
B
SA18
32K
90000 - 97FFF
A
SA54
32K
1B0000 - 1B7FFF
B
SA19
32K
98000 - 9FFFF
A
SA55
32K
1B8000 - 1BFFFF
B
SA20
32K
A0000 - A7FFF
A
SA56
32K
1C0000 - 1C7FFF
B
SA21
32K
A8000 - AFFFF
A
SA57
32K
1C8000 - 1CFFFF
B
SA22
32K
B0000 - B7FFF
A
SA58
32K
1D0000 - 1D7FFF
B
SA23
32K
B8000 - BFFFF
A
SA59
32K
1D8000 - 1DFFFF
B
SA24
32K
C0000 - C7FFF
A
SA60
32K
1E0000 - 1E7FFF
B
SA25
32K
C8000 - CFFFF
A
SA61
32K
1E8000 - 1EFFFF
B
SA26
32K
D0000 - D7FFF
A
SA62
32K
1F0000 - 1F7FFF
B
SA27
32K
D8000 - DFFFF
A
SA63
4K
1F8000 - 1F8FFF
B
SA28
32K
E0000 - E7FFF
A
SA64
4K
1F9000 - 1F9FFF
B
SA29
32K
E8000 - EFFFF
A
SA65
4K
1FA000 - 1FAFFF
B
SA30
32K
F0000 - F7FFF
A
SA66
4K
1FB000 - 1FBFFF
B
SA31
32K
F8000 - FFFFF
A
SA67
4K
1FC000 - 1FCFFF
B
SA32
32K
100000 - 107FFF
A
SA68
4K
1FD000 - 1FDFFF
B
SA33
32K
108000 - 10FFFF
A
SA69
4K
1FE000 - 1FEFFF
B
SA34
32K
110000 - 117FFF
A
SA70
4K
1FF000 - 1FFFFF
B
SA35
32K
118000 - 11FFFF
AT49SN6416(T)/3208(T)
1605C–FLASH–03/02
AT49SN6416(T)/3208(T)
Memory Organization – AT49SN6416
Memory Organization – AT49SN6416 (Continued)
x16
Plane
Sector
x16
Size (Words)
Address Range (A21 - A0)
Plane
Sector
Size (Words)
Address Range (A21 - A0)
A
SA0
4K
00000 - 00FFF
B
SA44
32K
128000 - 12FFFF
A
SA1
4K
01000 - 01FFF
B
SA45
32K
130000 - 137FFF
A
SA2
4K
02000 - 02FFF
B
SA46
32K
138000 - 13FFFF
A
SA3
4K
03000 - 03FFF
B
SA47
32K
140000 - 147FFF
A
SA4
4K
04000 - 04FFF
B
SA48
32K
148000 - 14FFFF
A
SA5
4K
05000 - 05FFF
B
SA49
32K
150000 - 157FFF
A
SA6
4K
06000 - 06FFF
B
SA50
32K
158000 - 15FFFF
A
SA7
4K
07000 - 07FFF
B
SA51
32K
160000 - 167FFF
A
SA8
32K
08000 - 0FFFF
B
SA52
32K
168000 - 16FFFF
A
SA9
32K
10000 - 17FFF
B
SA53
32K
170000 - 177FFF
A
SA10
32K
18000 - 1FFFF
B
SA54
32K
178000 - 17FFFF
A
SA11
32K
20000 - 27FFF
B
SA55
32K
180000 - 187FFF
A
SA12
32K
28000 - 2FFFF
B
SA56
32K
188000 - 18FFFF
A
SA13
32K
30000 - 37FFF
B
SA57
32K
190000 - 197FFF
A
SA14
32K
38000 - 3FFFF
B
SA58
32K
198000 - 19FFFF
A
SA15
32K
40000 - 47FFF
B
SA59
32K
1A0000 - 1A7FFF
A
SA16
32K
48000 - 4FFFF
B
SA60
32K
1A8000 - 1AFFFF
A
SA17
32K
50000 - 57FFF
B
SA61
32K
1B0000 - 1B7FFF
A
SA18
32K
58000 - 5FFFF
B
SA62
32K
1B8000 - 1BFFFF
A
SA19
32K
60000 - 67FFF
B
SA63
32K
1C0000 - 1C7FFF
A
SA20
32K
68000 - 6FFFF
B
SA64
32K
1C8000 - 1CFFFF
A
SA21
32K
70000 - 77FFF
B
SA65
32K
1D0000 - 1D7FFF
A
SA22
32K
78000 - 7FFFF
B
SA66
32K
1D8000 - 1DFFFF
A
SA23
32K
80000 - 87FFF
B
SA67
32K
1E0000 - 1E7FFF
A
SA24
32K
88000 - 8FFFF
B
SA68
32K
1E8000 - 1EFFFF
A
SA25
32K
90000 - 97FFF
B
SA69
32K
1F0000 - 1F7FFF
A
SA26
32K
98000 - 9FFFF
B
SA70
32K
1F8000 - 1FFFFF
A
SA27
32K
A0000 - A7FFF
C
SA71
32K
200000 - 207FFF
A
SA28
32K
A8000 - AFFFF
C
SA72
32K
208000 - 20FFFF
A
SA29
32K
B0000 - B7FFF
C
SA73
32K
210000 - 217FFF
A
SA30
32K
B8000 - BFFFF
C
SA74
32K
218000 - 21FFFF
A
SA31
32K
C0000 - C7FFF
C
SA75
32K
220000 - 227FFF
A
SA32
32K
C8000 - CFFFF
C
SA76
32K
228000 - 22FFFF
A
SA33
32K
D0000 - D7FFF
C
SA77
32K
230000 - 237FFF
A
SA34
32K
D8000 - DFFFF
C
SA78
32K
238000 - 23FFFF
A
SA35
32K
E0000 - E7FFF
C
SA79
32K
240000 - 247FFF
A
SA36
32K
E8000 - EFFFF
C
SA80
32K
248000 - 24FFFF
A
SA37
32K
F0000 - F7FFF
C
SA81
32K
250000 - 257FFF
A
SA38
32K
F8000 - FFFFF
C
SA82
32K
258000 - 25FFFF
B
SA39
32K
100000 - 107FFF
C
SA83
32K
260000 - 267FFF
B
SA40
32K
108000 - 10FFFF
C
SA84
32K
268000 - 26FFFF
B
SA41
32K
110000 - 117FFF
C
SA85
32K
270000 - 277FFF
B
SA42
32K
118000 - 11FFFF
C
SA86
32K
278000 - 27FFFF
B
SA43
32K
120000 - 127FFF
C
SA87
32K
280000 - 287FFF
19
1605C–FLASH–03/02
Memory Organization – AT49SN6416 (Continued)
Memory Organization – AT49SN6416 (Continued)
x16
x16
Plane
20
Sector
Size (Words)
Address Range (A21 - A0)
Plane
Sector
Size (Words)
Address Range (A21 - A0)
C
SA88
32K
288000 - 28FFFF
D
SA112
32K
348000 - 34FFFF
C
SA89
32K
290000 - 297FFF
D
SA113
32K
350000 - 357FFF
C
SA90
32K
298000 - 29FFFF
D
SA114
32K
358000 - 35FFFF
C
SA91
32K
2A0000 - 2A7FFF
D
SA115
32K
360000 - 367FFF
C
SA92
32K
2A8000 - 2AFFFF
D
SA116
32K
368000 - 36FFFF
C
SA93
32K
2B0000 - 2B7FFF
D
SA117
32K
370000 - 377FFF
C
SA94
32K
2B8000 - 2BFFFF
D
SA118
32K
378000 - 37FFFF
C
SA95
32K
2C0000 - 2C7FFF
D
SA119
32K
380000 - 387FFF
C
SA96
32K
2C8000 - 2CFFFF
D
SA120
32K
388000 - 38FFFF
C
SA97
32K
2D0000 - 2D7FFF
D
SA121
32K
390000 - 397FFF
C
SA98
32K
2D8000 - 2DFFFF
D
SA122
32K
398000 - 39FFFF
C
SA99
32K
2E0000 - 2E7FFF
D
SA123
32K
3A0000 - 3A7FFF
C
SA100
32K
2E8000 - 2EFFFF
D
SA124
32K
3A8000 - 3AFFFF
C
SA101
32K
2F0000 - 2F7FFF
D
SA125
32K
3B0000 - 3B7FFF
C
SA102
32K
2F8000 - 2FFFFF
D
SA126
32K
3B8000 - 3BFFFF
D
SA103
32K
300000 - 307FFF
D
SA127
32K
3C0000 - 3C7FFF
D
SA104
32K
308000 - 30FFFF
D
SA128
32K
3C8000 - 3CFFFF
D
SA105
32K
310000 - 317FFF
D
SA129
32K
3D0000 - 3D7FFF
D
SA106
32K
318000 - 31FFFF
D
SA130
32K
3D8000 - 3DFFFF
D
SA107
32K
320000 - 327FFF
D
SA131
32K
3E0000 - 3E7FFF
D
SA108
32K
328000 - 32FFFF
D
SA132
32K
3E8000 - 3EFFFF
D
SA109
32K
330000 - 337FFF
D
SA133
32K
3F0000 - 3F7FFF
D
SA110
32K
338000 - 33FFFF
D
SA134
32K
3F8000 - 3FFFFF
D
SA111
32K
340000 - 347FFF
AT49SN6416(T)/3208(T)
1605C–FLASH–03/02
AT49SN6416(T)/3208(T)
Memory Organization – AT49SN6416T
Memory Organization – AT49SN6416T (Continued)
x16
Plane
Sector
x16
Size (Words)
Address Range (A21 - A0)
Plane
Sector
Size (Words)
Address Range (A21 - A0)
168000 - 16FFFF
D
SA0
32K
00000 - 07FFF
C
SA45
32K
D
SA1
32K
08000 - 0FFFF
C
SA46
32K
170000 - 177FFF
D
SA2
32K
10000 - 17FFF
C
SA47
32K
178000 - 17FFFF
D
SA3
32K
18000 - 1FFFF
C
SA48
32K
180000 - 187FFF
D
SA4
32K
20000 - 27FFF
C
SA49
32K
188000 - 18FFFF
D
SA5
32K
28000 - 2FFFF
C
SA50
32K
190000 - 197FFF
D
SA6
32K
30000 - 37FFF
C
SA51
32K
198000 - 19FFFF
D
SA7
32K
38000 - 3FFFF
C
SA52
32K
1A0000 - 1A7FFF
D
SA8
32K
40000 - 47FFF
C
SA53
32K
1A8000 - 1AFFFF
D
SA9
32K
48000 - 4FFFF
C
SA54
32K
1B0000 - 1B7FFF
D
SA10
32K
50000 - 57FFF
C
SA55
32K
1B8000 - 1BFFFF
D
SA11
32K
58000 - 5FFFF
C
SA56
32K
1C0000 - 1C7FFF
D
SA12
32K
60000 - 67FFF
C
SA57
32K
1C8000 - 1CFFFF
D
SA13
32K
68000 - 6FFFF
C
SA58
32K
1D0000 - 1D7FFF
D
SA14
32K
70000 - 77FFF
C
SA59
32K
1D8000 - 1DFFFF
D
SA15
32K
78000 - 7FFFF
C
SA60
32K
1E0000 - 1E7FFF
D
SA16
32K
80000 - 87FFF
C
SA61
32K
1E8000 - 1EFFFF
D
SA17
32K
88000 - 8FFFF
C
SA62
32K
1F0000 - 1F7FFF
D
SA18
32K
90000 - 97FFF
C
SA63
32K
1F8000 - 1FFFFF
D
SA19
32K
98000 - 9FFFF
B
SA64
32K
200000 - 207FFF
D
SA20
32K
A0000 - A7FFF
B
SA65
32K
208000 - 20FFFF
D
SA21
32K
A8000 - AFFFF
B
SA66
32K
210000 - 217FFF
D
SA22
32K
B0000 - B7FFF
B
SA67
32K
218000 - 21FFFF
D
SA23
32K
B8000 - BFFFF
B
SA68
32K
220000 - 227FFF
D
SA24
32K
C0000 - C7FFF
B
SA69
32K
228000 - 22FFFF
D
SA25
32K
C8000 - CFFFF
B
SA70
32K
230000 - 237FFF
D
SA26
32K
D0000 - D7FFF
B
SA71
32K
238000 - 23FFFF
D
SA27
32K
D8000 - DFFFF
B
SA72
32K
240000 - 247FFF
D
SA28
32K
E0000 - E7FFF
B
SA73
32K
248000 - 24FFFF
D
SA29
32K
E8000 - EFFFF
B
SA74
32K
250000 - 257FFF
D
SA30
32K
F0000 - F7FFF
B
SA75
32K
258000 - 25FFFF
D
SA31
32K
F8000 - FFFFF
B
SA76
32K
260000 - 267FFF
C
SA32
32K
100000 - 107FFF
B
SA77
32K
268000 - 26FFFF
C
SA33
32K
108000 - 10FFFF
B
SA78
32K
270000 - 277FFF
C
SA34
32K
110000 - 117FFF
B
SA79
32K
278000 - 27FFFF
C
SA35
32K
118000 - 11FFFF
B
SA80
32K
280000 - 287FFF
C
SA36
32K
120000 - 127FFF
B
SA81
32K
288000 - 28FFFF
C
SA37
32K
128000 - 12FFFF
B
SA82
32K
290000 - 297FFF
C
SA38
32K
130000 - 137FFF
B
SA83
32K
298000 -29FFFF
C
SA39
32K
138000 - 13FFFF
B
SA84
32K
2A0000 - 2A7FFF
C
SA40
32K
140000 - 147FFF
B
SA85
32K
2A8000 - 2AFFFF
C
SA41
32K
148000 - 14FFFF
B
SA86
32K
2B0000 - 2B7FFF
C
SA42
32K
150000 - 157FFF
B
SA87
32K
2B8000 - 2BFFFF
C
SA43
32K
158000 - 15FFFF
B
SA88
32K
2C0000 - 2C7FFF
C
SA44
32K
160000 - 167FFF
B
SA89
32K
2C8000 - 2CFFFF
B
SA90
32K
2D0000 - 2D7FFF
21
1605C–FLASH–03/02
Memory Organization – AT49SN6416T (Continued)
Memory Organization – AT49SN6416T (Continued)
x16
x16
Plane
B
22
Sector
SA91
Size (Words)
Address Range (A21 - A0)
Plane
Sector
Size (Words)
Address Range (A21 - A0)
32K
2D8000 - 2DFFFF
A
SA112
32K
380000 - 387FFF
SA113
32K
388000 - 38FFFF
B
SA92
32K
2E0000 - 2E7FFF
A
B
SA93
32K
2E8000 - 2EFFFF
A
SA114
32K
390000 - 397FFF
B
SA94
32K
2F0000 - 2F7FFF
A
SA115
32K
398000 - 39FFFF
B
SA95
32K
2F8000 - 2FFFFF
A
SA116
32K
3A0000 - 3A7FFF
A
SA96
32K
300000 - 307FFF
A
SA117
32K
3A8000 - 3AFFFF
A
SA97
32K
308000 - 30FFFF
A
SA118
32K
3B0000 - 3B7FFF
A
SA98
32K
310000 - 317FFF
A
SA119
32K
3B8000 - 3BFFFF
SA120
32K
3C0000 - 3C7FFF
3C8000 - 3CFFFF
A
SA99
32K
318000 - 31FFFF
A
A
SA100
32K
320000 - 327FFF
A
SA121
32K
A
SA101
32K
328000 - 32FFFF
A
SA122
32K
3D0000 - 3D7FFF
SA123
32K
3D8000 - 3DFFFF
A
SA102
32K
330000 - 337FFF
A
A
SA103
32K
338000 - 33FFFF
A
SA124
32K
3E0000 - 3E7FFF
A
SA104
32K
340000 - 347FFF
A
SA125
32K
3E8000 - 3EFFFF
A
SA105
32K
348000 - 34FFFF
A
SA126
32K
3F0000 - 3F7FFF
A
SA106
32K
350000 - 357FFF
A
SA127
4K
3F8000 - 3F8FFF
A
SA107
32K
358000 - 35FFFF
A
SA128
4K
3F9000 - 3F9FFF
A
SA108
32K
360000 - 367FFF
A
SA129
4K
3FA000 - 3FAFFF
A
SA109
32K
368000 - 36FFFF
A
SA130
4K
3FB000 - 3FBFFF
A
SA110
32K
370000 - 377FFF
A
SA131
4K
3FC000 - 3FCFFF
A
SA111
32K
378000 - 37FFFF
A
SA132
4K
3FD000 - 3FDFFF
A
SA133
4K
3FE000 - 3FEFFF
A
SA134
4K
3FF000 - 3FFFFF
AT49SN6416(T)/3208(T)
1605C–FLASH–03/02
AT49SN6416(T)/3208(T)
DC and AC Operating Range
AT49SN6416(T)/3208(T) - 90
Operating
Temperature (Case)
Industrial
-40°C - 85°C
VCC Power Supply
1.65V - 1.95V
Operating Modes
WE
RESET
VPP(6)
Ai
I/O
VIL
VIH
VIH
X
Ai
DOUT
VIL
VIL
VIH
VIH
X
Ai
DOUT
Program/Erase(3)
VIL
VIH
VIL
VIH
VIHPP(7)
Ai
DIN
Standby/Program
Inhibit
VIH
X(1)
X
VIH
X
X
High Z
X
X
VIH
VIH
X
X
VIL
X
VIH
X
X
X
X
X
VILPP(8)
Output Disable
X
VIH
X
VIH
X
Reset
X
X
X
VIL
X
Mode
CE
Read
VIL
Burst Read
Program Inhibit
OE
High Z
X
High Z
A1 - A21 = VIL, A9 = VH(3), A0 = VIL
Manufacturer
Code(4)
A1 - A21 = VIL, A9 = VH(3), A0 = VIH
Device Code(4)
A0 = V IL, A1 - A21 = V IL
Manufacturer
Code(4)
A0 = VIH, A1 - A21 = VIL
Device Code(4)
Product Identification
Hardware
VIL
Software(5)
Notes:
VIL
VIH
VIH
VIH
1. X can be VIL or VIH.
2. Refer to AC programming waveforms.
3. VH = 12.0V ± 0.5V.
4. Manufacturer Code: 001FH; Device Code: 00DB – AT49SN3208; 00D1 – AT49SN3208T; 00DC - AT49SN6416;
00D8H - AT49SN6416T.
5. See details under “Software Product Identification Entry/Exit” on page 32.
6. The VPP pin can be tied to VCC. For faster program/erase operations, VPP can be set to 12.0V ± 0.5V.
7. VIHPP (min) = 1.2V.
8. VILPP (max) = 0.8V.
23
1605C–FLASH–03/02
DC Characteristics
Symbol
Parameter
Condition
ILI
Input Load Current
ILO
Max
Units
VIN = 0V to VCC
1
µA
Output Leakage Current
VI/O = 0V to VCC
1
µA
ISB1
V CC Standby Current CMOS
CE = V CCQ - 0.3V to VCC
10
µA
ICC(1)
V CC Active Current
f = 54 MHz; IOUT = 0 mA
30
mA
ICCRE
V CC Read While Erase Current
f = 54 MHz; IOUT = 0 mA
50
mA
ICCRW
V CC Read While Write Current
f = 54 MHz; IOUT = 0 mA
50
mA
VIL
Input Low Voltage
0.4
V
VIH
Input High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage
Note:
Min
V CCQ - 0.4
V
0.1
0.25
IOL = 100 µA
IOL = 2.1 mA
IOH = -100 µA
V CCQ - 0.1
IOH = -400 µA
1.4
V
V
1. In the erase mode, ICC is 30 mA.
Input Test Waveforms and Measurement Level
1.4V
AC
DRIVING
LEVELS
0.9V
AC
MEASUREMENT
LEVEL
0.4V
tR, tF < 5 ns
Output Test Load
VCCQ
1.8K
OUTPUT
PIN
1.3K
30 pF
Pin Capacitance
f = 1 MHz, T = 25°C(1)
CIN
COUT
Note:
24
Typ
Max
Units
Conditions
4
6
pF
VIN = 0V
8
12
pF
VOUT = 0V
1. This parameter is characterized and is not 100% tested.
AT49SN6416(T)/3208(T)
1605C–FLASH–03/02
AT49SN6416(T)/3208(T)
AC Asynchronous Read Timing Characteristics
Symbol
Parameter
Max
Units
tACC1
Access, AVD To Data Valid
Min
90
ns
tACC2
Access, Address to Data Valid
90
ns
tCE
Access, CE to Data Valid
90
ns
45
ns
tOE
OE to Data Valid
tAHAV
Address Hold from AVD
9
ns
tAVLP
AVD Low Pulse Width
10
ns
tAVHP
AVD High Pulse Width
10
ns
tAAV
Address Valid to AVD
10
tDF
CE, OE High to Data Float
tRO
RESET to Output Delay
ns
25
ns
150
ns
AVD Pulsed Asynchronous Read Cycle Waveform(1)(2)
tCE
CE
tDF
DATA VALID
I/O0-I/O15
tACC2
tDF
A0 -A21
tAAV
tAVHP
(1)
tAHAV
AVD
tAVLP
tACC1
tOE
OE
tRO
RESET
Notes:
1. After the high-to-low transition on AVD, AVD may remain low as long as the address is stable.
2. CLK may be static high or static low.
Asynchronous Read Cycle Waveform(1)(2)(3)(4)
tRC
A0 - A21
ADDRESS VALID
CE
tCE
tOE
OE
tDF
tOH
tACC2
tRO
RESET
I/O0 - I/O15
Notes:
HIGH Z
OUTPUT
VALID
1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC.
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC.
3. tDF is specified from OE or CE, whichever occurs first (CL = 5 pF).
4. AVD and CLK should be tied low.
25
1605C–FLASH–03/02
AC Asynchronous Read Timing Characteristics
Symbol
Parameter
tACC1
Min
Max
Units
Access, AVD To Data Valid
90
ns
tACC2
Access, Address to Data Valid
90
ns
tCE
Access, CE to Data Valid
90
ns
tOE
OE to Data Valid
45
ns
tAHAV
Address Hold from AVD
9
ns
tAVLP
AVD Low Pulse Width
10
ns
tAVHP
AVD High Pulse Width
10
ns
tAAV
Address Valid to AVD
10
ns
tDF
CE, OE High to Data Float
tRO
RESET to Output Delay
tPAA
Page Address Access Time
25
ns
150
ns
20
ns
Page Read Cycle Waveform 1(1)(2)
tCE
CE
tDF
I/O0-I/O15
DATA VALID
tACC2
tDF
(2)
A2 -A21
tAAV
tAHAV
tPAA
tACC2
(2)
A0 -A1
tAAV
tAVHP
(1)
tAHAV
AVD
tAVLP
tACC1
tOE
OE
tRO
RESET
Notes:
1. After the high-to-low transition on AVD, AVD may remain low as long as the page address is stable.
2. The diagram shown is for a four-word page read. For an eight-word page read A0 - A1 becomes A0 - A2 and A2 - A21
becomes A3 - A21.
Page Read Cycle Waveform 2(1)(2)
tCE
CE
tDF
I/O0-I/O15
DATA VALID
tACC2
tDF
(2)
A2 -A21
tPAA
tACC2
(2)
A0 -A1
(1)
AVD
VIL
tOE
OE
tRO
RESET
Notes:
26
1. AVD may remain low as long as the page address is stable.
2. The diagram shown is for a four-word page read. For an eight-word page read A0 - A1 becomes A0 - A2 and A2 - A21
becomes A3 - A21.
AT49SN6416(T)/3208(T)
1605C–FLASH–03/02
AT49SN6416(T)/3208(T)
AC Burst Read Timing Characteristics
Symbol
Parameter
Min
Max
Units
tCLK
CLK Period
18.5
ns
tCKH
CLK High Time
4
ns
tCKL
CLK Low Time
4
ns
tCKRT
CLK Rise Time
5
ns
tCKFT
CLK Fall Time
5
ns
tACK
Address Valid to Clock
7
ns
tAVCK
AVD Low to Clock
7
ns
tCECK
CE Low to Clock
7
ns
tCKAV
Clock to AVD High
3
ns
tQHCK
Output Hold from Clock
5
ns
tAHCK
Address Hold from Clock
10
ns
tCKRY
Clock to RDY Delay
tCEAV
CE Setup to AVD
10
ns
tAAV
Address Valid to AVD
10
ns
tAHAV
Address Hold From AVD
9
ns
tCKQV
CLK to Data Delay
tCEQZ
CE High to Output High-Z
13.5
ns
13.5
ns
10
ns
Burst Read Cycle Waveform
tCLK
...
...
...
CLK
tCKH
tCKL
tAHCK
tCECK
CE
tCE
tCEAV
tAVCK
(2)
AVD
tACK
tCKAV
tAAV
I/O0-I/O15
tCKQV
tAHAV
tCEQZ
tQHCK
D0
D1
... D126
D127
D128 D129
A0-A21
OE
tCKRY
RDY
Notes:
tCKRY
(1)
1. The RDY signal (solid line) shown is for a burst configuration register setting of B10 and B8 = 0. The RDY Signal (dashed
line) shown is for a burst configuration setting of B10 = 1 and B8 = 0.
2. After the high-to-low transition on AVD, AVD may remain low.
27
1605C–FLASH–03/02
Burst Read Waveform (Clock Latency of 4)
B
A
D
C
F
E
G
...
CLK
CE
AVD
OE
VALID
A0-A21
D0
I/O0-I/O15
RDY
Note:
D1 ...
D126
D127
D128
D129
(1)
1. Solid line reflects a B10 and B8 setting of 0 in the configuration register. Dashed line reflects a B10 setting of 0 and B8 setting of 1 in the configuration register.
Four-word Burst Read Waveform (Clock Latency of 4)
A
B
C
CLK
CE
AVD
OE
A0-A21
VALID
I/O0-I/O15
28
D0
D1
D2
D3
AT49SN6416(T)/3208(T)
1605C–FLASH–03/02
AT49SN6416(T)/3208(T)
AC Word Load Characteristics 1
Symbol
Parameter
tAS
Address, CE Setup Time to AVD High
10
ns
tAHAV
Address Hold Time from AVD High
9
ns
tAVLP
AVD Low Pulse Width
10
ns
tDS
Data Setup Time
15
ns
tDH
Data Hold Time
0
ns
tCEAV
CE Setup to AVD
10
ns
tWP
CE or WE Low Pulse Width
70
ns
tWPH
CE or WE High Pulse Width
25
ns
tWEAV
WE High Time to AVD Low
25
ns
25
ns
tCEAV
Min
CE High Time to AVD Low
Max
Units
AC Word Load Waveforms 1
WE Controlled(1)
CE
I/O0-I/O15
DATA VALID
A0 -A21
tAS
tAHAV
AVD
tDS
tAVLP
tDH
tWEAV
tWP
WE
Note:
1. After the high-to-low transition on AVD, AVD may remain low as long as the CLK input does not toggle.
CE Controlled(1)
WE
I/O0-I/O15
DATA VALID
A0 -A21
tAS
tAHAV
AVD
tDS
tAVLP
tCEAV
CE
Note:
tWP
tDH
tCEAV
1. After the high-to-low transition on AVD, AVD may remain low as long as the CLK input does not toggle.
29
1605C–FLASH–03/02
AC Word Load Characteristics 2
Symbol
Parameter
Min
Max
Units
tAS
Address Setup Time to WE and CE Low
0
ns
tAH
Address Hold Time
20
ns
tDS
Data Setup Time
20
ns
tDH
Data Hold Time
0
ns
tWP
CE or WE Low Pulse Width
35
ns
tWPH
CE or WE High Pulse Width
25
ns
AC Word Load Waveforms 2
WE Controlled(1)
CE
I/O0-I/O15
DATA VALID
A0 -A21
tDS
tDH
tAH
tAS
tWP
WE
AVD
VIL
Note:
1. The CLK input should not toggle.
CE Controlled(1)
WE
I/O0-I/O15
DATA VALID
A0 -A21
tDS
tAS
tDH
tAH
CE
tWP
AVD
VIL
Note:
30
1. The CLK input should not toggle.
AT49SN6416(T)/3208(T)
1605C–FLASH–03/02
AT49SN6416(T)/3208(T)
Program Cycle Characteristics
Symbol
Parameter
Min
Typ
Max
Units
tBP
Word Programming Time (V pp = VCC)
22
µs
tBPVPP
Word Programming Time (V PP > 11.5V)
10
µs
tSEC1
Sector Erase Cycle Time (4K word sectors)
100
ms
tSEC2
Sector Erase Cycle Time (32K word sectors)
500
ms
tES
Erase Suspend Time
15
µs
tPS
Program Suspend Time
10
µs
Program Cycle Waveforms
OE(1)
CE
XXAA
I/O0 -I/O15
XX55
555
A0 -A21
AAA
INPUT
DATA
XXA0
555
ADDR
AVD
WE
Sector, Plane or Chip Erase Cycle Waveforms
OE(1)
CE
XXAA
I/O0 -I/O15
A0 -A21
555
XX55
AAA
555
555
Note3
XX55
XXAA
XX80
AAA
Note2
AVD
WE
Notes:
1. OE must be high only when WE and CE are both low.
2. For chip erase, the address should be 555. For plane or sector erase, the address depends on what plane or sector is to be
erased. (See note 3 and 5 under Command Definitions on page 13.)
3. For chip erase, the data should be XX10H, for plane erase, the data should be XX20H, and for sector erase, the data should
be XX30H
4. The waveforms shown above use the WE controlled AC Word Load Waveforms 1.
31
1605C–FLASH–03/02
Data Polling Characteristics
Symbol
Parameter
tDH
Data Hold Time
tOEH
OE Hold Time
tOE
OE to Output Delay
tWR
Notes:
Min
Typ
Max
Units
10
ns
10
ns
(2)
ns
Write Recovery Time
0
ns
1. These parameters are characterized and not 100% tested.
2. See tOE spec in page 25.
Data Polling Waveforms
WE
CE
OE
I/O7
A0-A21
Toggle Bit Characteristics(1)
Symbol
Parameter
tDH
Data Hold Time
tOEH
OE Hold Time
Min
Typ
Max
Units
10
ns
10
ns
(2)
tOE
OE to Output Delay
tOEHP
OE High Pulse
50
ns
Write Recovery Time
0
ns
tWR
Notes:
ns
1. These parameters are characterized and not 100% tested.
2. See tOE spec in page 25.
Toggle Bit Waveforms(1)(2)(3)
Notes:
32
1. Toggling either OE or CE or both OE and CE will operate toggle bit.
The tOEHP specification must be met by the toggling input(s).
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
AT49SN6416(T)/3208(T)
1605C–FLASH–03/02
AT49SN6416(T)/3208(T)
Software Product Identification
Entry(1)
LOAD DATA AA
TO
ADDRESS 555
LOAD DATA 55
TO
ADDRESS AAA
Software Product Identification Exit(1)(6)
LOAD DATA AA
TO
ADDRESS 555
LOAD DATA 55
TO
ADDRESS AAA
OR
LOAD DATA F0
TO
ANY ADDRESS
EXIT PRODUCT
IDENTIFICATION
MODE(4)
LOAD DATA F0
TO
ADDRESS 555
LOAD DATA 90
TO
ADDRESS xxx(7)
EXIT PRODUCT
IDENTIFICATION
MODE(4)
ENTER PRODUCT
IDENTIFICATION
MODE(2)(3)(5)
Notes:
1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex) Address Format: A11 - A0 (Hex); A12 - A21 (Don’t Care).
2. A1 - A21 = V IL.
Manufacturer Code is read for A0 = VIL;
Device Code is read for A0 = VIH.
3. The device does not remain in identification mode if powered down.
4. The device returns to standard operation mode.
5. Manufacturer Code: 001FH
Device Code: 00DB - AT49SN3208; 00D1 - AT49SN3208T;
00DC - AT49SN6416; 00D8H - AT49SN6416T.
6. Either one of the Product ID Exit commands can be used.
7. For the AT49SN3208:
For the AT49SN3208T:
xxx = 0XX555 Status Read from Plane A
xxx = 1XX555 Status Read from Plane B
xxx = 1XX555 Status Read from Plane A
xxx = 0XX555 Status Read from Plane B
For the AT49SN6416:
xxx = 0XX555 Status Read from Plane A
xxx = 1XX555 Status Read from Plane B
xxx = 2XX555 Status Read from Plane C
xxx = 3XX555 Status Read from Plane D
For the AT49SN6416T:
xxx = 3XX555 Status Read from Plane A
xxx = 2XX555 Status Read from Plane B
xxx = 1XX555 Status Read from Plane C
xxx = 0XX555 Status Read from Plane D
If a read status has been entered for a plane, any read from this plane will be a status read while any read of another plane
will be a memory read, either random or burst. Program or erase operations cannot be performed while one of the planes is
in the read status mode.
33
1605C–FLASH–03/02
Table 5. Common Flash Interface Definition for AT49SN6416(T)/3208(T)
34
Address
AT49SN3208(T)
AT49SN6416(T)
Comments
10h
0051h
0051h
“Q”
11h
0052h
0052h
“R”
12h
0059h
0059h
“Y”
13h
0002h
0002h
14h
0000h
0000h
15h
0041h
0041h
16h
0000h
0000h
17h
0000h
0000h
18h
0000h
0000h
19h
0000h
0000h
1Ah
0000h
0000h
1Bh
0016h
0016h
VCC min write/erase
1Ch
0019h
0019h
VCC max write/erase
1Dh
00B5h
00B5h
VPP min voltage
1Eh
00C5h
00C5h
VPP max voltage
1Fh
0004h
0004h
Typ word write – 16 µs
20h
0000h
0000h
21h
0009h
0009h
Typ block erase – 500 ms
22h
000Fh
0010h
Typ chip erase, 32M bytes – 32,300 ms, 64M bytes – 64,300 ms
23h
0004h
0004h
Max word write/typ time
24h
0000h
0000h
n/a
25h
0003h
0003h
Max block erase/typ block erase
26h
0003h
0003h
Max chip erase/ typ chip erase
27h
0016h
0017h
Device size
28h
0001h
0001h
x16 device
29h
0000h
0000h
x16 device
2Ah
0000h
0000h
Multiple byte write not supported
2Bh
0000h
0000h
Multiple byte write not supported
2Ch
0002h
0002h
2 regions, x = 2
2Dh
003Eh
007Eh
64K bytes, 32M – Y = 62, 64M – Y = 126
2Eh
0000h
0000h
64K bytes, 32M – Y = 62, 64M – Y = 126
2Fh
0000h
0000h
64K bytes, Z = 256
30h
0001h
0001h
64K bytes, Z = 256
31h
0007h
0007h
8K bytes, Y = 7
32h
0000h
0000h
8K bytes, Y = 7
33h
0020h
0020h
8K bytes, Z = 32
34h
0000h
0000h
8K bytes, Z = 32
AT49SN6416(T)/3208(T)
1605C–FLASH–03/02
AT49SN6416(T)/3208(T)
Table 5. Common Flash Interface Definition for AT49SN6416(T)/3208(T) (Continued)
Address
AT49SN3208(T)
AT49SN6416(T)
Comments
VENDOR SPECIFIC EXTENDED QUERY
41h
0050h
0050h
“P”
42h
0052h
0052h
“R”
43h
0049h
0049h
“I”
44h
0031h
0031h
Major version number, ASCII
45h
0030h
0030h
Minor version number, ASCII
46h
00BFh
00BFh
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
47h
0000h
AT49SN3208T or
0001h
AT49SN3208
0000h
AT49SN6416T or
0001h
AT49SN6416
48h
0007h
0007h
Bit 0 – 4 word linear burst with wrap around, 0 – no, 1 – yes
Bit 1 – 8 word linear burst with wrap around, 0 – no, 1 – yes
Bit 2 – continuos burst undefined bits are “0”
49h
0003h
0003h
Bit 0 – 4 word page, 0 – no, 1 – yes
Bit 1 – 8 word page, 0 – no, 1 – yes
Undefined bits are “0”
4Ah
0080h
0080h
Location of protection register lock byte, the section's first byte
4Bh
0003h
0003h
# of bytes in the factory prog section of prot register – 2*n
4Ch
0003h
0003h
# of bytes in the user prog section of prot register – 2*n
– chip erase supported, 0 – no, 1 – yes
– erase suspend supported, 0 – no, 1 – yes
– program suspend supported, 0 – no, 1 – yes
– simultaneous operations supported, 0 – no, 1 – yes
– burst mode read supported, 0 – no, 1 – yes
– page mode read supported, 0 – no, 1 – yes
– queued erase supported, 0 – no, 1 – yes
– protection bits supported, 0 – no, 1 – yes
Bit 8 – top (“0”) or bottom (“1”) boot block device undefined bits are “0”
35
1605C–FLASH–03/02
AT49SN6416(T) Ordering Information
ICC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
Operation Range
90
25
0.01
AT49SN6416-90CI
55C1
Industrial
(-40° to 85°C)
90
25
0.01
AT49SN6416T-90CI
55C1
Industrial
(-40° to 85°C)
Package Type
55C1
36
55-ball, Plastic Chip-size Ball Grid Array Package (CBGA)
AT49SN6416(T)/3208(T)
1605C–FLASH–03/02
AT49SN6416(T)/3208(T)
Packaging Information – AT49SN6416(T)
55C1 – CBGA
D
0.12 C
C Seating Plane
E
Side View
A1
Top View
A
D1
1.375 mm Ref
8 7
6
5
4
3
2 1
COMMON DIMENSIONS
(Unit of Measure = mm)
A
B
C
E1
D
SYMBOL
MIN
NOM
MAX
A
–
–
1.00
F
A1
0.23
–
–
G
D
7.90
8.00
8.10
E
e
D1
3.25 mm Ref
e
Øb
Bottom View
E
NOTE
5.25 TYP
10.90
11.00
E1
4.50 TYP
e
0.75 TYP
Øb
0.35 TYP
11.10
3/20/02
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
55C1, 55-ball (8 x 7 Array), 8 x 11 x 1.0 mm Body, 0.75 mm Ball Pitch
Ceramic Ball Grid Array Package (CBGA)
DRAWING NO.
55C1
REV.
A
37
1605C–FLASH–03/02
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Printed on recycled paper.
1605C–FLASH–03/02
xM