ETC AT49BV640(T)

Features
• 64-megabit (4M x 16) Flash Memory
• 2.7V - 3.6V Read/Write
• High Performance
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– Asynchronous Access Time – 70 ns
– Page Mode Read Time – 20 ns
Sector Erase Architecture
– Eight 4K Word Sectors with Individual Write Lockout
– 32K Word Main Sectors with Individual Write Lockout
Typical Sector Erase Time: 32K Word Sectors – 500 ms; 4K Word Sectors – 100 ms
Suspend/Resume Feature for Erase and Program
– Supports Reading and Programming Data from Any Sector by Suspending Erase
of a Different Sector
– Supports Reading Any Word by Suspending Programming of Any Other Word
Low-power Operation
– 30 mA Active
– 10 µA Standby
1.8V I/O Option Reduces Overall System Power
Data Polling and Toggle Bit for End of Program Detection
VPP Pin for Write Protection and Accelerated Program/Erase Operations
RESET Input for Device Initialization
TSOP or CBGA Package
Top or Bottom Boot Block Configuration Available
128-bit Protection Register
Common Flash Interface (CFI)
64-megabit
(4M x 16)
Page Mode
2.7-volt Flash
Memory
AT49BV640
AT49BV640T
Description
The AT49BV640(T) is a 2.7-volt 64-megabit Flash memory. The memory is divided
into multiple sectors for erase operations. The device can be read or reprogrammed
off a single 2.7V power supply, making it ideally suited for in-system programming.
The output voltage can be separately controlled down to 1.65V through the VCCQ
supply pin. This device can operate in the asynchronous or page read mode.
Preliminary
To increase the flexibility of the device, it contains an Erase Suspend and Program
Suspend feature. This feature will put the erase or program on hold for any amount of
time and let the user read data from or program data to any of the remaining sectors.
The end of a program or an erase cycle is detected by Data Polling or the toggle bit.
The VPP pin provides data protection and faster programming and erase times. When
the VPP input is below 0.8V, the program and erase functions are inhibited. When VPP
is at 1.65V or above, normal program and erase operations can be performed. With
VPP at 12.0V, the program and erase operations are accelerated.
With VPP at 12V, a six-byte command (Enter Single Pulse Program Mode) to remove
the requirement of entering the three-byte program sequence is offered to further
improve programming time. After entering the six-byte code, only single pulses on the
write control lines are required for writing into the device. This mode (Single Pulse
Word Program) is exited by powering down the device, by taking the RESET pin to
GND or by a high-to-low transition on the VPP input. Erase, Erase Suspend/Resume,
Program Suspend/Resume and Read Reset commands will not work while in this
mode; if entered they will result in data being programmed into the device. It is not recommended that the six-byte code reside in the software of the final product but only
exist in external programming code.
Rev. 3366B–FLASH–8/03
1
Pin Configurations
AT49BV640(T)
TSOP Top View
Type 1
Pin Name
Pin Function
I/O0 - I/O15
Data Inputs/Outputs
A0 - A21
Addresses
CE
Chip Enable
OE
Output Enable
WE
Write Enable
RESET
Reset
WP
Write Protect
VPP
Write Protection and Power Supply for
Accelerated Program/Erase Operations
VCCQ
Output Power Supply
AT49BV640(T)
CBGA Top View
1
2
3
4
5
6
7
8
A13
A11
A8
VPP
WP
A19
A7
A4
A14
A10
WE
RST
A18
A17
A5
A2
A15
A12
A9
A21
A20
A6
A3
A1
A16
I/O14
I/O5
I/O11
I/O2
I/O8
CE
A0
VCCQ I/O15
I/O6
I/O12
I/O3
I/O9
I/O0
GND
I/O7
I/O13
I/O4
VCC
I/O10
I/O1
OE
A
B
A15
A14
A13
A12
A11
A10
A9
A8
A21
A20
WE
RESET
VPP
WP
A19
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
VCCQ
GND
I/O15
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
VCC
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
GND
CE
A0
C
D
E
F
GND
2
AT49BV640(T)
3366B–FLASH–8/03
AT49BV640(T)
Device Operation
COMMAND SEQUENCES: The device powers on in the read mode. Command
sequences are used to place the device in other operating modes such as program and
erase. After the completion of a program or an erase cycle, the device enters the read
mode. The command sequences are written by applying a low pulse on the WE input
with CE low and OE high or by applying a low-going pulse on the CE input with WE low
and OE high. The address is latched on the falling edge of the WE or CE pulse whichever occurs first. Valid data is latched on the rising edge of the WE or the CE pulse,
whichever occurs first. The addresses used in the command sequences are not affected
by entering the command sequences.
ASYNCHRONOUS READ: The AT49BV640(T) is accessed like an EPROM. When CE
and OE are low and WE is high, the data stored at the memory location determined by
the address pins are asserted on the outputs. The outputs are put in the high impedance
state whenever CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention.
PAGE READ: The page read operation of the device is controlled by CE and OE inputs.
The page size is four words. The first word access of the page read is the same as the
asynchronous read. The first word is read at an asynchronous speed of 80 ns. Once the
first word is read, toggling A0 and A1 will result in subsequent reads within the page
being output at a speed of 20 ns. The page read diagram is shown on page 20.
RESET: A RESET input pin is provided to ease some system applications. When
RESET is at a logic high level, the device is in its standard operating mode. A low level
on the RESET pin halts the present device operation and puts the outputs of the device
in a high-impedance state. When a high level is reasserted on the RESET pin, the
device returns to read or standby mode, depending upon the state of the control pins.
ERASE: Before a word can be reprogrammed it must be erased. The erased state of
the memory bits is a logical “1”. The entire memory can be erased by using the Chip
Erase command or individual sectors can be erased by using the Sector Erase
command.
CHIP ERASE: Chip Erase is a six-bus cycle operation. The automatic erase begins on
the rising edge of the last WE pulse. Chip Erase does not alter the data of the protected
sectors. After the full chip erase the device will return back to the read mode. The hardware reset during Chip Erase will stop the erase but the data will be of unknown state.
Any command during Chip Erase except Erase Suspend will be ignored.
SECTOR ERASE: As an alternative to a full chip erase, the device is organized into
multiple sectors that can be individually erased. The Sector Erase command is a six-bus
cycle operation. The sector whose address is valid at the sixth falling edge of WE will be
erased provided the given sector has not been protected.
WORD PROGRAMMING: The device is programmed on a word-by-word basis. Programming is accomplished via the internal device command register and is a four-bus
cycle operation. The programming address and data are latched in the fourth cycle. The
device will automatically generate the required internal programming pulses. Please
note that a “0” cannot be programmed back to a “1”; only erase operations can convert
“0”s to “1”s.
FLEXIBLE SECTOR PROTECTION: The AT49BV640(T) offers two sector protection
modes, the Softlock and the Hardlock. The Softlock mode is optimized as sector protection for sectors whose content changes frequently. The Hardlock protection mode is
recommended for sectors whose content changes infrequently. Once either of these two
modes is enabled, the contents of the selected sector is read-only and cannot be erased
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3366B–FLASH–8/03
or programmed. Each sector can be independently programmed for either the Softlock
or Hardlock sector protection mode. At power-up and reset, all sectors have their Softlock protection mode enabled.
SOFTLOCK AND UNLOCK: The Softlock protection mode can be disabled by issuing a
two-bus cycle Unlock command to the selected sector. Once a sector is unlocked, its
contents can be erased or programmed. To enable the Softlock protection mode, a sixbus cycle Softlock command must be issued to the selected sector.
HARDLOCK AND WRITE PROTECT (WP): The Hardlock sector protection mode operates in conjunction with the Write Protection (WP) pin. The Hardlock sector protection
mode can be enabled by issuing a six-bus cycle Hardlock software command to the
selected sector. The state of the Write Protect pin affects whether the Hardlock protection mode can be overridden.
• When the WP pin is low and the Hardlock protection mode is enabled, the sector
cannot be unlocked and the contents of the sector is read-only.
• When the WP pin is high, the Hardlock protection mode is overridden and the sector
can be unlocked via the Unlock command.
To disable the Hardlock sector protection mode, the chip must be either reset or power
cycled.
Table 1. Hardlock and Softlock Protection Configurations in Conjunction with WP
WP
Hard
lock
Soft
lock
Erase/
Prog
Allowed?
VCC/5V
0
0
0
Yes
No sector is locked
VCC/5V
0
0
1
No
Sector is Softlocked. The
Unlock command can unlock
the sector.
VCC/5V
0
1
1
No
Hardlock protection mode is
enabled. The sector cannot
be unlocked.
VPP
Comments
VCC/5V
1
0
0
Yes
No sector is locked.
VCC/5V
1
0
1
No
Sector is Softlocked. The
Unlock command can unlock
the sector.
VCC/5V
1
1
0
Yes
Hardlock protection mode is
overridden and the sector is
not locked.
VCC/5V
1
1
1
No
Hardlock protection mode is
overridden and the sector
can be unlocked via the
Unlock command.
VIL
x
x
x
No
Erase and Program
Operations cannot be
performed.
SECTOR PROTECTION DETECTION: A software method is available to determine if
the sector protection Softlock or Hardlock features are enabled. When the device is in
the software product identification mode (see Software Product Identification Entry and
Exit sections) a read from the I/O0 and I/O1 at address location 00002H within a sector
will show if the sector is unlocked, softlocked, or hardlocked.
4
AT49BV640(T)
3366B–FLASH–8/03
AT49BV640(T)
Table 2. Sector Protection Status
I/O1
I/O0
Sector Protection Status
0
0
Sector Not Locked
0
1
Softlock Enabled
1
0
Hardlock Enabled
1
1
Both Hardlock and Softlock Enabled
PROGRAM/ERASE STATUS: The device provides several bits to determine the status
of a program or erase operation: I/O2, I/O3, I/O5, I/O6, and I/O7. All other status bits are
don’t care. The Table 4 on page 25 and the following four sections describe the function
of these bits. To provide greater flexibility for system designers, the AT49BV640(T) contains a programmable configuration register. The configuration register allows the user
to specify the status bit operation. The configuration register can be set to one of two different values, “00” or “01”. If the configuration register is set to “00”, the part will
automatically return to the read mode after a successful program or erase operation. If
the configuration register is set to a “01”, a Product ID Exit command must be given after
a successful program or erase operation before the part will return to the read mode. It
is important to note that whether the configuration register is set to a “00” or to a “01”,
any unsuccessful program or erase operation requires using the Product ID Exit command to return the device to read mode. The default value (after power-up) for the
configuration register is “00”. Using the four-bus cycle set configuration register command as shown in the Command Definition table on page 11, the value of the
configuration register can be changed. Voltages applied to the reset pin will not alter the
value of the configuration register. The value of the configuration register will affect the
operation of the I/O7 status bit as described below.
DATA POLLING: The AT49BV640(T) features Data Polling to indicate the end of a program cycle. If the status configuration register is set to a “00”, during a program cycle an
attempted read of the last word loaded will result in the complement of the loaded data
on I/O7. Once the program cycle has been completed, true data is valid on all outputs
and the next cycle may begin. During a chip erase or sector erase operation, an attempt
to read the device will give a “0” on I/O7. Once the program or erase cycle has completed, true data will be read from the device. Data Polling may begin at any time during
the program cycle. Please see Table 3 on page 10 for more details.
If the status bit configuration register is set to a “01”, the I/O7 status bit will be low while
the device is actively programming or erasing data. I/O7 will go high when the device
has completed a program or erase operation. Once I/O7 has gone high, status information on the other pins can be checked.
The Data Polling status bit must be used in conjunction with the erase/program and VPP
status bit as shown in the algorithm in Figures 2 and 3.
TOGGLE BIT: In addition to Data Polling, the AT49BV640(T) provides another method
for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the memory will result in I/O6 toggling
between one and zero. Once the program cycle has completed, I/O6 will stop toggling
and valid data will be read. Examining the toggle bit may begin at any time during a program cycle. Please see Table 3 on page 10 for more details.
The toggle bit status bit should be used in conjunction with the erase/program and VPP
status bit as shown in the algorithm in Figures 4 and 5 on page 9.
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3366B–FLASH–8/03
ERASE/PROGRAM STATUS BIT: The device offers a status bit on I/O5 that indicates
whether the program or erase operation has exceeded a specified internal pulse count
limit. If the status bit is a “1”, the device is unable to verify that an erase or a word program operation has been successfully performed. The device may also output a “1” on
I/O5 if the system tries to program a “1” to a location that was previously programmed to
a “0”. Only an erase operation can change a “0” back to a “1”. If a program (Sector
Erase) command is issued to a protected sector, the protected sector will not be programmed (erased). The device will go to a status read mode and the I/O5 status bit will
be set high, indicating the program (erase) operation did not complete as requested.
Once the erase/program status bit has been set to a “1”, the system must write the
Product ID Exit command to return to the read mode. The erase/program status bit is a
“0” while the erase or program operation is still in progress. Please see Table 3 on page
10 for more details.
VPP STATUS BIT: The AT49BV640(T) provides a status bit on I/O3 that provides information regarding the voltage level of the VPP pin. During a program or erase operation,
if the voltage on the VPP pin is not high enough to perform the desired operation successfully, the I/O3 status bit will be a “1”. Once the VPP status bit has been set to a “1”,
the system must write the Product ID Exit command to return to the read mode. On the
other hand, if the voltage level is high enough to perform a program or erase operation
successfully, the VPP status bit will output a “0”. Please see Table 3 on page 10 for more
details.
ERASE SUSPEND/ERASE RESUME: The Erase Suspend command allows the system to interrupt a sector erase operation and then program or read data from a different
sector. After the Erase Suspend command is given, the device requires a maximum
time of 15 µs to suspend the erase operation. The system can then read data or program data to any other sector within the device. An address is not required during the
Erase Suspend command. During a sector erase suspend, another sector cannot be
erased. To resume the sector erase operation, the system must write the Erase Resume
command. The Erase Resume command is a one-bus cycle command, which does
require the sector address. The device also supports an erase suspend during a complete chip erase. While the chip erase is suspended, the user can read from any sector
within the memory that is protected. The command sequence for a chip erase suspend
and a sector erase suspend are the same.
PROGRAM SUSPEND/PROGRAM RESUME: The Program Suspend command allows
the system to interrupt a programming operation and then read data from a different
word within the memory. After the Program Suspend command is given, the device
requires a maximum of 10 µs to suspend the programming operation. After the programming operation has been suspended, the system can then read from any other word
within the device. An address is not required during the program suspend operation. To
resume the programming operation, the system must write the Program Resume command. The program suspend and resume are one-bus cycle commands. The command
sequence for the erase suspend and program suspend are the same, and the command
sequence for the erase resume and program resume are the same.
128-BIT PROTECTION REGISTER: The AT49BV640(T) contains a 128-bit register that
can be used for security purposes in system design. The protection register is divided
into two 64-bit blocks. The two blocks are designated as block A and block B. The data
in block A is non-changeable and is programmed at the factory with a unique number.
The data in block B is programmed by the user and can be locked out such that data in
the block cannot be reprogrammed. To program block B in the protection register, the
four-bus cycle Program Protection Register command must be used as shown in the
Command Definition in Hex table on page 11. To lock out block B, the four-bus cycle
lock protection register command must be used as shown in the Command Definition in
6
AT49BV640(T)
3366B–FLASH–8/03
AT49BV640(T)
Hex table. Data bit D1 must be zero during the fourth bus cycle. All other data bits during
the fourth bus cycle are don’t cares. To determine whether block B is locked out, the
Product ID Entry command is given followed by a read operation from address 80H. If
data bit D1 is zero, block B is locked. If data bit D1 is one, block B can be reprogrammed. Please see the Protection Register Addressing Table on page 12 for the
address locations in the protection register. To read the protection register, the Product
ID Entry command is given followed by a normal read operation from an address within
the protection register. After determining whether block B is protected or not or reading
the protection register, the Product ID Exit command must be given prior to performing
any other operation.
CFI: Common Flash Interface (CFI) is a published, standardized data structure that
may be read from a flash device. CFI allows system software to query the installed
device to determine the configurations, various electrical and timing parameters, and
functions supported by the device. CFI is used to allow the system to learn how to interface to the flash device most optimally. The two primary benefits of using CFI are ease
of upgrading and second source availability. The command to enter the CFI Query
mode is a one-bus cycle command which requires writing data 98h to address 55h. The
CFI Query command can be written when the device is ready to read data or can also
be written when the part is in the product ID mode. Once in the CFI Query mode, the
system can read CFI data at the addresses given in Table 4 on page 25. To exit the CFI
Query mode, the product ID exit command must be given. If the CFI Query command is
given while the part is in the product ID mode, then the product ID exit command must
first be given to return the part to the product ID mode. Once in the product ID mode, it
will be necessary to give another product ID exit command to return the part to the read
mode.
HARDWARE DATA PROTECTION: Hardware features protect against inadvertent programs to the AT49BV640(T) in the following ways: (a) VCC sense: if VCC is below 1.8V
(typical), the program function is inhibited. (b) V CC power-on delay: once VCC has
reached the V CC sense level, the device will automatically time-out 10 ms (typical)
before programming. (c) Program inhibit: holding any one of OE low, CE high or WE
high inhibits program cycles. (d) Noise filter: pulses of less than 15 ns (typical) on the
WE or CE inputs will not initiate a program cycle. (e) VPP is less than VILPP.
INPUT LEVELS: While operating with a 2.7V to 3.6V power supply, the address inputs
and control inputs (OE, CE and WE) may be driven from 0 to 5.5V without adversely
affecting the operation of the device. The I/O lines can be driven from 0 to VCCQ + 0.6V.
OUTPUT LEVELS: For the AT49BV640(T), output high levels are equal to VCCQ - 0.1V
(not VCC). For 2.7V to 3.6V output levels, VCCQ must be tied to VCC.
7
3366B–FLASH–8/03
Figure 1. Data Polling Algorithm
(Configuration Register = 00)
Figure 2. Data Polling Algorithm
(Configuration Register = 01)
START
START
Read I/O7 - I/O0
Addr = VA
Read I/O7 - I/O0
Addr = VA
NO
YES
I/O7 = 1?
I/O7 = Data?
YES
NO
NO
I/O3, I/O5 = 1?
I/O3, I/O5 = 1?
YES
YES
Read I/O7 - I/O0
Addr = VA
I/O7 = Data?
Notes:
8
Program/Erase
Operation Not
Successful, Write
Product ID
Exit Command
YES
NO
Program/Erase
Operation Not
Successful, Write
Product ID
Exit Command
NO
Note:
Program/Erase
Operation
Successful,
Device in
Read Mode
Program/Erase
Operation
Successful,
Write Product ID
Exit Command
1. VA = Valid address for programming. During a sector
erase operation, a valid address is any sector address
within the sector being erased. During chip erase, a
valid address is any non-protected sector address.
1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector
address within the sector being erased. During
chip erase, a valid address is any non-protected
sector address.
2. I/O7 should be rechecked even if I/O5 = “1”
because I/O7 may change simultaneously with
I/O5.
AT49BV640(T)
3366B–FLASH–8/03
AT49BV640(T)
Figure 4. Toggle Bit Algorithm
(Configuration Register = 01)
Figure 3. Toggle Bit Algorithm
(Configuration Register = 00)
START
START
Read I/O7 - I/O0
Read I/O7 - I/O0
Read I/O7 - I/O0
Read I/O7 - I/O0
Toggle Bit =
Toggle?
Toggle Bit =
Toggle?
NO
YES
YES
NO
NO
I/O3, I/O5 = 1?
Read I/O7 - I/O0
Twice
Read I/O7 - I/O0
Twice
Toggle Bit =
Toggle?
NO
Note:
NO
YES
YES
Program/Erase
Operation Not
Successful, Write
Product ID
Exit Command
I/O3, I/O5 = 1?
YES
YES
Toggle Bit =
Toggle?
NO
Program/Erase
Operation Not
Successful, Write
Product ID
Exit Command
Program/Erase
Operation
Successful,
Device in
Read Mode
1. The system should recheck the toggle bit even if
I/O5 = “1” because the toggle bit may stop toggling
as I/O5 changes to “1”.
Note:
Program/Erase
Operation
Successful,
Write Product ID
Exit Command
1. The system should recheck the toggle bit even if I/O5 =
“1” because the toggle bit may stop toggling as I/O5
changes to “1”.
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3366B–FLASH–8/03
Table 3. Status Bit Table
Status Bit
I/O7
I/O7
I/O6
I/O5(1)
I/O3(2)
I/O2
00
01
00/01
00/01
00/01
00/01
I/O7
0
TOGGLE
0
0
1
Erasing
0
0
TOGGLE
0
0
TOGGLE
Erase Suspended & Read
Erasing Sector
1
1
1
0
0
TOGGLE
Erase Suspended & Read
Non-erasing Sector
DATA
DATA
DATA
DATA
DATA
DATA
Erase Suspended & Program
Non-erasing Sector
I/O7
0
TOGGLE
0
0
TOGGLE
Erase Suspended & Program
Suspended and Reading from
Non-suspended Sectors
DATA
DATA
DATA
DATA
DATA
DATA
Program Suspended & Read
Non-suspended Word
DATA
DATA
DATA
DATA
DATA
DATA
Configuration Register
Programming
Notes:
10
1. I/O5 switches to a “1” when a program or an erase operation has exceeded the maximum time limits or when a program or
sector erase operation is performed on a protected sector.
2. I/O3 switches to a “1” when the VPP level is not high enough to successfully perform program and erase operations.
AT49BV640(T)
3366B–FLASH–8/03
AT49BV640(T)
Command Definition in (Hex)(1)
1st Bus
Cycle
Bus
Cycles
Addr
Data
Read
1
Addr
DOUT
Chip Erase
6
555
AA
Command Sequence
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
6th Bus
Cycle
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
AAA(2)
55
555
80
555
AA
AAA
55
555
10
Sector Erase
6
555
AA
AAA
55
555
80
555
AA
Word Program
4
555
AA
AAA
55
555
A0
Addr
DIN
Enter Single-pulse Program
Mode
6
555
AA
AAA
55
555
80
555
Single-pulse Word Program
Mode
1
Addr
DIN
Sector Softlock
6
555
AA
AAA
55
555
80
(4)
70
55
555
80
(4)
AAA
55
SA
AA
AAA
55
555
A0
555
AA
AAA
55
SA(4)
40
555
AA
AAA
55
SA(4)(5)
60
Sector Unlock
2
555
AA
SA
Sector Hardlock
6
555
AA
AAA
Erase/Program Suspend
1
xxx
B0
Erase/Program Resume
1
SA(4)
30
Product ID Entry
3
555
AA
AAA
55
555
90
Product ID Exit(3)
3
555
AA
AAA
55
555
F0
Product ID Exit(3)
1
xxx
FX
Program Protection
Register – Block B
4
555
AA
AAA
55
555
C0
Addr
DIN
Lock Protection
Register – Block B
4
555
AA
AAA
55
555
C0
080
X0
Status of Block B
Protection
4
555
AA
AAA
55
555
90
80
DOUT(6)
Set Configuration Register
4
555
AA
AAA
55
555
E0
xxx
00/01(7)
CFI Query
1
X55
98
Notes:
5th Bus
Cycle
30
1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex). The ADDRESS FORMAT in each bus cycle
is as follows: A11 - A0 (Hex), A11 - A21 (Don’t Care).
2. Since A11 is a Don’t Care, AAA can be replaced with 2AA.
3. Either one of the Product ID Exit commands can be used.
4. SA = sector address. Any word address within a sector can be used to designate the sector address (see pages 13 - 17 for details).
5. Once a sector is in the Hardlock protection mode, it cannot be disabled unless the chip is reset or power cycled.
6. If data bit D1 is “0”, block B is locked. If data bit D1 is “1”, block B can be reprogrammed.
7. The default state (after power-up) of the configuration register is “00”.
11
3366B–FLASH–8/03
Absolute Maximum Ratings*
*NOTICE:
Temperature under Bias ................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages Except VPP
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
VPP Input Voltage
with Respect to Ground ......................................... 0V to 13.0V
All Output Voltages
with Respect to Ground ...........................-0.6V to VCCQ + 0.6V
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Protection Register Addressing Table
Word
Use
Block
A7
A6
A5
A4
A3
A2
A1
A0
0
Factory
A
1
0
0
0
0
0
0
1
1
Factory
A
1
0
0
0
0
0
1
0
2
Factory
A
1
0
0
0
0
0
1
1
3
Factory
A
1
0
0
0
0
1
0
0
4
User
B
1
0
0
0
0
1
0
1
5
User
B
1
0
0
0
0
1
1
0
6
User
B
1
0
0
0
0
1
1
1
7
User
B
1
0
0
0
1
0
0
0
Note:
12
1. All address lines not specified in the above table must be 0 when accessing the Protection Register, i.e., A21 - A8 = 0.
AT49BV640(T)
3366B–FLASH–8/03
AT49BV640(T)
Memory Organization – AT49BV640
Memory Organization – AT49BV640 (Continued)
x16
x16
Size
(Words)
Address Range
(A21 - A0)
SA0
4K
00000 - 00FFF
SA45
32K
130000 - 137FFF
SA1
4K
01000 - 01FFF
SA46
32K
138000 - 13FFFF
SA2
4K
02000 - 02FFF
SA47
32K
140000 - 147FFF
SA3
4K
03000 - 03FFF
SA48
32K
148000 - 14FFFF
SA4
4K
04000 - 04FFF
SA49
32K
150000 - 157FFF
SA5
4K
05000 - 05FFF
SA50
32K
158000 - 15FFFF
SA6
4K
06000 - 06FFF
SA51
32K
160000 - 167FFF
SA7
4K
07000 - 07FFF
SA52
32K
168000 - 16FFFF
SA8
32K
08000 - 0FFFF
SA53
32K
170000 - 177FFF
SA9
32K
10000 - 17FFF
SA54
32K
178000 - 17FFFF
SA10
32K
18000 - 1FFFF
SA55
32K
180000 - 187FFF
SA11
32K
20000 - 27FFF
SA56
32K
188000 - 18FFFF
SA12
32K
28000 - 2FFFF
SA57
32K
190000 - 197FFF
SA13
32K
30000 - 37FFF
SA58
32K
198000 - 19FFFF
SA14
32K
38000 - 3FFFF
SA59
32K
1A0000 - 1A7FFF
1A8000 - 1AFFFF
Sector
Sector
Size
(Words)
Address Range
(A21 - A0)
SA15
32K
40000 - 47FFF
SA60
32K
SA16
32K
48000 - 4FFFF
SA61
32K
1B0000 - 1B7FFF
SA17
32K
50000 - 57FFF
SA62
32K
1B8000 - 1BFFFF
SA18
32K
58000 - 5FFFF
SA63
32K
1C0000 - 1C7FFF
SA19
32K
60000 - 67FFF
SA64
32K
1C8000 - 1CFFFF
SA20
32K
68000 - 6FFFF
SA65
32K
1D0000 - 1D7FFF
SA21
32K
70000 - 77FFF
SA66
32K
1D8000 - 1DFFFF
SA22
32K
78000 - 7FFFF
SA67
32K
1E0000 - 1E7FFF
SA23
32K
80000 - 87FFF
SA68
32K
1E8000 - 1EFFFF
SA24
32K
88000 - 8FFFF
SA69
32K
1F0000 - 1F7FFF
SA25
32K
90000 - 97FFF
SA70
32K
1F8000 - 1FFFFF
SA26
32K
98000 - 9FFFF
SA71
32K
200000 - 207FFF
SA27
32K
A0000 - A7FFF
SA72
32K
208000 - 20FFFF
SA28
32K
A8000 - AFFFF
SA73
32K
210000 - 217FFF
SA29
32K
B0000 - B7FFF
SA74
32K
218000 - 21FFFF
SA30
32K
B8000 - BFFFF
SA75
32K
220000 - 227FFF
SA31
32K
C0000 - C7FFF
SA76
32K
228000 - 22FFFF
SA32
32K
C8000 - CFFFF
SA77
32K
230000 - 237FFF
SA33
32K
D0000 - D7FFF
SA78
32K
238000 - 23FFFF
SA34
32K
D8000 - DFFFF
SA79
32K
240000 - 247FFF
SA35
32K
E0000 - E7FFF
SA80
32K
248000 - 24FFFF
SA36
32K
E8000 - EFFFF
SA81
32K
250000 - 257FFF
SA37
32K
F0000 - F7FFF
SA82
32K
258000 - 25FFFF
SA38
32K
F8000 - FFFFF
SA83
32K
260000 - 267FFF
SA39
32K
100000 - 107FFF
SA84
32K
268000 - 26FFFF
SA40
32K
108000 - 10FFFF
SA85
32K
270000 - 277FFF
SA41
32K
110000 - 117FFF
SA86
32K
278000 - 27FFFF
SA42
32K
118000 - 11FFFF
SA87
32K
280000 - 287FFF
SA43
32K
120000 - 127FFF
SA88
32K
288000 - 28FFFF
SA44
32K
128000 - 12FFFF
SA89
32K
290000 - 297FFF
13
3366B–FLASH–8/03
Memory Organization – AT49BV640 (Continued)
Memory Organization – AT49BV640 (Continued)
x16
x16
Size
(Words)
Address Range
(A21 - A0)
Sector
SA90
32K
298000 - 29FFFF
SA113
32K
350000 - 357FFF
SA91
32K
2A0000 - 2A7FFF
SA114
32K
358000 - 35FFFF
SA92
32K
2A8000 - 2AFFFF
SA115
32K
360000 - 367FFF
SA93
32K
2B0000 - 2B7FFF
SA116
32K
368000 - 36FFFF
SA94
32K
2B8000 - 2BFFFF
SA117
32K
370000 - 377FFF
SA95
32K
2C0000 - 2C7FFF
SA118
32K
378000 - 37FFFF
SA96
32K
2C8000 - 2CFFFF
SA119
32K
380000 - 387FFF
SA97
32K
2D0000 - 2D7FFF
SA120
32K
388000 - 38FFFF
SA98
32K
2D8000 - 2DFFFF
SA121
32K
390000 - 397FFF
SA99
32K
2E0000 - 2E7FFF
SA122
32K
398000 - 39FFFF
SA100
32K
2E8000 - 2EFFFF
SA123
32K
3A0000 - 3A7FFF
SA101
32K
2F0000 - 2F7FFF
SA124
32K
3A8000 - 3AFFFF
SA102
32K
2F8000 - 2FFFFF
SA125
32K
3B0000 - 3B7FFF
SA103
32K
300000 - 307FFF
SA126
32K
3B8000 - 3BFFFF
SA104
32K
308000 - 30FFFF
SA127
32K
3C0000 - 3C7FFF
SA105
32K
310000 - 317FFF
SA128
32K
3C8000 - 3CFFFF
SA106
32K
318000 - 31FFFF
SA129
32K
3D0000 - 3D7FFF
SA107
32K
320000 - 327FFF
SA130
32K
3D8000 - 3DFFFF
SA108
32K
328000 - 32FFFF
SA131
32K
3E0000 - 3E7FFF
SA109
32K
330000 - 337FFF
SA132
32K
3E8000 - 3EFFFF
SA110
32K
338000 - 33FFFF
SA133
32K
3F0000 - 3F7FFF
SA111
32K
340000 - 347FFF
SA134
32K
3F8000 - 3FFFFF
SA112
32K
348000 - 34FFFF
Sector
14
Size
(Words)
Address Range
(A21 - A0)
AT49BV640(T)
3366B–FLASH–8/03
AT49BV640(T)
Memory Organization – AT49BV640T (Continued)
Memory Organization – AT49BV640T
x16
x16
Sector
Size
(Words)
Address Range
(A21 - A0)
Sector
Size
(Words)
Address Range
(A21 - A0)
168000 - 16FFFF
SA0
32K
00000 - 07FFF
SA45
32K
SA1
32K
08000 - 0FFFF
SA46
32K
170000 - 177FFF
32K
178000 - 17FFFF
SA2
32K
10000 - 17FFF
SA47
SA3
32K
18000 - 1FFFF
SA48
32K
180000 - 187FFF
188000 - 18FFFF
SA4
32K
20000 - 27FFF
SA49
32K
SA5
32K
28000 - 2FFFF
SA50
32K
190000 - 197FFF
32K
198000 - 19FFFF
SA6
32K
30000 - 37FFF
SA51
SA7
32K
38000 - 3FFFF
SA52
32K
1A0000 - 1A7FFF
SA8
32K
40000 - 47FFF
SA53
32K
1A8000 - 1AFFFF
SA9
32K
48000 - 4FFFF
SA54
32K
1B0000 - 1B7FFF
SA10
32K
50000 - 57FFF
SA55
32K
1B8000 - 1BFFFF
SA11
32K
58000 - 5FFFF
SA56
32K
1C0000 - 1C7FFF
SA12
32K
60000 - 67FFF
SA57
32K
1C8000 - 1CFFFF
68000 - 6FFFF
SA58
32K
1D0000 - 1D7FFF
1D8000 - 1DFFFF
SA13
32K
SA14
32K
70000 - 77FFF
SA59
32K
SA15
32K
78000 - 7FFFF
SA60
32K
1E0000 - 1E7FFF
32K
1E8000 - 1EFFFF
SA16
32K
80000 - 87FFF
SA61
SA17
32K
88000 - 8FFFF
SA62
32K
1F0000 - 1F7FFF
SA18
32K
90000 - 97FFF
SA63
32K
1F8000 - 1FFFFF
SA19
32K
98000 - 9FFFF
SA64
32K
200000 - 207FFF
208000 - 20FFFF
SA20
32K
A0000 - A7FFF
SA65
32K
SA21
32K
A8000 - AFFFF
SA66
32K
210000 - 217FFF
32K
218000 - 21FFFF
SA22
32K
B0000 - B7FFF
SA67
SA23
32K
B8000 - BFFFF
SA68
32K
220000 - 227FFF
SA24
32K
C0000 - C7FFF
SA69
32K
228000 - 22FFFF
SA25
32K
C8000 - CFFFF
SA70
32K
230000 - 237FFF
32K
238000 - 23FFFF
SA26
32K
D0000 - D7FFF
SA71
SA27
32K
D8000 - DFFFF
SA72
32K
240000 - 247FFF
SA28
32K
E0000 - E7FFF
SA73
32K
248000 - 24FFFF
SA29
32K
E8000 - EFFFF
SA74
32K
250000 - 257FFF
SA30
32K
F0000 - F7FFF
SA75
32K
258000 - 25FFFF
SA31
32K
F8000 - FFFFF
SA76
32K
260000 - 267FFF
32K
268000 - 26FFFF
SA32
32K
100000 - 107FFF
SA77
SA33
32K
108000 - 10FFFF
SA78
32K
270000 - 277FFF
278000 - 27FFFF
SA34
32K
110000 - 117FFF
SA79
32K
SA35
32K
118000 - 11FFFF
SA80
32K
280000 - 287FFF
32K
288000 - 28FFFF
290000 - 297FFF
SA36
32K
120000 - 127FFF
SA81
SA37
32K
128000 - 12FFFF
SA82
32K
SA38
32K
130000 - 137FFF
SA83
32K
298000 -29FFFF
32K
2A0000 - 2A7FFF
2A8000 - 2AFFFF
SA39
32K
138000 - 13FFFF
SA84
SA40
32K
140000 - 147FFF
SA85
32K
SA41
32K
148000 - 14FFFF
SA86
32K
2B0000 - 2B7FFF
32K
2B8000 - 2BFFFF
SA42
32K
150000 - 157FFF
SA87
SA43
32K
158000 - 15FFFF
SA88
32K
2C0000 - 2C7FFF
SA44
32K
160000 - 167FFF
SA89
32K
2C8000 - 2CFFFF
15
3366B–FLASH–8/03
Memory Organization – AT49BV640T (Continued)
Memory Organization – AT49BV640T (Continued)
x16
x16
Size
(Words)
Address Range
(A21 - A0)
SA90
32K
2D0000 - 2D7FFF
SA91
32K
2D8000 - 2DFFFF
SA92
32K
2E0000 - 2E7FFF
SA115
32K
398000 - 39FFFF
SA93
32K
2E8000 - 2EFFFF
SA116
32K
3A0000 - 3A7FFF
SA94
32K
2F0000 - 2F7FFF
SA117
32K
3A8000 - 3AFFFF
SA95
32K
2F8000 - 2FFFFF
SA118
32K
3B0000 - 3B7FFF
Sector
Sector
Size
(Words)
Address Range
(A21 - A0)
SA113
32K
388000 - 38FFFF
SA114
32K
390000 - 397FFF
SA96
32K
300000 - 307FFF
SA119
32K
3B8000 - 3BFFFF
SA97
32K
308000 - 30FFFF
SA120
32K
3C0000 - 3C7FFF
32K
3C8000 - 3CFFFF
SA98
32K
310000 - 317FFF
SA121
SA99
32K
318000 - 31FFFF
SA122
32K
3D0000 - 3D7FFF
SA100
32K
320000 - 327FFF
SA123
32K
3D8000 - 3DFFFF
SA101
32K
328000 - 32FFFF
SA124
32K
3E0000 - 3E7FFF
SA102
32K
330000 - 337FFF
SA125
32K
3E8000 - 3EFFFF
SA103
32K
338000 - 33FFFF
SA126
32K
3F0000 - 3F7FFF
SA104
32K
340000 - 347FFF
SA127
4K
3F8000 - 3F8FFF
SA105
32K
348000 - 34FFFF
SA128
4K
3F9000 - 3F9FFF
SA106
32K
350000 - 357FFF
SA129
4K
3FA000 - 3FAFFF
SA107
32K
358000 - 35FFFF
SA130
4K
3FB000 - 3FBFFF
SA108
32K
360000 - 367FFF
SA131
4K
3FC000 - 3FCFFF
SA109
32K
368000 - 36FFFF
SA132
4K
3FD000 - 3FDFFF
SA110
32K
370000 - 377FFF
SA133
4K
3FE000 - 3FEFFF
SA111
32K
378000 - 37FFFF
SA134
4K
3FF000 - 3FFFFF
SA112
32K
380000 - 387FFF
16
AT49BV640(T)
3366B–FLASH–8/03
AT49BV640(T)
DC and AC Operating Range
Operating
Temperature (Case)
AT49BV640(T) - 70
AT49BV640(T) - 85
-40°C - 85°C
-40°C - 85°C
2.7V - 3.6V
2.7V - 3.6V
Industrial
VCC Power Supply
Operating Modes
Mode
CE
Read
VIL
VIL
Burst Read
WE
RESET
VPP(5)
Ai
I/O
VIL
VIH
VIH
X
Ai
DOUT
VIL
VIH
VIH
X
Ai
DOUT
Ai
DIN
X
High Z
OE
Program/Erase
VIL
VIH
VIL
VIH
VIHPP(6)
Standby/Program
Inhibit
VIH
X(1)
X
VIH
X
X
X
VIH
VIH
X
X
VIL
X
VIH
X
X
X
X
X
VILPP(7)
Output Disable
X
VIH
X
VIH
X
Reset
X
X
X
VIL
X
(3)
Program Inhibit
High Z
X
High Z
A0 = VIL, A1 - A21 = VIL
Manufacturer
Code(3)
A0 = VIH, A1 - A21 = VIL
Device Code(3)
Product Identification
Software(4)
Notes:
VIH
1. X can be VIL or VIH.
2.
3.
4.
5.
6.
7.
Refer to AC programming waveforms.
Manufacturer Code: 001FH; Device Code: 00D6H - AT49BV640; 00D2H - AT49BV640T.
See details under “Software Product Identification Entry/Exit” on page 24.
The VPP pin can be tied to VCC. For faster program/erase operations, VPP can be set to 12.0V ± 0.5V.
VIHPP (min) = 1.65V.
VILPP (max) = 0.8V.
17
3366B–FLASH–8/03
DC Characteristics
Symbol
Parameter
Condition
ILI
Input Load Current
ILO
Max
Units
VIN = 0V to VCC
1
µA
Output Leakage Current
VI/O = 0V to VCC
1
µA
ISB1
VCC Standby Current CMOS
CE = VCCQ - 0.3V to VCC
10
µA
ICC(1)
VCC Active Current
f = 5 MHz; IOUT = 0 mA
30
mA
ICCRE
VCC Read While Erase Current
f = 5 MHz; IOUT = 0 mA
50
mA
ICCRW
VCC Read While Write Current
f = 5 MHz; IOUT = 0 mA
50
mA
VIL
Input Low Voltage
0.6
V
VIH
Input High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage
Note:
Min
VCCQ - 0.6
IOL = 2.1 mA
V
0.45
IOH = -100 µA; VCCQ = 1.65V - 2.2V
VCCQ - 0.1
IOH = -400 µA; VCCQ = 2.7V - 3.1V
2.4
V
V
1. In the erase mode, ICC is 30 mA.
Input Test Waveforms and Measurement Level
2.0V
AC
DRIVING
LEVELS
1.5V
AC
MEASUREMENT
LEVEL
0.6V
tR, tF < 5 ns
Output Test Load
VCCQ
1.8K
OUTPUT
PIN
1.3K
30 pF
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Typ
Max
Units
Conditions
CIN
4
6
pF
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
18
1. This parameter is characterized and is not 100% tested.
AT49BV640(T)
3366B–FLASH–8/03
AT49BV640(T)
AC Asynchronous Read Timing Characteristics
AT49BV640(T)-70
Symbol
Parameter
Min
tACC
Access, Address to Data Valid
tCE
Access, CE to Data Valid
AT49BV640(T)-85
Max
Min
Max
Units
70
85
ns
70
85
ns
tOE
OE to Data Valid
20
20
ns
tDF
CE, OE High to Data Float
25
25
ns
tRO
RESET to Output Delay
150
150
ns
Asynchronous Read Cycle Waveform(1)(2)(3)
tRC
A0 - A21
ADDRESS VALID
CE
tCE
tOE
OE
tDF
tOH
tACC
tRO
RESET
I/O0 - I/O15
Notes:
HIGH Z
OUTPUT
VALID
1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC.
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC.
3. tDF is specified from OE or CE, whichever occurs first (CL = 5 pF).
19
3366B–FLASH–8/03
AC Asynchronous Read Timing Characteristics
AT49BV640(T)-70
Symbol
Parameter
Min
tACC
Access, Address to Data Valid
tCE
Access, CE to Data Valid
tOE
Max
AT49BV640(T)-85
Min
Max
Units
70
85
ns
70
85
ns
OE to Data Valid
20
20
ns
tDF
CE, OE High to Data Float
25
25
ns
tRO
RESET to Output Delay
150
150
ns
tPAA
Page Address Access Time
20
20
ns
Page Read Cycle Waveform
tCE
CE
tDF
I/O0-I/O15
DATA VALID
tACC
tDF
A2 -A21
tPAA
tACC
A0 -A1
tOE
OE
tRO
RESET
20
AT49BV640(T)
3366B–FLASH–8/03
AT49BV640(T)
AC Word Load Characteristics
Symbol
Parameter
Min
Max
Units
tAS
Address Setup Time to WE and CE Low
0
ns
tAH
Address Hold Time
20
ns
tDS
Data Setup Time
20
ns
tDH
Data Hold Time
0
ns
tWP
CE or WE Low Pulse Width
35
ns
tWPH
CE or WE High Pulse Width
25
ns
AC Word Load Waveforms
WE Controlled
CE
I/O0-I/O15
DATA VALID
A0 -A21
tDS
tDH
tAH
tAS
tWP
WE
CE Controlled
WE
I/O0-I/O15
DATA VALID
A0 -A21
tDS
tAS
CE
tDH
tAH
tWP
21
3366B–FLASH–8/03
Program Cycle Characteristics
Symbol
Parameter
Min
Typ
Max
Units
tBP
Word Programming Time (Vpp = VCC)
22
µs
tBPVPP
Word Programming Time (VPP > 11.5V)
10
µs
tSEC1
Sector Erase Cycle Time (4K word sectors)
100
ms
tSEC2
Sector Erase Cycle Time (32K word sectors)
500
ms
tES
Erase Suspend Time
15
µs
tPS
Program Suspend Time
10
µs
Program Cycle Waveforms
OE(1)
CE
XXAA
I/O0 -I/O15
XX55
555
A0 -A21
AAA
INPUT
DATA
XXA0
555
ADDR
WE
Sector or Chip Erase Cycle Waveforms
OE(1)
CE
XXAA
I/O0 -I/O15
A0 -A21
555
XX55
AAA
555
555
Note3
XX55
XXAA
XX80
AAA
Note2
WE
Notes:
22
1. OE must be high only when WE and CE are both low.
2. For chip erase, the address should be 555. For sector erase, the address depends on what sector is to be erased. (See note
4 under Command Definitions on page 11.)
3. For chip erase, the data should be XX10H and for sector erase, the data should be XX30H
4. The waveforms shown above use the WE controlled AC Word Load Waveforms.
AT49BV640(T)
3366B–FLASH–8/03
AT49BV640(T)
Data Polling Characteristics
Symbol
Parameter
Min
tDH
Data Hold Time
10
ns
tOEH
OE Hold Time
10
ns
tOE
OE to Output Delay(2)
tWR
Notes:
Typ
Max
Units
ns
Write Recovery Time
0
ns
1. These parameters are characterized and not 100% tested.
2. See tOE spec on page 19.
Data Polling Waveforms
WE
CE
OE
I/O7
A0-A21
Toggle Bit Characteristics(1)
Symbol
Parameter
tDH
Data Hold Time
10
ns
tOEH
OE Hold Time
10
ns
tOE
OE to Output Delay(2)
tOEHP
OE High Pulse
50
ns
Write Recovery Time
0
ns
tWR
Notes:
Min
Typ
Max
Units
ns
1. These parameters are characterized and not 100% tested.
2. See tOE spec on page 19.
Toggle Bit Waveforms(1)(2)(3)
Notes:
1. Toggling either OE or CE or both OE and CE will operate toggle bit.
The tOEHP specification must be met by the toggling input(s).
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
23
3366B–FLASH–8/03
Software Product Identification
Entry(1)
LOAD DATA AA
TO
ADDRESS 555
LOAD DATA 55
TO
ADDRESS AAA
LOAD DATA 90
TO
ADDRESS 555
Software Product Identification Exit(1)(6)
LOAD DATA AA
TO
ADDRESS 555
LOAD DATA 55
TO
ADDRESS AAA
OR
LOAD DATA F0
TO
ANY ADDRESS
EXIT PRODUCT
IDENTIFICATION
MODE(4)
LOAD DATA F0
TO
ADDRESS 555
EXIT PRODUCT
IDENTIFICATION
MODE(4)
ENTER PRODUCT
IDENTIFICATION
MODE(2)(3)(5)
Notes:
24
1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex) Address Format: A11 - A0 (Hex); A12 - A21 (Don’t Care).
2. A1 - A21 = VIL.
Manufacturer Code is read for A0 = VIL;
Device Code is read for A0 = VIH.
3. The device does not remain in identification mode if powered down.
4. The device returns to standard operation mode.
5. Manufacturer Code: 001FH
Device Code: 00D6H - AT49BV640; 00D2H - AT49BV640T.
6. Either one of the Product ID Exit commands can be used.
AT49BV640(T)
3366B–FLASH–8/03
AT49BV640(T)
Table 4. Common Flash Interface Definition for AT49BV640(T)
Address
Data
Comments
10h
0051h
“Q”
11h
0052h
“R”
12h
0059h
“Y”
13h
0002h
14h
0000h
15h
0041h
16h
0000h
17h
0000h
18h
0000h
19h
0000h
1Ah
0000h
1Bh
0027h
VCC min write/erase
1Ch
0031h
VCC max write/erase
1Dh
00B5h
VPP min voltage
1Eh
00C5h
VPP max voltage
1Fh
0004h
Typ word write – 16 µs
20h
0000h
21h
0009h
Typ block erase – 500 ms
22h
0010h
Typ chip erase – 64,300 ms
23h
0004h
Max word write/typ time
24h
0000h
n/a
25h
0003h
Max block erase/typ block erase
26h
0003h
Max chip erase/ typ chip erase
27h
0017h
Device size
28h
0001h
x16 device
29h
0000h
x16 device
2Ah
0000h
Multiple byte write not supported
2Bh
0000h
Multiple byte write not supported
2Ch
0002h
2 regions, x = 2
2Dh
007Eh
64K bytes, Y = 126
2Eh
0000h
64K bytes, Y = 126
2Fh
0000h
64K bytes, Z = 256
30h
0001h
64K bytes, Z = 256
31h
0007h
8K bytes, Y = 7
32h
0000h
8K bytes, Y = 7
33h
0020h
8K bytes, Z = 32
34h
0000h
8K bytes, Z = 32
25
3366B–FLASH–8/03
Table 4. Common Flash Interface Definition for AT49BV640(T) (Continued)
Address
Data
Comments
VENDOR SPECIFIC EXTENDED QUERY
26
41h
0050h
“P”
42h
0052h
“R”
43h
0049h
“I”
44h
0031h
Major version number, ASCII
45h
0030h
Minor version number, ASCII
46h
00A7h
Bit 0 – chip erase supported, 0 – no, 1 – yes
Bit 1 – erase suspend supported, 0 – no, 1 – yes
Bit 2 – program suspend supported, 0 – no, 1 – yes
Bit 3 – simultaneous operations supported, 0 – no, 1 – yes
Bit 4 – burst mode read supported, 0 – no, 1 – yes
Bit 5 – page mode read supported, 0 – no, 1 – yes
Bit 6 – queued erase supported, 0 – no, 1 – yes
Bit 7 – protection bits supported, 0 – no, 1 – yes
47h
0000h AT49BV640T or
0001h AT49BV640
48h
0000h
Bit 0 – 4 word linear burst with wrap around, 0 – no, 1 – yes
Bit 1 – 8 word linear burst with wrap around, 0 – no, 1 – yes
Bit 2 – continuos burst, 0 – no, 1 – yes
Undefined bits are “0”
49h
0001h
Bit 0 – 4 word page, 0 – no, 1 – yes
Bit 1 – 8 word page, 0 – no, 1 – yes
Undefined bits are “0”
4Ah
0080h
Location of protection register lock byte, the section's first byte
4Bh
0003h
# of bytes in the factory prog section of prot register – 2*n
4Ch
0003h
# of bytes in the user prog section of prot register – 2*n
Bit 0 – top (“0”) or bottom (“1”) boot block device
Undefined bits are “0”
AT49BV640(T)
3366B–FLASH–8/03
AT49BV640(T)
AT49BV640(T) Ordering Information
ICC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
Operation Range
70
30
0.01
AT49BV640-70TI
AT49BV640-70CI
48T
48C18
Industrial
(-40° to 85° C)
85
30
0.01
AT49BV640-85TI
AT49BV640-85CI
48T
48C18
Industrial
(-40° to 85° C)
70
30
0.01
AT49BV640T-70TI
AT49BV640T-70CI
48T
48C18
Industrial
(-40° to 85° C)
85
30
0.01
AT49BV640T-85TI
AT49BV640T-85CI
48T
48C18
Industrial
(-40° to 85° C)
Package Type
48C18
48-ball, Plastic Chip-size Ball Grid Array Package (CBGA)
48T
48-lead, Plastic Thin Small Outline Package (TSOP)
27
3366B–FLASH–8/03
Packaging Information – AT49BV640(T)
48C18 – CBGA
E
A1 BALL ID
D
Top View
A1
A
E1
1.375 REF
e
Side View
A1 BALL CORNER
3.625 REF
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
A
E
B
MIN
NOM
MAX
7.90
8.00
8.10
E1
C
D1
D
D
5.25 TYP
10.90
D1
E
F
3.75 TYP
–
1.0
A1
0.21
–
–
b
6
5
4
3
2
11.10
–
Ø
7
11.00
A
e
8
NOTE
0.75 BSC
0.35 TYP
1
Øb
Bottom View
08/8/03
R
28
2325 Orchard Parkway
San Jose, CA 95131
TITLE
48C18, 48-ball (8 x 6 Array),0.75 mm Pitch, 8.0 x 11.0 x 1.0 mm
Chip-scale Ball Grid Array Package (CBGA)
DRAWING NO.
48C18
REV.
A
AT49BV640(T)
3366B–FLASH–8/03
AT49BV640(T)
Packaging Information – AT49BV640(T)
48T – TSOP
PIN 1
0º ~ 8º
c
Pin 1 Identifier
D1 D
L
b
e
L1
A2
E
A
GAGE PLANE
SEATING PLANE
COMMON DIMENSIONS
(Unit of Measure = mm)
A1
MIN
NOM
MAX
A
–
–
1.20
A1
0.05
–
0.15
A2
0.95
1.00
1.05
D
19.80
20.00
20.20
D1
18.30
18.40
18.50
Note 2
E
11.90
12.00
12.10
Note 2
L
0.50
0.60
0.70
SYMBOL
Notes:
1. This package conforms to JEDEC reference MO-142, Variation DD.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
L1
0.25 BASIC
b
0.17
0.22
0.27
c
0.10
–
0.21
e
NOTE
0.50 BASIC
10/18/01
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
48T, 48-lead (12 x 20 mm Package) Plastic Thin Small Outline
Package, Type I (TSOP)
DRAWING NO.
REV.
48T
B
29
3366B–FLASH–8/03
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3366B–FLASH–8/03
xM